ARTICLE IN PRESS

INTEGRATION, the VLSI journal 42 (2009) 304–311

Contents lists available at ScienceDirect

INTEGRATION, the VLSI journal

0167-92

doi:10.1

� Corr

E-m

journal homepage: www.elsevier.com/locate/vlsi

CMOS single-ended-to-differential low-noise amplifier

Tomas Carrasco Carrillo �, Jose Gabriel Macias-Montero, Aitor Osorio Martı,Javier Sieiro Cordoba, Jose Marıa Lopez-Villegas

Department of Electronics, University of Barcelona, C/Martı i Franques 1, 08028 Barcelona, Spain

a r t i c l e i n f o

Keywords:

CMOS

Low-noise amplifier (LNA)

Low-power–low-voltage

Noise optimization

RF

AmI

IEEE 802.15.4

60/$ - see front matter & 2008 Elsevier B.V. A

016/j.vlsi.2008.11.003

esponding author. Tel.: +34 93 40 39158; fax:

ail address: tcarrasco@el.ub.es (T.C. Carrillo).

a b s t r a c t

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit

has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to

minimize power consumption, active loads and currents mirrors have been replaced by optimized

inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been

carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode

S-parameters. The LNA has been implemented using a 0.35mm RFCMOS technology. Performances are a

noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180711. Regarding non-linear

behaviour, the obtained 1 dB-compression point obtained is �9.5 dB m while intermodulation intercept

point is �3 dB m, dissipating 6 mA from 1.5 V supply voltage.

& 2008 Elsevier B.V. All rights reserved.

1. Introduction

Low-noise amplifiers (LNA) are one of the key components inreceivers because it tends to dominate the sensitivity and noisefigure (NF) of the whole system [1]. This sensitivity is directlyrelated to both active and passive devices available in a giventechnology. Thus the chosen technology will have a high impacton the final specs that could be achievable. However, thespecifications of the communication standard and product costas well as small size, level of integration, power consumption areadditional constraints that will complicate the technology selec-tion process. Actually, in high performance applications, LNA noisefigures below 2 dB have been demonstrated [2–4] using integratedtechnologies such as SiGe, GaAs or improved CMOS (microma-chining, SOI, etc.).

Nonetheless there are applications where the system specifi-cations are relaxed, e.g. in wireless sensor networks, enabling theuse of conventional CMOS processes. The LNA proposed in thiswork is a part of the RF front-end receiver of a reduced functionaldevice (RFD) intended to work in compliance with the IEEE802.15.4 low-frequency band (European 868–868.6 MHz) [5]. Thekey characteristic of the standard is its protocol simplicity andflexibility providing a reliable data transfer in a short-rangeoperation (typically within a range of 10 m). A summary of themost important specifications of the standard is shown in Table 1.

Due to the final application, i.e. a wireless sensor network, theRFD units must be tiny, consume a small amount of power, and

ll rights reserved.

+34 93 40 33333.

have a very low final cost. Taking into account such constraints,RFCMOS 0.35mm is a good technology option for the implementa-tion of a complete transceiver of the RFD unit.

Once the framework, has been established, the designer mustface three challenges. First, the choice of communication systemarchitecture will have a strong influence on the possible circuittopologies of the LNA for achieving the specifications of thestandard. Second, the designer should identify and apply the bestdesign methodologies and strategies for archiving a low-voltagelow-power (LVLP) circuit. And third, once the technology hasbeen fixed, the LNA performance depends strongly on the qualityof the passives components; therefore, the designer has to be ableto evaluate their behaviour using full-wave electromagneticsimulators.

In this work, the selected transceiver architecture uses onesingle-ended antenna for both transmission and reception pathsthat are split using an external switch, as shown in Fig. 1. Tominimize the effects of the common-mode noise, e.g. digitalswitching noise, the received signal must be processed differen-tially. Therefore, this assumption points out the need of a single-ended-to-differential LNA design. Commonly, out of chip passiveBalUn has been used to convert single-ended signals to differ-ential signals. Unfortunately, it introduces losses increasing thesystem noise figure. To avoid these mentioned drawbacks, anactive topology is preferred in this work. Moreover, to compensatethe dynamic range of the complete system without increasing thetotal power consumption, a fully differential variable gainamplifier has been connected to LNA output. With this selectedarchitecture, the system specifications are translated into the LNAblock as a maximum NF of 7 dB, a minimum gain of 18 dB, and aninput intercept point to the third harmonic (IIP3) of �10 dB m.

ARTICLE IN PRESS

Table 1IEEE 802.15.4 standard specifications.

Quantity Value

Sensitivity �92 dB m

BER 6.25�10�5

Max. power input �20 dB m

Channel bandwidth 600 kHz

Fig. 1. Input and output stage of the transceiver.

Fig. 2. Schematic of a single-ended-to-differential low-noise amplifier.

Fig. 3. Schematic of a folded cascode LNA adapted to apply PCSNIM technique.

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311 305

Of course, the LNA must dissipate a lower current consump-tion. In order to accomplish this last request, the supply voltagehas been reduced to 1.5 V, considerably lower than typical value of3.3 V for a 0.35mm technology where nominal threshold voltagesare around 0.5 V. This voltage reduction supposes a clear penaltyfor the designer who has to reduce the possible number of stackedtransistor, with the corresponding reduction of some of the basicsLNA performance, e.g., gain, NF, or reverse isolation, among others.To avoid this drawback, for the first time the substitution ofresistive or active loads, as well as current mirrors by optimizedon-chip inductors and transformers [6] is proposed. Consideringthis framework, RFCMOS accurate models for such inductors andtransformers are not always available. Therefore, the designer hasto be able to evaluate the performance of these integrated passiveusing full-wave electromagnetic simulators, particularly if layoutoptimization techniques are used. This disadvantage becomes abenefit, due to the fact that the designer can obtain the bestcomponent for each application. In the work presented hereafter,the benefits translate in achieving the best resonance tank for aspecific frequency, the exact inductance value and the higherquality factor Q for a degeneration inductor beyond the inductorlibrary supplied by the foundry manufacturer. Moreover, eachinductance of the LNA has been designed to obtain the bestperformance depending on its specific application, i.e., as a load,

RF chock, AC current source, input/output matching or sourcedegeneration. It is the use of the optimizing components [7] thatallows complete monolithic integration of a compliance solution.

The schematic of the proposed LNA is shown in Fig. 2. The firststage is based on a folded cascode topology [8] that allows a low-power dissipation using a low-voltage supply. It will be explainedin Section 2 using power constraint simultaneous noise and input-matching impedance design technique (PCSNIM). The secondstage is a differential cascode structure that supports the single-ended-to-differential conversion [9]. Therefore, Section 3 estab-lishes the formalism to study three-port amplifiers, and willanalyse the designed active BalUn. In Section 4, the LNAcharacterization is presented, where measurements are comparedwith simulations. Finally, Section 5 gives the conclusions of thework.

2. First stage: single-ended LNA

The key point in the design of a LNA consists in thedetermination of suitable tradeoffs between the different circuitspecs such as NF, gain, linearity, impedance matching, and powerdissipation. Over the years, there have appeared several designtechniques for optimizing such tradeoffs. To name a fewrepresentatives, one can find the classical noise matching (CNM)technique, the simultaneous noise and input matching (SNIM) atany specified amount of power dissipation technique, the power-constrained noise optimization (PCNO) technique, and thePCSNIM technique [10].

For the design of the first stage, the PCSNIM has been selected.The PCSNIM basically consist in SNIM, but the topology includes afeedback capacitor Cd in addition to the well-known sourcedegeneration inductor LS. This is shown in Fig. 3 where a foldedcascode topology is presented in detail. The inclusion of thefeedback capacitor adds a new degree of freedom that allows theinclusion of the power constraint in the design. As it has beenreported in [10], the LNA performance parameters are given by

Zopt ¼

affiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

d5gð1�jcj2Þ

qþ j Ct

Cgsþ ajcj

ffiffiffiffid

5g

q� �

oCgsa2d

5gð1�jcj2Þ þCtCgsþ ajcj

ffiffiffiffid

5g

q� �2� �� sLS (1)

Fmin ¼ 1þ2o

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffigdð1� jcj2Þ

qoT

ffiffiffi5p (2)

ARTICLE IN PRESS

Table 2Parameter definitions.

Parameter

name

Definition

Zopt Optimum noise impedance

Fmin Noise factor minimum

Zin Input impedance

oT Cut-off frequency

gm Transconductance

Cgs Gate–source capacitance

Ct Cgs+Cd

C Noise correlation coefficient

a gm/gd0

gd0 Drain–source conductance

g Experimental parameter related to the channel thermal noise

current, for short-channel transistors it can be greater than 2

d Experimental parameter related to the channel noise current. For

short-channel transistors it can be greater than 2

5E91E8

500

1000

1500

2000

0

2500

2

4

6

8

0

10

FREQUENCY (GHz)

IMP

ED

AN

CE

(OH

M)

QU

ALI

TY F

AC

TOR

IMPEDANCE & QUALITY FACTOR

1E9

Fig. 4. In red, impedance and quality factor simulated by MoMentum for a 25 nH

inductance. In blue, impedance and quality factor for the maximum inductor

available in technology Hit Kit, 13 nH.

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311306

Zin ¼ sLS þ1

sCtþ

gmLS

Ct(3)

And the condition that allows SNIM is

Zopt ¼ Z�in (4)

From (1)–(3), the conditions that satisfy (4) and the matchingwith the source impedance are as follows:

Re½Zopt � ¼ Re½ZS� (5)

Im½Zopt � ¼ Im½ZS� (6)

Re½Zin� ¼ Re½ZS� (7)

All the parameter definitions are summarized in Table 2.The design parameters that can make (5)–(7) to be satisfied

simultaneously are: VGS1, W1 the width of M1, LS, and Cd. Sincethere are three equations and four unknowns, (5)–(7) can besolved for an arbitrary value by fixing the value of one of thedesign parameters. Therefore, in the PCSNIM LNA design techni-que, by the addition of an extra capacitor, the SNIM can beachieved at any level of power dissipation. The optimization islimited by the input impedance prescript. In order to adapt to thedesired impedance, it is necessary to add and input inductance Lg.

The qualitative description of the PCSNIM design processwould be as follows:

(1)

Choose the transistor size W1 and VGS1 based on the powerconstraint PD and minimum NF Fmin.

(2)

Choose the additional capacitance Cd, as well as the degen-eration inductance LS to satisfy (5) and (6) simultaneously. Thevalue of Cd should be selected considering the compromisebetween the size of LS and the available power gain. Too muchLS can lead to the increase in NFmin, while large Cd leads to thegain reduction due to the degradation of the effective cutofffrequency of the composite transistor (transistor including Cd).

(3)

If there exists any mismatch between Zin and Zs*, Lg is selectedto provide impedance matching. The different componentsvalues that allow a PCSNIM are also limited by inductors sizes.

If the inductors area exceeds the expected values, it is necessaryto relax the gain, noise, and power constraints. Furthermore, dueto the folded cascode capacity to diminish the supply voltage, thefolding of the common-gate transistor helps to extend the cutofffrequency of the common-source transistor. Moreover, the para-sitic capacitances at the drain node of the common-sourcetransistor can easily be eliminated by the resonance with the RFchock inductance. In Fig. 3, the size of M1 is 800mm and M2 is

280mm. Selecting a Vgs of 0.65 V, the current for this LNA stage isof 2.96 mA, from a supply voltage of 1.5 V. The value of thedegeneration inductance is 3 nH. In order to adapt the impedanceinput to the antenna impedance of 50O, Lg is designed with avalue of 25 nH.

The inductor quality factor Q represents an importantcharacteristic that directly affects LNA power and noise perfor-mance. For instance, when it is used to match different stages orto degenerate a transistor, it adds actually a voltage noise sourceto the node where the inductor is connected with a valueproportional to 1/Q. In the case of a RF chock or load, the inductoris designed to resonate out; therefore, the Q affects directly to themaximum allowable impedance. Fig. 4 shows, in red, theimpedance and quality factor of an optimized layout inductor of25 nH using a different strip width at each turn [11]. Theoptimization has been performed using MoMentum EM simulatorfrom Agilent Technologies to obtain the highest Q at 868.35 MHz.To compare, impedance and Q of the biggest inductor supplied bythe manufacturer, with an inductance of 13 nH, have been tracedin blue on the same plot. Additionally, both inductors have beenresonated at 868.35 MHz with an ideal capacitance. Improvementobtained using the inductor optimization procedure is easilyobserved: the impedance at resonance has been boosted by afactor of three. Therefore, for a fixed gain value of the LNA, thesolution using the optimized inductor will have a powerconsumption three times lower than the one using the standardinductor library.

3. Active BalUn

In conventional CMOS receiver architectures, the conversion ofthe single-ended signal from the antenna to a differential signal atthe input of LNA is performed by mean of an off chip passiveBalUn. The disadvantage of this scheme is that the overall receiverNF is degraded by the insertion loss of the BalUn. In addition, thecost of the receiver grows due to the need of an extra off chipcomponent. An alternative to this solution is to implement theconversion using an integrated active BalUn. This option providesan additional gain to LNA, desensitizing the overall NF of thesystem with respect to the NF of the next stages. Furthermore, bymeans of the active BalUn, the matching of the gain in thedifferential branches and the phase unbalance over a largerbandwidth are enhanced.

To evaluate the performance of the circuit, some of the typicalcharacterization parameters defined for fully differential stagesneed to be redefined, e.g., the common-mode rejection ratio(CMRR). In fully differential schemes, this parameter is defined as

ARTICLE IN PRESS

Fig. 5. Schematic of an active BalUn.

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311 307

the differential and common-mode gain quotient. In single-endedtopologies, this parameter involves a conversion of the single-ended input signal to a differential or common mode at theoutput. Therefore, although mixed-mode S-parameters are com-monly well established for N-even number of ports, it is not thecase for odd N-ports networks [12]. Thus, for completeness andwith the aim of accurate study, the active BalUn features, will bediscussed with the mixed-mode S-parameters formulation for thesingle-ended to differential conversion hereafter.

The well-known nine S-parameter matrix is related to itsstimulus and response by Bstd ¼ SstdAstd, where Bstd and Astd areresponse and stimulus waves vectors, respectively. The standardsuffix has been used to discard any possible mistake. To resumethe balance and unbalance information of the design, it is possibleto express a new mixed-mode S-parameter matrix with respect tothe standard matrix. In order to find this relation, it is possible toexpress the response and stimulus of standard mode and mixed-mode as follows:

ad2¼

1ffiffiffi2p ða2 � a3Þ (8)

bd2¼

1ffiffiffi2p ðb2 � b3Þ (9)

ac2¼

1ffiffiffi2p ða2 þ a3Þ (10)

bc2¼

1ffiffiffi2p ðb2 þ b3Þ (11)

The port 1 remains grounded with respect to the common-mode. Accordingly

aP1¼ a1 (12)

bP1¼ b1 (13)

where aP1and bP1

represent the excitation in Port 1 referred toground. ad2

and bd2are, respectively, the differential stimulus and

response in Port 2. And ac2and bc2

are common-mode stimulusand response in Port 2, respectively. Following on with the matrixrepresentation, it is easy to express the mixed-mode excitationsfrom its standard definition

aP1

ad2

ac2

0B@

1CA ¼

1 0 0

0 1ffiffi2p � 1ffiffi

2p

0 1ffiffi2p 1ffiffi

2p

0BB@

1CCA

a1

a2

a3

0B@

1CA (14)

The same transformation is found for the response Bmm ¼ MBstd.Once the matrix transformation M is known, the transforma-

tion between the S mixed-mode matrix and the standard matrix isgiven by [13]

Smm ¼ MSstdM�1 (15)

The mixed-mode S parameters can be represented by

bP1

bd2

bc2

0B@

1CA ¼

SP1P1SP1d2

SP1c2

Sd2P1Sd2d2

Sd2c2

Sc2P1Sc2d2

Sc2c2

0B@

1CA

aP1

ad2

ac2

0B@

1CA (16)

where Sd2P1and Sc2P1

represent, respectively, the gain indifferential and common mode:

Sd2P1¼

1ffiffiffi2p ðS21 � S31Þ (17)

Sc2P1¼

1ffiffiffi2p ðS21 þ S31Þ (18)

where SP1d2and SP1c2

represent the inverse isolation to differentialand common-mode:

SP1d2¼

1ffiffiffi2p ðS12 � S13Þ (19)

SP1c2¼

1ffiffiffi2p ðS12 þ S13Þ (20)

The different reflection coefficients are given by the nextexpressions:

SP1P1¼ S11 (21)

Sd2d2¼ 1

2ðS22 � S23 � S32 þ S33Þ (22)

Sc2c2¼ 1

2ðS22 þ S23 þ S32 þ S33Þ (23)

In addition, it appears that mixed-mode conversions Sd2c2

represents the conversion of common-mode to differential whena common-mode stimulus loads Port 2. Similarly, Sc2d2

representsthe differential mode to common-mode conversion:

Sd2c2¼ 1

2ðS22 þ S23 � S32 þ S33Þ (24)

Sc2d2¼ 1

2ðS22 � S23 þ S32 � S33Þ (25)

Now we can revise is the CMRR and the balanced phase (BP):

CMRR ¼SP1d2

SP1c2

(26)

BP ¼ phaseðS21Þ � phaseðS31Þ (27)

Notice the difference with the actual CMRR definition in fullydifferential circuits where the relation does not include modeconversion.

Now, with these figures of merit, the performance of thesecond stage, shown in Fig. 5, can be correctly evaluated. Thesecond stage of the LNA is formed by a differential cascodeconfiguration, where the input signal is copied from one branch tothe other through a bypass capacitor. The feedback circuit consistsof R1 and CF. The resistor R1 plays two roles: it keeps DC bias ofM4, while it senses the signal feedback from M3 drain. CF providesa DC blocking function and RF signal copy [14].

Ideally, this circuit will provide equal amplitude (or gain) and1801 phase difference. However, due to the finite impedance atnode S1 caused by parasitics at high frequency, the gain matchingand the balanced phase are degraded. An active device is oftenused as the current source; however, the voltage drop across the

ARTICLE IN PRESS

DIFFERENTIAL PHASE

160165170175180185190195200205210

0FREQUENCY (MHz)

PH

AS

E (D

EG

RE

ES

)

Active SourceInductance

500 1000 1500 2000

Fig. 6. Phase unbalance comparing between used of active source or inductive.

A

A

B

B

BA

BA

AB

BA

Fig. 7. Doubled centroid interdigitation topology for the differential pair in the

active BalUn. layout and schematic.

Fig. 8. Single-ended-to-differential LNA.

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311308

drain and source makes implementing using a low-power supplydifficult. For that reason, the active current source has beenreplaced by an inductor to increase the impedance of S1 at highfrequencies. Fig. 6 shows the improvement in the phase balancewhen an inductor is used.

The differential transformer at the drain of the cascode pairtransistors M5 and M6 is designed to resonate at 868.35 MHz.From the differential signal point of view, it generates a largeimpedance and, at the same time, it presents a notch for common-mode signal. The transformer has been optimized varying thewidth of each turn [15] using the former layout optimizationprocedure for inductors.

In Fig. 5, size of M3 and M4 is 1200mm. Selecting a Vgs of0.65 V, the current consumption for this LNA stage is 2.71 mAdrawn from a supply voltage of 1.5 V. The value for CF is 1 pF.

Gain and phase imbalance, as well as mixed-mode behaviour,are hardly dependent on device mismatches and layout symmetryand with intention of reducing any transistor mismatches,common-centroid topologies have been implemented. Hence, inthe design of the folded cascode, a square ABBA configuration hasbeen employed. Furthermore, in the case of the differential pair,the centroid interdigitation shown in Fig. 7 has been used [16].Similarly, all capacitors, inductors and transformers have beendesigned keeping symmetry as much as possible. Fig. 8 shows the

complete LNA single-ended-to-differential implementation with atotal die area of 3 mm2 including pads.

4. Experimental results

The LNA was implemented using a 0.35mm RFCMOS processfrom Austrian Micro System. This technology contemplates thepossibility of using four metal levels where the last one is a thickmetal of 2.8mm thickness and 10 mO/&.

The circuit has been measured on wafer using a CASCADEMicrotech ACP40-GSG probe for the single-ended input and anACP40-GSGSG probe for the differential output. A four-port ENARF network analyzer [17] from Agilent Technologies has been usedfor the small signal characterization, whereas the probes havebeen deembedded using a three-port SOLT calibration techniquewith a LRMM differential substrate. In addition, test structures(open and short) have been fabricated in order to remove theeffect of the pads. It must be kept in mind that the LNA design hasbeen optimized to be matched with the previous and nexttransceiver stages, and does not matter instrumentation sourceand load impedances, i.e. 50O.

The main measured figures of merit of the LNA gain are a singleended to differential gain of 21 dB, an output-to-input isolationbetter than 50 dB, and an input return loss of 10 dB whileconsuming 5.8 mA from a 1.5 V voltage supply. The differentialoutput reflection coefficient is �4.8 dB referred to 100O. Actually,the LNA has been designed to be matched to a differential VGA.Under that loading condition, the output reflection coefficient is�9.8 dB. Fig. 9 shows both the measured and simulated gains, andisolation. Fig. 10 shows input return loss and differential outputreturn loss. Note that the simulated gain is less than the measuredone. This is due to the fact that the actual quality factor of thefabricated inductors and transformers are better than thesimulated ones.

One of the main features of the proposed circuit is the rejectionof the common mode thanks to the inverter transformer placed atthe output of the active BalUn. It is important to keep in mind thatsuch device forces a differential broadband boundary condition.Therefore, the effectiveness for rejecting the common modedepends mainly on transformer mismatches. In Fig. 11, themeasured difference of the phase between the two outputbranches has been plotted from 650 to 950 MHz showing anexcellent performance of 180.071.01 in the whole frequencyrange.

Another interesting figure of merit is the CMRR calculated asthe differential gain Sd2P1

divided by common-mode gain Sc2P .Notice that the CMRR is only important if the next stageconnected to the LNA is single ended; otherwise, the rejection tothe common-node noise is measured from the phase imbalance of

ARTICLE IN PRESS

0.5

-20

-10

0

10

20

-30

30

-100

-50

0

-150

50

FREQUENCY (GHz)

DIF

F. T

RA

NS

DU

CE

R G

AIN

(dB

)

RE

VE

RS

E IS

OLA

TIO

N (d

B)

TRANSDUCER GAIN AND REVERSE ISOLATION

1.0 1.5 2.0 2.50.0

Fig. 9. Differential transducer power gain and reverse isolation. Measure is in red

and simulation is in blue.

0.5 3.0

-15

-10

-5

0

-20

5

FREQUENCY (GHz)

MA

GN

ITU

DE

(dB

)

REFLECTION COEFFICIENT

0.0 1.0 1.5 2.0 2.5

Fig. 10. Measured input reflection coefficients for 50O reference in red. Measured

differential reflection coefficient for 100O reference in blue.

700650 925

179

180

181

178

182

FREQUENCY (GHz)

PH

AS

E (D

EG

RE

ES

)

DIFFERENTIAL PHASE

750 800 850 900

Fig. 11. Differential phase in more detail. Measure is in red and simulation is in

blue.

60

40

20

0

-20

-40

-600 1 2 3 4 5

Frequency (GHz)

CM

RR

(dB

)

Fig. 12. Common-mode rejection ratio (CMRR). Measured data is in red and

simulation data is in blue.

NOISE FIGURE OVER 50OHM

2.004.006.008.00

10.0012.0014.0016.0018.0020.00

0.20

FREQUENCY (GHz)

NF

(dB

)

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

1.10

1.20

1.30

1.40

1.50

Fig. 13. Noise figure measured and simulated over 50O. Measured data is in red

and simulation data is in blue.

Table 3Performance comparison for 900 MHz LNAs in CMOS technology.

Quantity [18] [19] [10] This work

Gain (dB) 20 17.5 12 21

NF (dB) 3.2 2 1.35 4.3

S11 (dB) �12 �10 �18 �9.5

S22 n.a. �15 dB n.a. �9.8 dB

1 dB CP (dB m) �4 �15 �15 �9.5

IIP3 (dB m) 8 �6 �4 �3.0

DC power (mW) 27 22 2 9

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311 309

both output branches. As shown in Fig. 12, a CMRR of �33 dB hasbeen measured. Notice that the difference with the simulatedvalue is quite large. The reason is an amplitude imbalancebetween both outputs. For the circuit described in this work, theoutput of the LNA is connected to a differential input VGA. In thatcase, the CMRR lowers to a value better than �50 dB.

In order to measure the noise figure, a HP 8970B NF meter hasbeen used. Fig. 13 shows the simulated and measured NF over50O. At the frequency of interest, the NF measured value is 5.0 dB,whereas the simulated one is 4.7 dB. Although there are lower NF

reported values, as shown in Table 3, such designs do not includethe input gate matching inductor integrated on chip.

The non-linear behaviour of the LNA has been characterizedthrough the measurements of the 1 dB-compression point (P1 dB)and the third order input referred interception point (IIP3).Keeping in mind that the IEEE 802.15.4 establishes only onechannel in the European 868 MHz band, the 1 dB-compressionpoint value is a better figure of merit about the maximum powerat the input that can hold the LNA. Both outputs of the LNA havebeen combined out of chip by means of a hybrid coupler. Fig. 14shows the obtained result. At a value of �9.5 dB m of the inputpower, the differential gain falls by 1 dB.

For measuring the IIP3 value, two signals have been combinedusing one hybrid coupler at the input of the LNA. The signals havebeen separated 1 MHz in frequency. At the same time, bothoutputs of the LNA have been combined in a single-ended signal.

ARTICLE IN PRESS

1dB COMPRESSION POINT

0.0

5.0

10.0

15.0

20.0

25.0

-60GAIN (dB)

INP

UT

PO

WE

R (d

Bm

)

-50 -40 -30 -20 -10 0 10

Fig. 14. Compression point �1 dB.

INPUT INTERMODULATED POWER

-60-50-40-30-20-10

01020

-40INPUT POWER (dBm)

OU

TPU

T P

OW

ER

(dB

m)

Fundamental Tone3º Harmonic Tone

-35 -30 -25 -20 -15 -10 0-5

Fig. 15. Intermodulation input power measured. Fundamental tone at 868.35 MHz

is in blue. In cyan, the third harmonic at 869.35 MHz.

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311310

Fig. 15 shows a measured IIP3 value of �3 dB m. Theoretically, anIIP3 value 9 dB greater than P1 dB value should be expected.

In order to summarize the resulting performance of theproposed LNA, Table 3 shows a comparison with other state-of-the-art 900 MHz LNAs in CMOS technologies. Notice that thiswork is the only one which provides a complete monolithicsolution, integrating all inductors in the same die. For equivalentgain and IIP3 conditions in [18,19], the power consumption hasbeen reduced by half due to the use of optimized inductors, whilestill keeping a good noise performance. Although [10] shows alower NF and power consumption, it must be kept in mind thatonly the source degeneration inductor has been integrated;consequently the LNA performance depends mainly on theexternal components.

5. Conclusion

In this work, a low-power single-ended-to-differential LNA forIEEE 802.15.4 application has been implemented in a conventional0.35mm RFCMOS process. In order to enhance LNA performancefor the first time, the substitution of current mirrors as well asresistive and active loads, by optimized on-chip inductors andtransformers has been proposed. It has been proved that thereplacement of the current mirrors by optimized inductanceallows a supply voltage reduction of (Vth,nmos+|Vth,pmos|) value. Inaddition, the use of optimized load transformers and RF chockshas enabled the decrease of the polarization current by a factor ofthree for a fixed LNA gain value. Moreover, the behaviour of thesymmetric inverter transformer as a load in the active BalUnpresents a notch for the common-mode signal resulting. Thus, the

phase balance is better than 11 in a large frequency range. Allthese improvements translate to the figures of merit of thedesigned LNA as follows: a NF of 4.3 dB, power gain of 21 dB,and a balance of 180711, while dissipating 6 mA from supplyvoltage of 1.5 V.

Acknowledgment

The authors would like to thank to Dr. Angel Dieguez for hisinvaluable help. They would also like to thank to AgilentTechnologies for equipment support. This research wasfunded by the Spanish Government under project TEC2007-67247-C02-02.

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Tomas Carrasco Carrillo was born in Marbella, Spain,in 1976. He received the Physics degree, M.S. degree inelectronic engineering from the University of Barcelo-na, Barcelona, Spain, in 2002, 2003, respectively and iscurrently working toward the Ph.D. degree in electro-nics at the University of Barcelona, Barcelona, Spain.From 2004 to 2007 he collaborated with Epson EuropeElectronics Gmbh, involved in the design of RFICcircuits and monolithic RF systems. From March 2007to October 2007, he was a Visitor Research Engineerwith Institut fur MikrosystemTechnik (IMTEK) andFraunhofer IAF , Freiburg, Germany, where he was

involve in the design of a Front End for Nuclear

Magnetic Resonance Systems. He is currently participating in an Internship inQualcomm CDMA Technologies, San Diego, California where he works developingRFIC systems for multistandard commercial solutions.

ARTICLE IN PRESS

T.C. Carrillo et al. / INTEGRATION, the VLSI journal 42 (2009) 304–311 311

Jose Gabriel Macıas-Montero was born in Barcelona,Spain, in 1975. He received the M.Sc. degree inelectronic engineering from the University of Barcelo-na, Barcelona, Spain, in 1999, and is currently workingtoward the Ph.D. degree in electronics at the Universityof Barcelona. From November 1999 to August 2000, hewas an RF Designer with the Institute for Microelec-tronics, Frankfurt , Germany. In September 2000, hejoined the Department of Electronics, University ofBarcelona, as an Assistant Professor. From February toJuly 2003, he was a Visiting Research Fellow with theDelft Institute of Microelectronics and SubmicronTechnology (DIMES), Delft University of Technology,

Delft, The Netherlands. He was involved in the simplification of the MEXTRAMmodel for bipolar transistors on silicon substrates, as well as in the design andtesting of different RF circuits for high-resistivity silicon technology characteriza-tion. Since February 2005, he has been a Research Fellow with DIMES. His currentresearch interests are the design of ultra-low-power RF circuits for short-rangeapplications and the characterization and design of passives and integratedantennas on high-resistivity silicon for RF power harvesting applications.

Aitor Osorio Marti was born in Escaldes-Engordany,Andorra, Spain, in 1975. He received the B.S. degree intelecommunications engineering and M.S. degree inelectronic engineering from the University of RamonLlull, Barcelona, Spain, in 1997 and 1999, respectively,and the Ph.D. degree in electronics at the University ofBarcelona, Barcelona, Spain in 2006. In 2000, he joinedthe Electronics Department, University of Barcelona.From August 2001 to February 2002, he was a VisitorResearch Engineer with Austriamicrosystems AG, Un-terpremstaetten, Austria, where he was involved in thedesign and development of small and compact anten-

nas for ISM bands. His current research activities

concern the analysis and optimization of RF homodyne transceivers systems forshort-range low-power applications.

Javier Jose Sieiro Cordoba (M’04) was born inBarcelona, Spain, in 1971. He received the Physicsdegree, M.S. degree in electronic engineering, and Ph.D.degree in physics from the University of Barcelona,Barcelona, Spain, in 1995, 1999, and 2001, respectively.From 2002 to 2003, he was a member of the ElectronicComponents Technology and Materials (ECTM) Group,Delft University of Technology, Delft, The Netherlands,where he was involved with the modeling of passivecomponents and the design of RFIC circuits. Since2003, he has been with the Department of Electronics,University of Barcelona, where here is currently anAssociate Professor. His research interests are the

modeling of passive components and the design of homodyne transceiverarchitectures.

Jose Marıa Lopez-Villegas (M’93–SM’03) was born inBarcelona, Spain, in 1962. He received the Physicsdegree and Ph.D. degree in physics from the Universityof Barcelona, Barcelona, Spain, in 1985 and 1990,respectively. From 1985 to 1987, he was VisitingResearch Fellow with the Laboratoire d’ElectronicPhilips (LEP), Paris, France, where he was involved inthe electrical characterization of III–V compoundsemiconductor devices. In 1990, he joined the Electro-nic Department, University of Barcelona, initially as anAssistance Professor and then as a permanent Profes-sor Titular. He is currently the Head of the RF Group,

Electronics Department, University of Barcelona. His

research and development activities are focused on the design optimization andtest of RF systems and circuits performed using silicon technologies. Within thisfield, he is particularly interested in the modeling and optimization of integratedinductors and transformers for RFICs applications and in the development of newhomodyne transceiver architectures.