The28nmCMOSPowerAmplifierIECC2017Keynotetalk2017-05-19TedJohansson,IntegratedCircuitsandSystem,Dept.ofElectricalEngineering,LinköpingUniversity,Swedented.johansson@liu.se

Outline2

•  Moore’slaw•  Dennardscaling•  CMOSscalingbeyond130nm

•  Moore’slawandradiocircuitdesign

•  The28nmCMOSPowerAmplifier(PA)•  PAdesigninscaledCMOSforwirelessapplicaXons

•  FinFETandradiodesign

Moore’slawisnotaboutscalingbuteconomy!3

G.E.Moore,Electronics1965

4

Numberoftransistorerperchip

ISSCC1970-2015:Doublingeach24month

5

DennardscalingofMOSdevices

Component/circuitparameter Scalingfactor*

Componentdimension/thickness 1/λDopingconcentraXon λGateoxidethickness 1/λSupplyvoltage 1/λCurrent 1/λCapacitance 1/λDelayXme(1/speed) 1/λTransistorpower 1/λ2

Energyefficiency(”MIPS/W”) 1/λ3

Powerdensity 1 *constantelectricalfield

RobertDennard

Dennardetal.,JSSC,pp.256-268,Oct1974Dennard,SSCMag,pp.29-38,No.2,2015

Dennard&Moore1975-2000:Thewinningteam!6

Dennardscalingwhentransistorsgehngsmaller:•  fastercomponentsandcircuits,•  lowertotalpower(constantpowerdensity),•  electronicscanbemadesmaller,lighter,faster,beier.Moore’slaw:•  samecostperareawhencomponentsscale,•  moretransistorsperchip,•  lowercostpertransistor.

ProblemwithDennardscaling7

•  Supplyvoltagewasnotproperlyscaled,morelike1/sqrt(λ).•  SupplyvoltagereducXoninpracXcestoppedmorethantenyearsago.

•  Thermalnoise(kT/q=25mVatroomtemperature),

•  Sub-thresholdleakage(powerconsumpXon,thermalissues).

ProblemwithDennardscaling8

•  PowerconsumpXonlimitsthescaling

•  IncreasedclockspeedleadstohigherpowerconsumpXon

9

32/28 nm bulk MOSFET

90nm:mechanicalstraininthechannel=>highermobility

90nm:PD-SOI(reducedswitchingXme,correspondingtooneprocessnode,butmore

highersubstratecost).

45nm:MaterialwithhigherdielectricconstantsreplacingSiO2asinsulatorinthegate(reducedleakagecurrents)

28nm:Metalgate(smallerthresholdvoltagevariaXons)

28nm:FD-SOIThinundopedchannelwithdeviceproperXesgivenbyverXcaldimensionsand

backsidebias.

CMOS scaling down to 130 nm was rather ”linear”

10

22nm:Tri-GateorFinFET

FirstdescripXon?Hisamotoetal.,TED1991

Intel22nmwithextensionsforSoCdesign(Janetal.,IEDM2012)

2017:State-of-the-artis10nm11

•  Early2015:Intelsays10nmdelayedunXl2017(ITRS=2015)•  April2015:TSMCannouncedthat10nmproducXonwould

beginattheendof2016.

•  May2015:SamsungElectronicsshowedoffa300mmwaferof10nmFinFETchips.

•  August2016:IntelbegantrialproducXonat10nm.•  October2016:SamsungElectronicsannouncedmass

producXonat10nm.

•  April2017:SamsungstartedshippingtheirGalaxyS8whichusesSamsung'sversionofa10nmprocessor.

Wikipedia

12

Moore’slawinseveraldimensions

Moore’slawandradiocircuitdesign13

•  Nodesformanynewradiocircuitdesignstodayis28nmonbulksubstrateorFD-SOI.40and55nmalsopopular.

•  NodesgivemorethanfastenoughtransistorsforallwirelesscommunicaXoninthe1-6GHzbands(mobilecomm,wirelessnetworks,sensors,etc.),butalsoforshortrangecommunicaXon(e.g.5G,28-60-100+GHz).

•  DemandsforhighlevelofintegraXon(ofdigitalblocks)maketheselectedprocesseslesssuitableforradiodesign-toosmallnodes-butwesXllhavetolivewiththisproblem!

14

•  LastacXvepartinthetransmiierbeforetheantenna.Booststhesignaltohigherpowerlevelsfortransmihngthesignaltoadistantreceiver.

•  Powerlevels:•  Cellularphones:23-24Bm(Pav),upto30dBm(Ppeak),•  WLAN:upto20-23dBm(Pav),upto30dBm(Ppeak),

•  Bluetooth:typicallyaround5dBm.

•  Frequencyrangeoueninthe1-6GHzintervalforCMOSintegratedPAs

Thepoweramplifier(PA)

Thepoweramplifier(PA)15

•  RequirementsforportableapplicaXons(consumer-oriented):•  highintegraXon=>lowprice,•  baieryoperaXon=>highefficiencyneeded,

•  highlinearity=>highdatarate.

HowtoreachhighPAoutputpower16

•  Large devices (many parallel transistors) + impedance transformation. Power combination using (on-chip) transformers.

•  High supply voltage

•  ”Digital” PAs (class-D inverter-based, using normal supply voltage)

LDMOS structure with no additional process steps or masks*

17

Howtohandlethehighsupplyvoltage?

New component/new structures

DesignedinGlobalFoundry’s65nmCMOS-processforWLANapplicaXons.Conceptscalableto(availablein)45nmand32/28nm.

T.Johanssonetal.,EuMIC2013

•  TransistorswithW=5.6mmmountedonPCB

DifferenXalPA,Vdd=3V,f=2412MHzP-1dB=32,5dBm(1,8W).ClassAB,efficiencyover50%forunmodulatedsignal.

WLANPAT.Johanssonetal.,EuMIC2013

ThelinearPA19

•  Linear PAs (class A, AB, …) are the most commonly used amplifier classes on radio PA design.

•  Drawback: 2 x supply over the drain node of the transistor.

20

Howtohandlethehighvoltage?

Most common circuit solution: the cascode (stacked devices)

The voltage is however not evenly distributed between the transistors => not optimal (improved variants exist)

21

Transistorstacking:extendingtheconcept

C2, C3, C4 set Zs2, Zs3, Zs4

InpracXcelimitedtofourstackeddevices

Last=4Ropt

Chenetal.,JSSC2013

LimitaXonformaximumsupplyvoltage22

•  ConvenXonalbulkCMOS:manydiodebreakdownstowellsandsubstrate.

•  ScaledbulkCMOS:breakdownvoltagesdownto4-5V.

•  Stackedbulkcomponents(PA):willbelimitedbythedrain-substratebreakdownoftheuppermosttransistorinthestack.

•  WithSOI,thereisnobreakdowntothesubstrate.PossibletostackcomponentswithoutbreakdownvoltagelimitaXons.

23

28nmFD-SOI(UTBB)

Lg=24nm,Tox=1.8nm,Vsup=1.0Vultra-thinsilicon:7nmultra-thinburiedoxide:25nm

High-kdielectricMetal-gateelectrodeS/D:epitaxyraisedUndopedchannelBulk/SOIintegraXon

StackedPAdesign:Lg=150nm,Tox=2.8nm,Vsup=1.8V(+10%)

STMicroelectronics

3-stackedhigh-powerPAin28nmFD-SOI24

3-stackedhigh-powerPAin28nmFD-SOI25

•  JointprojectEricsson+AcreoSwedishICT+LiU•  Area1.5x2.2mm

•  Cost50k$•  UnderevaluaXon

PA1 PA2

DC test DC

test GSG calibration

”DigitalPA”26

•  CMOS-inverterscanbeusedasswitchedPA,classD.•  Theyoperateatnormal(”digital”)supplyvoltageandhas

noover-voltagecomparedtootherclassesofPAs.

•  InthisparXcularcase,theinvertersareusingavariantofcascode,sothattheoutputstagecanuse2xVDD,resulXnginhigheroutputpower.

Xuetal.,JSSC,2011

”DigitalPA”+transformerpowercombinaXon27

•  ThePAsaredividedinto4xdifferenXalPAsandpowercombinedusinganon-chiptransformer.

Fritzinetal.,ESSCIRC2011

4x1.5mm,130nmCMOS

28

Hottopic!

FinFETandradio29

•  NorecentexamplesintheliteratureofradiocircuitdemonstraXonusingFinFETs(someat45nmnodeforpureresearch).

•  DevicesimulaXonpapers.

•  ParasiXccapacitancesimportant!•  ”similarcharacteris-csintermsof

transconductance,Earlyvoltage,voltagegain,self-hea-ngissuebutUTBBoutperformsFinFETintermsofcutofffrequenciesthankstotheirrela-velylowerfringingparasi-ccapacitances.”(Raskin,”FinFETversusUTBBSOI-aRFperspecXve”,ESSDERC2015)

Summary30

•  MooreandDennard:conXnuedtransistorscaling,currentlyat10nmforlargeprocessors

•  FinFETforRFICdesign:lotofparasiXcsmakeradiodesignunfavorable.

•  Integratedradiodesign:28nmCMOS(bulkorFD-SOI)is”state-of-the-art”.

•  Alotoftricksneededtoreachhighoutputpower(>=30dBmor1W),butpossibleandwithgoodenoughperformanceforpopularapplicaXons.

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ThankyouforyouraienXon!