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CMOS Technology Scaling

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Page 1: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

CMOS Technology Scaling

Page 2: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

Moore’s law

“Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114.

“VLSI: some fundamental challenges” Moore, IEEE Spectrum 1970, p.30.

“Moore’s law governs the Silicon revolution”Bandyopadhyay, Proc. of IEEE, 1998, p.78

Gordon Moore was Ph.D. in Chemistry

Interdisciplinary barriers in Science and Technology are imaginary !

Moore co-founded Intel and proved his vision

Page 3: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

IEEE J. Solid State Circuits, Vo. 9(5), p.256 , 1974

Page 4: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

Typical Scaling Scenario• 1974 : 5m Technology, Vdd = 10V • 1984 : 1m Technology, Vdd = 5V• 1994 : 0.35m Technology, Vdd = 3.5V• 2004 : 90nm Technology, Vdd = 1V • 2014 : 22nm Technology, Vdd = 0.75V

Page 5: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

Constant Electric Field Scaling

Primary scaling factors:Tox, L, W, Xj (all linear dimensions) 1/KNa, Nd (doping concentration) KVdd (supply voltage) 1/K

Derived scaling behavior of transistor:Electric field 1Ids 1/KCapacitance 1/K

Derived scaling behavior of circuit:Delay (CV/I) 1/KPower (VI) 1/K2

Power-delay product 1/K3

Circuit density ( 1/A) K2

Technology scaling

Scaling factor K > 1

Page 6: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

Constant Voltage Scaling

Primary scaling factors:Tox, L, W, Xj (all linear dimensions) 1/KNa, Nd (doping concentration) K2

Vdd (supply voltage) 1Derived scaling behavior of transistor:

Electric field KIds KCapacitance 1/K

Derived scaling behavior of circuit:Delay (CV/I) 1/K2

Power (VI) KPower-delay product 1/KCircuit density ( 1/A) K2

Technology scaling

Scaling factor K > 1

Page 7: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

Generalized Scaling

Primary scaling factors:Tox, L, W, Xj (all linear dimensions) 1/KNa, Nd (doping concentration) KVdd (supply voltage) /K

Derived scaling behavior of transistor:Electric field Ids 2/KCapacitance 1/K

Derived scaling behavior of circuit:Delay (CV/I) 1/KPower (VI) 3/K2

Power-delay product 2/K3

Circuit density ( 1/A) K2

Technology scaling

Scaling factor K > 1

Page 8: CMOS Technology Scaling. Moore’s law “Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114. “VLSI: some fundamental

Non Scaling FactorsBandgap of Silicon Eg=1.12eV

Thermal voltage kT/q

Mobility degradationIncreasing doping and electric field

Velocity saturation

Parasitic s/d resistance

Process tolerance