modern vlsi design 3e: chapter 1 partly from 2002 prentice hall ptr week1-1 overview why vlsi?...
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week1-1Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Overview
Why VLSI?
Moore’s Law.
ASIC: Abstraction and Hierarchy.
FPGA: cheaper and programmable ASIC
week1-2Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
VLSI and you
Microprocessors: personal computers; microcontrollers.
DRAM/SRAM.
Special-purpose processors.
Many other applications: telecom, DSP,etc.
week1-3Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Moore’s Law
Gordon Moore: co-founder of Intel.
Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
Exponential improvement in technology is a
natural trend: steam engines, dynamos,
automobiles.
week1-4Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Moore’s Law plot
week1-5Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Overview
Why VLSI?
Moore’s Law.
ASIC: Abstraction and Hierarchy.
FPGA: cheaper ASIC
week1-6Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
ASIC and FPGA
Application-specific integrated circuit
design
Field programmable gate array
week1-7Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
ASIC
Top-down approaches
week1-8Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Levels of abstraction
Specification: function, cost, etc.
Architecture: large blocks.
Logic: gates + registers.
Circuits: transistor sizes for speed, power.
Layout: determines parasitics.
week1-9Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Design abstractions
specification
behavior
register-transfer
logic
circuit
layout
English
Executableprogram
Sequentialmachines
Logic gates
transistors
rectangles
Throughput,design time
Function units,clock cycles
Literals, logic depth
nanoseconds
microns
function cost
week1-10Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
CAD Tools
specification
behavior
register-transfer
logic
circuit
layout
English
VHDL/verilog
(schematic)
Gate netlist
(schematic)
Transistor netlist
Synopsys
Cadence
week1-11Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
ASIC: Hierarchical name
Interior view of a component: components and wires that make it up.
Exterior view of a component = type: body; pins. Full
addera
bcin
sum
cout
week1-12Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
ASIC:Instantiating component types
Each instance has its own name: add1 (type full adder) add2 (type full adder).
Each instance is a separate copy of the type:
Add1(Fulladder)
a
bcin
sum
cout
Add2(Fulladder)
a
bcin
sumAdd1.a Add2.a
week1-13Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Net lists and component lists
Net list:net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Component list:top: in1=net1 n1=topin1
n2=topin2 n3=topine out=outnet
i1: in=net1 out=net2xxx: xin1=topin1
xin2=topin2 xin3=botin1 B=net2 out=net3
i2: in=net3 out=outnet
week1-14Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Component hierarchy
top
i1 xxx i2
week1-15Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Hierarchical names
Typical hierarchical name: top/i1.foo
component pin
week1-16Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Layout and its abstractions
Layout for dynamic latch:
week1-17Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Stick diagram
week1-18Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Transistor schematic
week1-19Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Mixed schematic
inverter
week1-20Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Characteristics of ASIC
Expensive
Many cycles of design: Simulation,
synthesis
Design for testing (DFT)
week1-21Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
week1-22Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Layout of ASIC
Pentium IVTechnology: 0.13 umArea: 35 mm squareSpeed: 2.2GHzPower: 55 W
week1-23Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Design abstractions
specification
behavior
register-transfer
logic
circuit
layout
English
Executableprogram
Sequentialmachines
Logic gates
transistors
rectangles
Throughput,design time
Function units,clock cycles
Literals, logic depth
nanoseconds
microns
function cost
week1-24Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
CAD Tools
specification
behavior
register-transfer
logic
circuit
layout
English
VHDL/verilog
(schematic)
Gate netlist
(schematic)
Transistor netlist
Synopsys
Cadence
week1-25Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Characteristics of FPGA
Programmability
Simulation, synthesis
Test
week1-26Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
week1-27Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Layout of FPGA
week1-28Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Top-down vs. bottom-up design
Top-down design adds functional detail. Create lower levels of abstraction from upper levels.
Bottom-up design creates abstractions from low-
level behavior.
Good design needs both top-down and bottom-up
efforts.
week1-29Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Design abstractions
specification
behavior
register-transfer
logic
circuit
layout
English
Executableprogram
Sequentialmachines
Logic gates
transistors
rectangles
Throughput,design time
Function units,clock cycles
Literals, logic depth
nanoseconds
microns
function cost
week1-30Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
CAD Tools
specification
behavior
register-transfer
logic
circuit
layout
English
VHDL/verilog
(schematic)
Gate netlist
(schematic)
Transistor netlist
Xilinx Foundation tools
week1-31Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Contents of the Course
ASIC FPGA
Transistor and Layout
Gate and Schematic
Systems and VHDL/Verilog
week1-32Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Contents of the Course (cont’d)
2 ASIC labs 2 FPGA labs
Transistor/Layout
Gate and Schematic
Systems/VHDL
(Cadence)
(Synopsys)
(XilinxFoundation)
week1-33Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
The Future Is Not What It Used To Be
week1-34Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR
Future of VLSI
Nanotechnology
Biotechnology
Information technology
week1-35Modern VLSI Design 3e: Chapter 1 Partly from 2002 Prentice Hall PTR