co oftunit v

8/10/2019 CO oftUnit V

1/50

1

Mailam Engineering College(Approved by AICTE, New Delhi, Affiliated to Anna University, Chennai

& Accredited by National Board of Accreditation (NBA, New Delhi

Mailam (Po), Villupuram (Dt). Pin: 604 304

DEPARTMET !" C!MP#TER APP$%CAT%!&Computer !rgani'ation MC*++

Part A

+. -at i memor/ /tem

Every Co!p"ter contains several types of devices to store the instr"ctions and datafor its operation# These stora$e devices pl"s the al$orith! i!ple!ents by hardware andsoftware needed to !ana$e the stored infor!ation fro! the !e!ory syste! of co!p"ter#

*. 1i2e t-e laiiation o memor/ C%U e$ister

'ain !e!ory

econdary 'e!ory

Cache !e!ory#

3. Deine &tati Memorie an5 D/nami Memorie.'e!ories that consist of circ"itscapable of retainin$ their state as lon$ as power is

applied are )nown*s static !e!ories# In Dyna!ic 'e!ories s"ch cells do not retain theirstate indefinitely#

4. -at i rea5 ae time

A basic perfor!ance !eas"re is the avera$e ti!e to read a fi+ed a!o"nt ofinfor!ation for instance, one word fro! the !e!ory# This para!eter is called the readaccess ti!e#

. Deine RAMIn stora$e location can be accessed in any order and access ti!e is independent of

the location bein$ accessed, the !e!ory is ter!ed as rando! access !e!ory#

6. -at i R!M'e!ories whose content cannot be altered online if they can be altered at all are

read only !e!ories#

7. -at are PR!Me!i cond"ctor 's whose contents can be chan$ed offline-with so!e diffic"lties is called%'s#

Prepared ByMrs. V.Rekha AP / MCA

#%T V MEM!R8 AD %9! &8&TEM

'e!ory technolo$y . 'e!ory syste!s . /irt"al !e!ory . Caches . Desi$n !ethods .

Associative !e!ories . Inp"t 0 "tp"t syste! . %ro$ra!!ed I0 . D'A and Interr"pts .

I0 Devices and Interfaces#


2/50

2

. -at i &RAM AD DRAMA'1 tatic rando! access !e!ory# It tends to be faster# They re2"ire no refreshin$#

DA'1 Dyna!ic rando! access !e!ory# Data is stored in the for! of char$es# ocontin"o"s refreshin$ is needed#

. -at i 2olatile memor/A !e!ory is volatile if the loss of power destroys the stored infor!ation# Infor!ation

can be stored indefinitely in a volatile !e!ory by providin$ battery bac)"p or other !eansto !aintain a contin"o"s s"pply of power#

+0. -at are t-e ategorie o memorie,

A'

DA'

++. -at i la- memor/

A recent se!icond"ctor technolo$y called flash !e!ory of a sa!e non-volatility as a%', b"t it can be done a bit at a ti!e#

+*. -at i a-e memor/ an5 ;rite an a52antage o uing a-e memor/

'e!ory word are stored in cache data !e!ory and are $ro"ped into s!all pa$escalled cache bloc)s or line# The contents of the caches data !e!ory are th"s copies of aset of !ain !e!ory bloc)s# Used to increase the speed and perfor!ance d"rin$ !e!oryaccess#

+3. Mention t;o /tem organi'ation or a-e.

Two syste! or$ani3ations for caches are 4oo) aside

4oo) thro"$h

+4. -at i RAM?#& memor/

The )ey feat"re of A'BU technolo$y is a fast si$nalin$ !ethod "sed to transferinfor!ation between chips "sin$ narrow b"s# Instead of "sin$ si$nals that have volta$elevels of either 5 or / s"pply to represent the lo$ic val"es, the si$nals consist of !"chs!aller volta$e swin$s aro"nd a reference volta$e, vref# !all volta$e swin$s !a)e itpossible to have short transition ti!es, which allows for a hi$h speed of trans!ission#

+. -at i ;rite@t-roug- protool

6or write operation, the cache location and the !ain !e!ory location are "pdatedsi!"ltaneo"sly#

+6. 1i2e t-e 5ierene et;een EEPR!M an5 "la- memor/

The pri!ary difference between EE%' and flash !e!ory is that flash restrictswrites to !"ltiple )ilobytes bloc)s, increasin$ the !e!ory capacity per chip by red"cin$area of control#

+7. Dierene et;een a-e memor/ an5 2irtual memor/

In caches, replace!ent is pri!arily controlled by the hardware# In /', replace!ent is

pri!arily controlled by the # The N"!ber of bits in the address deter!ines the si3e of /', where as cache si3e is

independent of the address si3e# B"t there is only one class of cache#



3/50

3

+. #e o Virtual Memor/.%rotection1 /' is often "sed to protect one pro$ra! fro! others in the syste! Base

and Bo"nds1 this !ethod allows relocation# User processes cannot be allowed to chan$ethese re$isters, b"t the !"st be able to do so on a process switch#

+. %nterlea2e5 Memor/.

Ban)s of !e!ory are often one word wide, so b"s width need not be chan$ed toaccess !e!ory# 7owever several independent areas of !e!ory can be accessedsi!"ltaneo"sly by "sin$ interleaved !e!ory#

*0. -at i ;rite aB protoolIn this sche!e, only the bloc) in cache is !odified# The !ain !e!ory when the

bloc) !"st be replaces in the cache# This re2"ires the "se of a dirty bit to )eep trac) ofbloc)s, that have been !odified#

*+. Deine t-e term interrupt.

The interr"pt is a tas) "sed to perfor! specific operation# et of instr"ctions which isinvo)ed by interr"pt is called interr"pt service ro"tine 8I9# :enerally is classified ashardware and software interr"pt#

**. -at i t-e untion o A$# C#'ost of the co!p"ter operations (arith!etic and lo$ic are perfor!ed in A4U# The

data re2"ired for the operation is bro"$ht by the processor and the operation is perfor!edby the A4U#

The control "nit acts as the nerve center, which coordinates all the co!p"teroperations# It iss"es ti!in$ si$nals that $overns the data transfer#

*3. -at are ai operation o a omputer

The basic operations are EAD and ;ITE#

*4. -at are t-e regiter generall/ ontaine5 in t-e proeor

'A-'e!ory Address e$ister 'D-'e!ory Data e$ister

I-Instr"ction e$ister

5-n-:eneral p"rpose e$isters

%C-%ro$ra! Co"nter

*. -at i t-e ue o uer regiterThe b"ffer re$ister is "sed to avoid speed !is!atch between the I0 device and theprocessor#

*6. -at i t-e maimum i'e o t-e memor/ t-at an e ue5 in a +6@it

omputer an5 3* it omputer

The !a+i!"! si3e of the !e!ory that can be "sed in a > ?@: !e!ory locations#

*7. Deine memor/ ae time memor/ /le time

The ti!e re2"ired to access one word is called the !e!ory access ti!e# r it is theti!e that elapses between the initiation of an operation and the co!pletion of thatoperation#



4/50

4

It is the !ini!"! ti!e delay re2"ired between the initiations of two s"ccessive!e!ory operations# E$# The ti!e between two s"ccessive read operations#

*. -en i a memor/ unit alle5 a RAM

A !e!ory "nit is called as A' if any location can be accessed for a read or writesoperation in so!e fi+ed a!o"nt of ti!e that is independent of the location*s address#

30. -at i MM#

''U is the 'e!ory 'ana$e!ent Unit# It is a special !e!ory control circ"it "sed fori!ple!entin$ the !appin$ of the virt"al address space onto the physical !e!ory#

3+. Deine memor/ ell or5 line

A !e!ory cell is capable of storin$ one bit of infor!ation# It is "s"ally or$ani3ed inthe for! of an array# In a !e!ory cell, all the cells of a row are connected to a co!!on linecalled as word line#

3*. o; ;ill /ou -an5le multiple interrupt ;hen the processor is bein$ processin$ an interr"pt, the processor i$nores any new

interr"pt si$nal and these new si$nals have to wait in a 2"e"e and processor will chec) after

the c"rrently processin$ interr"pt is finished# Each interr"pt has a priority val"e# ;hen theprocessor is bein$ e+ec"tin$ an interr"pt, another interr"pt can interr"pt and $ain theprocessor if the second interr"pt has a hi$her priority than first one

33. Deine tati memorie

A !e!ory that consists of circ"its capable of retainin$ their state as lon$ as power isapplied is called tatic !e!ories#

34. -at are t-e C-arateriti o emion5utor RAM memorie

They are available in a wide ran$e of speeds#

Their cycle ti!e ran$e fro!


5/50

5

3. -at are a/n-ronou DRAM

In asynchrono"s DA's, the ti!in$ of the !e!ory device is controlledasynchrono"sly# A speciali3ed !e!ory controller circ"it provides the necessary controlsi$nals A and CA that $overn the ti!in$# The processor !"st ta)e into acco"nt thedelay in the response of the !e!ory# "ch !e!ories are asynchrono"s DA's#

40. -ere i a T$? loate5 an5 ;-at 5oe it ontain

A translation loo) aside b"ffer (T4B is a cache that !e!ory !ana$e!ent hardware"ses to i!prove virt"al address translation speed# All c"rrent des)top, noteboo), and serverprocessors "se a T4B to !ap virt"al and physical address spaces, and it is nearly alwayspresent in any hardware which "tili3es virt"al !e!ory#4+. Deine ?an5;i5t-

;hen transferrin$ bloc)s of data, it is of interest to )now how !"ch ti!e is neededto transfer an entire bloc)# ince bloc)s can be variable in si3e it is "sef"l to define aperfor!ance !eas"re in ter!s of n"!ber of bits or bytes that can be transferred in onesecond# This !eas"re is often referred to as the !e!ory bandwidth#

4*. -at i 5oule 5ata rate &DRAM Do"ble data rates DA's are those which can transfer data on both ed$es of the

cloc) and their bandwidth is essentially do"bled for lon$ b"rst transfers#

43. -at i mot-eroar5

'other Board is a !ain syste! printed circ"it board which contains the processor# It willocc"py an "nacceptably lar$e a!o"nt of space on the board#

44. -at are &%MM an5 D%MM

I''s are in$le In-line 'e!ory 'od"les# DI''s are D"al In-line 'e!ory 'od"les#"ch !od"les are an asse!bly of several !e!ory chips on a separate s!all board thatpl"$s vertically into a sin$le soc)et on the !otherboard#

4. -at i memor/ Controller

A !e!ory controller is a circ"it which is interposed between the processor and thedyna!ic !e!ory# It is "sed for perfor!in$ !"ltiple+in$ of address bits# It provides A-CA ti!in$# It also sends 0; and C si$nals to the !e!ory# ;hen "sed with DA' chips,which do not have self refreshin$ capability, the !e!ory controller has to provide all theinfor!ation needed to control the refreshin$ process#

46. Dierentiate tati RAM an5 5/nami RAM

tatic A' Dyna!ic A'

They are fast They are slow

They are very e+pensive They are less e+pensive

They retain their state indefinitely They do not retain their state indefinitely

They re2"ire several transistors They re2"ire less no transistors#

4ow density 7i$h density

47. -at are R%MM

DA' chips can be asse!bled in to lar$er !od"les called I''s# It can hold "pto


6/50

6

DA's are A'BU DA's# A'BU re2"ires specially desi$ned !e!ory chips#These chips "se cell arrays based on the standard DA' technolo$y# '"ltiple ban)s of cellarrays are "sed to access !ore than one word at a ti!e# Circ"itry needed to interface to theA'BU channel is incl"ded on the chip# "ch chips are )nown as DA's#

4. -at are t-e peial eature o Diret RDRAM

It is a two channel a!b"s## It has


7/50

7

Two aspects of locality of reference are te!poral aspect and spatial aspect# Te!poralaspect is that a recently e+ec"ted instr"ction is li)ely to be e+ec"ted a$ain very soon# Thespatial aspect is that instr"ctions in close pro+i!ity to a recently e+ec"ted instr"ction arealso to be e+ec"ted soon#

. Deine a-e line.

Cache bloc) is "sed to refer to a set of conti$"o"s address locations of so!e si3e#Cache bloc) is also referred to as cache line#

60. -at are t-e t;o ;a/ in ;-i- t-e /tem uing a-e an proee5 or a

;rite operation

;rite thro"$h protocol techni2"e#

;rite-bac) or copy bac) protocol techni2"e#

6+. -at i ;riting t-roug- protool6or a write operation "sin$ write thro"$h protocol d"rin$ write hit1 the cache location

and the !ain !e!ory location are "pdated si!"ltaneo"sly# 6or a write !iss1 6or a write!iss, the infor!ation is written directly to the !ain !e!ory#

6*. -en 5oe a rea5mi our

;hen the addressed word in a read operation is not in the cache, a read !iss occ"r#

63. -at i ;rite@aB or op/ aB protool6or a write operation "sin$ this protocol d"rin$ write hit1 the techni2"e is to "pdate

only the cache location and to !ar) it as "pdated with an associated fla$ bit, often calledthe dirty or !odified bit# The !ain !e!ory location of the word is "pdated later, when thebloc) containin$ this !ar)ed word is to be re!oved fro! the cache to !a)e roo! for a newbloc)# 6or a write !iss1 the bloc) containin$ the addressed word is first bro"$ht into thecache, and then the desired word in the cache is overwritten with the new infor!ation#

64. -at i loa5@t-roug- or earl/ retart

;hen a read !iss occ"rs for a syste! with cache the re2"ired word !ay be sent tothe processor as soon as it is read fro! the !ain !e!ory instead of loadin$ in to the cache#This approach is called load thro"$h or early restart and it red"ces the processor*s waitin$period#

6. -at are t-e mapping te-niFue Direct !appin$ Associative !appin$ et Associative !appin$

66. -at i a -it -it rate

A s"ccessf"l access to data in cache !e!ory is called hit# The n"!ber of hits statedas a fraction of all atte!pted access#

67. -at are 2etore5 interrupt

In a co!p"ter, a vectored interr"pt is an I0 interr"pt that tells the part of theco!p"ter that handles I0 interr"pts at the hardware level that a re2"est for attention fro!an I0 device has been received and also identifies the device that sent the re2"est#

6. -at are t-e t;o ;a/ o ontruting a larger mo5ule to mount la- -ip ona mall ar5



8/50

8

6lash cards 6lash drivers#6. Deine mi rate an5 mi penalt/

It is the n"!ber of !isses stated as a fraction of atte!pted accesses# The e+tra ti!eneeded to brin$ the desired infor!ation into the cache#

70. Deine ae time or magneti 5iBThe s"! of see) ti!e and rotational delay is called as access ti!e for dis)s# ee)

ti!e is the ti!e re2"ired to !ove the read0write head to the proper trac)# otational delayor latency is the a!o"nt of ti!e that elapses after the head is positioned over the correcttrac) "ntil the startin$ position of the addressed sector passes "nder the read0write head#

7+. -at i p-ae eno5ing or Man-eter eno5ing

It is one encodin$ techni2"e for co!binin$ cloc)in$ infor!ation with data# It is asche!e in which chan$es in !a$neti3ation occ"r for each data bit# It s disadvanta$e is poorbit-stora$e density#7*. -at are preet- intrution

%refetch Instr"ctions are those instr"ctions which can be inserted into a pro$ra!

either by the pro$ra!!er or by the co!piler#

73. Deine /tem pae an5 uer pae.

'ana$e!ent ro"tines are part of the operatin$ syste! of the co!p"ter# It isconvenient to asse!ble the ro"tines into a virt"al address space#

The syste! space is separated fro! virt"al address space in which the "serapplication pro$ra!s reside# The letter space is called "ser space#74. -at are page

All pro$ra!s and data are co!posed of fi+ed len$th "nits called pa$es# Each consistsof bloc)s of words that occ"py conti$"o"s locations in !ain !e!ory#

7. -at i replaement algorit-m

;hen the cache is f"ll and a !e!ory word that is not in the cache is referenced, thecache control hardware !"st decide which bloc) sho"ld be re!oved to create space for thenew bloc) that contains the reference word #The collection of r"les for !a)in$ this decisionconstit"tes the replace!ent al$orith!#

76. -at i 5irt/ or mo5iie5 itThe cache location is "pdated with an associated fla$ bit called dirty bit#

77. -at i ;rite mi

D"rin$ the write operation if the addressed word is not in cache then said to be write!iss#

7. -at i aoiati2e reear-

The cost of an associative cache is hi$her than the cost of a direct !apped cache beca"se ofthe need to search all ta$ patterns to deter!ine whether a $iven bloc) is in the cache#A search of this )ind is called an associative search#

7. -at i 2irtual memor/



9/50

9

Techni2"es that a"to!atically !ove pro$ra! and data bloc)s into the physical !ain!e!ory when they are re2"ired for e+ec"tion are called as virt"al !e!ory#

0. -at i 2irtual a55re

The binary address that the processor "sed for either instr"ction or data called as virt"al

address#

+. -at i 2irtual page numer page rame

Each virt"al address $enerated by the processor whether it is for an instr"ction fetchis interpreted as a virt"al pa$e#

An area in the !ain !e!ory that can hold one pa$e is called as pa$e fra!e#

*. -at i in-eter te-nolog/

The dis) and the read0write heads are placed in a sealed air-filtered enclos"re called;inchester technolo$y#

3. -at i a 5iB 5ri2e 5iB ontroller

The electro!echanical !echanis! that spins the dis) and !oves the read0writeheads called dis) drive#

The electronic circ"itry that controls the operation of the syste! called as dis)controller#

4. -at i main memor/ a55reThe address of the first !ain !e!ory location of the bloc) of words involved in the

transfer is called as !ain !e!ory address#

. -at i Error -eBing

It co!p"tes the error correctin$ code (ECC val"e for the data read fro! a $iven sector andco!pares it with the correspondin$ ECC val"e read fro! the dis)#

6. -at i ooting

;hen the power is t"rned on the has to be loaded into the !ain !e!ory whichta)es place as part of a process called bootin$# To initiate bootin$ a tiny part of !ain!e!ory is i!ple!ented as a nonvolatile '#

7. -at are t-e t;o tate o proeor

"pervisor state User state#

. -at i loBup@ree

A cache that can s"pport !"ltiple o"tstandin$ !isses is called loc)"p-free#

. -at i a /le tealing in DMA



10/50

10

The ti!in$ se2"ence of events for the devices as D'A controller > re2"ests andac2"ires b"s !astership and later releases the b"s# D"rin$ Its ten"re as the b"s !aster, it!ay perfor! one or !ore data transfer operations, dependin$ on whether it is operatin$ inthe cycle stealin$ or bloc) !ode#

Part @ ?

+. Eplain ome ai onept o memor/ /tem.

Co!p"ter sho"ld have a lar$e !e!ory to facilitate e+ec"tion of pro$ra!s that arelar$e and deal with h"$e a!o"nts of data# The !e!ory sho"ld be fast, lar$e, andine+pensive# Unfort"nately, it is i!possible to !eet all three of these re2"ire!entssi!"ltaneo"sly# Increased speed and si3e are achieved at increased cost# To solve thisproble!, !"ch wor) has $one into developin$ clever str"ct"res that i!prove the apparentspeed and si3e of the !e!ory, yet )eep the cost reasonable#

The !a+i!"! si3e of the !e!ory that can be "sed in any co!p"ter is deter!inedby the addressin$ sche!e# 6or e+a!ple, a @5 ? < T (Tera locations# The n"!ber of locations represents the si3e of the address spaceof the co!p"ter#

6ro! the syste! standpoint, we can view the !e!ory "nit as a blac) bo+# Datatransfer between the !e!ory and the processor ta)es place thro"$h the "se of twoprocessor re$isters, "s"ally called 'A (!e!ory address re$ister and 'D (!e!ory datare$ister, If 'A is ) bits lon$ and 'D is n bits lon$, then the !e!ory "nit !ay contain "pto > ) addressable locations#

D"rin$ a !e!ory cycle, n bits of data are transferred between the !e!ory and theprocessor# This transfer ta)es place over the processor b"s, which has ) address lines and n

data lines# The b"s also incl"des the con


11/50

11

this action by assertin$ the '6C si$nal# Upon receipt of the '6C si$nal, the processor loadsthe data on the data lines into the 'D re$ister#

The processor writes data into a !e!ory location by loadin$ the address of thislocation into 'A and loadin$ the data into 'D# It indicates that a write operation isinvolved by settin$ the 0 ; line to 5# If read or write operations involve consec"tive

address locations in the !ain !e!ory, then a Gbloc) transferG operation can be perfor!edin which the only address sent to the !e!ory is the one that identifies the first location#

The ti!e between the ead and the '6C si$nals is referred to as the memory accesstime# The memory cycle time is the !ini!"! ti!e delay re2"ired between the initiations oftwo s"ccessive !e!ory operations, If any location can be accessed for a ead or ;riteoperation so!e fi+ed a!o"nt of ti!e that is independent of the locationHs address in a!e!ory "nit is called random-access memory (A'# ne way to red"ce the !e!oryaccess ti!e is to "se a cache memory. This is a s!all, fast !e!ory that is inserted betweenthe lar$er, slower !ain !e!ory and the processor# It holds the c"rrently active se$!ents ofa pro$ra! and their data#

Virtual memory is "sed to increase the apparent si3e of the physical !e!ory# Data

are addressed in a virt"al address space that can be as lar$e as the addressin$ capability ofthe processor# B"t at any $iven ti!e, only the active portion of this space is !apped ontolocations in the physical !e!ory# The re!ainin$ virt"al addresses are !apped onto theb"l)1 stora$e devices "sed, which are "s"ally !a$netic dis)s# The virt"al address space is!apped onto the physical !e!ory where data are act"ally stored# The !appin$ f"nction isi!ple!ented by a special !e!ory control circ"it, often called the memory managementunit#

*. Diu internal organi'ation o memor/ -ip.

'e!ory cells are "s"ally or$ani3ed in the for! of an array, in which each cell iscapable of storin$ one bit of infor!ation# A possible or$ani3ation is ill"strated,



12/50

12

Organization of bit cell in a memory chipEach row of cells constit"tes a !e!ory word, and all cells of a row are connected to

a co!!on line referred to as the word line, which is driven by the address decoder on thechip# The cells in each col"!n are connected to a ense0;rite circ"it by two bit lines# Theense0;rite circ"its are connected to the data inp"t0o"tp"t lines of the chip# D"rin$ a eadoperation, these circ"its* sense, or read, the infor!ation stored in the cells selected by aword line and trans!it this infor!ation to the o"tp"t data lines# D"rin$ a ;rite operation,the ense0;rite circ"its receive inp"t infor!ation and store it in the cells of the selectedword#

An e+a!ple of a very s!all !e!ory chip consistin$ of


13/50

13

Organization of 1K x 1 memory chip

The !e!ory circ"it in 6i$"re @#> stores bits and re2"ires


14/50

14

rite operation

The state of the cell is set by placin$ the appropriate val"e on bit line b and itsco!ple!ent on bH, and then activatin$ the word line# This forces the cell into thecorrespondin$ state# The re2"ired si$nals on the bit lines are $enerated by the ense0;ritecirc"it# If Tl and T> are t"rned on (closed, it lines b and b H will have hi$h and low si$nals,

respectively#

A static RAM cell

An example of a CMOS memory cell

The power s"pply volta$e, / s"pply, is F / in older C' A's or # / in new lowvolta$e versions# Note that Gcontin"o"s power is needed for the cell to retain its state# Ifpower is interr"pted, the cellHs contents will be lost#

;hen power is restored, the latch will settle into a stable state, b"t it will notnecessarily be the sa!e state the cell was in before the interr"ption# 7ence, A's are saidto be volatile !e!ories beca"se their contents are lost when power is interr"pted#

A !aor advanta$e of C' A's is their very low power cons"!ption beca"sec"rrent flows in the cell only when the cell is bein$ accessed# therwise, Tl, T> and onetransistor in each inverter are t"rned off, ens"rin$ that there is no active path between /s"pply and $ro"nd#

tatic A's can be accessed very 2"ic)ly# Access ti!es of "st a few nanosecondsare fo"nd in co!!ercially available chips# A's are "sed in applications where speed is ofcritical concern#



15/50

15

4. Eplain A/n-ronou DRAM& &/n-ronou DRAM& .

A/n-ronou DRAM&:

tatic A's are fast, b"t they co!e at a hi$h cost beca"se their cells re2"ire several

transistors# 4ess e+pensive A's can be i!ple!ented if si!pler cells are "sed# 7owever,s"ch cells do not retain their state indefinitelyL hence, they are called dyna!ic A's(DA's#

Infor!ation is stored in a dyna!ic !e!ory cell in the for! of a char$e on acapacitor, and this char$e can be !aintained for only tens of !illiseconds# ince the cell isre2"ired to store infor!ation for a !"ch lon$er ti!e, its contents !"st be periodicallyrefreshed by restorin$ the capacitor char$e to its f"ll val"e#

An e+a!ple of a dyna!ic !e!ory cell that consists of a capacitor, C, and atransistor, T, is order to store infor!ation in this cell, transistor T is t"rned on and anappropriate volta$e is applied to the bit line# This ca"ses a )nown a!o"nt of char$e to bestored in the capacitor#

A ingle tranitor 5/nami memor/ ell



16/50

16

Internal Organization of a 2M x 8 ynamic memory chip

A


17/50

17

chips are bein$ developed# To red"ce the n"!ber of !e!ory chips needed in a $ivenco!p"ter, a DA' chip is or$ani3ed to read or write a n"!ber of bits in parallel# To providefle+ibility in desi$nin$ !e!ory syste!s, these chips are !an"fact"red in differentor$ani3ations#

&/n-ronou DRAM&

DA's whose operation is directly synchroni3ed with a cloc) si$nal are )nown assynchrono"s DA's (DA's# The cell array is the sa!e as in asynchrono"s DA's# Theaddress and data connections are b"ffered by !eans of re$isters# ;e sho"ld partic"larlynote that the o"tp"t of each sense a!plifier is connected to a latch# A ead operationca"ses the contents of all cells in the selected row to be loaded into these latches# B"t, if anaccess is !ade for refreshin$ p"rposes only, it will not chan$e the contents of these latchesLit will !erely refresh the contents of the cells# Data held in the hitches that correspond tothe selected col"!n(s are transferred into the data o"tp"t re$ister, th"s beco!in$ availableon the data o"tp"t pins#

The row address is latched "nder control of the A si$nal# The !e!ory typicallyta)es > or cloc) cycles to activate the selected row# Then, the col"!n address is latched

"nder control of the CA si$nal# After a delay of one cloc) cycle, the first set of data bits isplaced on the data lines# The DA' a"to!atically incre!ents the col"!n address toaccess the ne+t three sets of bits in the selected row, which are placed on the data lines inthe ne+t cloc) cycles#

DA's have b"ilt-in refresh circ"itry# A part of this circ"itry is a refresh co"nter,which provides the addresses of the rows that are selected for refreshin$# In a typicalDA', each row !"st be refreshed at least every =@ !s# Co!!ercial DA's can be"sed with cloc) speeds above


18/50

18

#!rst rea of length $ in S"RAM

A $ood indication of the perfor!ance is $iven by two para!eters1 latency and

bandwidth# The ter! !e!ory latency is "sed to refer to the a!o"nt of ti!e it ta)es totransfer a word of data to or fro! the !e!ory# In the case of readin$ or writin$ a sin$leword of data, the latency provides a co!plete indication of !e!ory perfor!ance# B"t, inthe case of b"rst operations that transfer a bloc) of data, the ti!e needed to co!plete theoperation depends also on the rate at which s"ccessive words can be transferred and on thesi3e of the bloc)#

;hen transferrin$ bloc)s of data, it is of interest to )now how !"ch ti!e is neededto transfer an entire bloc)# ince bloc)s can be variable in si3e, it is "sef"l to define aperfor!ance !eas"re in ter!s of the n"!ber of bits or bytes that can be transferred in onesecond# This !eas"re is often referred to as the !e!ory bandwidth# The bandwidth of a!e!ory "nit depends on the speed of access to the stored data and on the n"!ber of bitsthat can be accessed in parallel#

. Diu aout Rea5 !nl/ Memorie.

' !e!ories are non-volatile !e!ories, which !ean only readin$ of stored data,a !e!ory of this type is called read-only !e!ory#

A ROM cell



19/50

19

The dia$ra! shows a possible confi$"ration for a ' cell# A lo$ic val"e 5 is storedin the cell if the transistor is connected to $ro"nd at point %L otherwise, a < is stored# Thebit line is connected thro"$h a resistor to the power s"pply# To read the state of the cell, theword line is activated#

Th"s, the transistor switch is closed and the volta$e on the bit line drops to near 3ero

if there is a connection between the transistor and $ro"nd# If there is no connection to$ro"nd, the bit line re!ains at the hi$h volta$e, indicatin$ a


20/50

20

A card is si!ply pl"$$ed into a conveniently accessible slot# 6lash cards co!e in a variety of!e!ory si3es# Typical si3es are , >, =@ 'B and so on#

"la- 5ri2e

4ar$er flash !e!ory !od"les have been developed to replace, hard dis) drives#

These flash drives are desi$ned to f"lly e!"late the bard dis)s, to the point that they can befitted into standard dis) drive bays# The fact that flash drives are solid state electronicdevices that have no !ovable parts provides#

A%antages&

They have shorter see) and access ti!es, which res"lts in faster response#

They have lower power cons"!ption, which !a)es the! attractive for battery driven

applications, and they are also insensitive to vibration# Another type of ' chip allows the stored data to be erased and new data to be

loaded#

"is'a%asntages&

6lash drives are less stora$e capacity#

7i$her cost per bit and it will beco!e wea) after it has been written several ti!es#

6. Diu pee5, i'e an5 ot o Memorie

An ideal !e!ory wo"ld be fast, lar$e, and ine+pensive# a very fast !e!ory can bei!ple!ented if A' chips are "sed# B"t these chips are e+pensive beca"se their basic cellshave si+ transistors, which precl"de pac)in$ a very lar$e n"!ber of cells onto a sin$le chip#

It is i!practical to b"ild a lar$e !e!ory "sin$ A' chips# The alternative is to "sedyna!ic A' chips, which have !"ch si!pler basic cells and th"s are !"ch less e+pensive#

B"t s"ch !e!ories are si$nificantly slower#

Altho"$h dyna!ic !e!ory "nits in the ran$e of h"ndreds of !e$abytes can bei!ple!ented at a reasonable cost, the affordable si3e is still s!all co!pared to thede!ands of lar$e pro$ra!s with vol"!ino"s data#

A sol"tion is provided by "sin$ secondary stora$e, !ainly !a$netic dis)s, toi!ple!ent lar$e !e!ory spaces# /ery lar$e dis)s are available at a reasonable price, andthey are "sed e+tensively in co!p"ter syste!s#

They are !"ch slower than the se!icond"ctor !e!ory "nits# o a h"$e a!o"nt ofcost-effective stora$e can be provided by !a$netic dis)s# A lar$e, yet affordable, !ain

!e!ory can be b"ilt with dyna!ic A' technolo$y# This leaves A's to be "sed in s!aller"nits where speed is of the essence, s"ch as in cache !e!ories#

All of these different types of !e!ory "nits are e!ployed effectively in a co!p"ter#The entire co!p"ter !e!ory can be viewed as the hierarchy depicted# The fastest access isto data held in processor re$isters# Therefore, if we consider the re$isters to be part of the!e!ory hierarchy, then the processor re$isters are at the top in ter!s of the speed ofaccess# f co"rse, the re$isters provide only a !in"sc"le portion of the re2"ired !e!ory#



21/50

21

Memory hierarchy

At the ne+t level of the hierarchy is a relatively s!all a!o"nt of !e!ory that can bei!ple!ented directly on the processor chip# This !e!ory, called aprocessor cache, holdscopies of instr"ctions and data stored in a !"ch lar$er !e!ory that is provided e+ternally#

There are often two levels of caches# A pri!ary cache is always located on theprocessor chip# This cache is s!all beca"se it co!petes for space on the processor chip,which !"st i!ple!ent !any other f"nctions#

The pri!ary cache is referred to as level (L1) cache# A lar$er, secondary cache isplaced between the pri!ary cache and the rest of the !e!ory# It is referred to as level (L) cache# It is "s"ally i!ple!ented "sin$ A' chips# It is possible to have both 4l and 4>caches on the processor chip#

The ne+t level in the hierarchy is called the !ain !e!ory# This rather lar$e !e!oryis i!ple!ented "sin$ dyna!ic !e!ory co!ponents, typically in the for! of I''s, DI''s,or I''s# The !ain !e!ory is !"ch lar$er b"t si$nificantly slower than the cache !e!ory#In a typical co!p"ter, the access ti!e for the !ain !e!ory is abo"t ten ti!es lon$er thanthe access ti!e for the 4 < cache# Dis) devices provide a h"$e a!o"nt of ine+pensivestora$e# They are very slow co!pared to the se!icond"ctor devices "sed to i!ple!ent the!ain !e!ory#



22/50

22

A hard dis) drive is a device for storin$ and retrievin$ di$ital infor!ation, pri!arilyco!p"ter data# It consists of one or !ore ri$id rapidly rotatin$ discs coated with !a$netic!aterial and with !a$netic heads arran$ed to write data to the s"rfaces and read it fro!the!# D"rin$ pro$ra! e+ec"tion, the speed of !e!ory access is of "t!ost i!portance# The)ey to !ana$in$ the operation of the hierarchical !e!ory syste! in 6i$"re @#


23/50

23

Cache memory

T-e ai o Ca-e:

The caches are or$ani3ed on basis of bloc)s, the s!allest a!o"nt of data which canbe copied between two adacent levels at a ti!e# If data re2"ested by the processor ispresent in so!e bloc) in the "pper level, it is called a hit#

If data is not fo"nd in the "pper level, the re2"est is called a !iss and the data isretrieved fro! the lower level in the hierarchy# The fraction of !e!ory accesses fo"nd in the"pper level is called a hit ratio# The stora$e, which ta)es advanta$e of locality of accesses,is called a cache

The processor does not need to )now e+plicitly abo"t the e+istence of the cache# Itsi!ply iss"es ead and ;rite re2"ests "sin$ addresses that refer to locations in the!e!ory# The cache control circ"itry deter!ines whether the re2"ested word c"rrently e+istsin the cache#

The ead or ;rite operation is perfor!ed on the appropriate cache location# In thiscase, a read or !rite hit is said to have occ"rred# In a ead operation, the !ain !e!ory is

not involved#

6or a ;rite operation, the syste! can proceed in two ways# In the first techni2"e,called the !ritethrough protocol, the cache location and the !ain !e!ory location are"pdated si!"ltaneo"sly#

The second techni2"e is to "pdate only the cache location and to !ar) it as "pdatedwith an associated fla$ bit, often called the dirty or modi"ied #it#

The !ain !e!ory location of the word is "pdated later, when the bloc) containin$this !ar)ed word is to be re!oved fro! the cache to !a)e roo! for a new bloc)# Thistechni2"e is )nown as the write- bac), or copy-#ac$, protocol#

The write-thro"$h protocol is si!pler, b"t it res"lts in "nnecessary ;rite operationsin the !ain !e!ory when a $iven cache word is "pdated several ti!es d"rin$ its cacheresidency# Note that the write-bac) protocol !ay also res"lt in "nnecessary ;rite operationsbeca"se when a cache bloc) is written bac) to the !e!ory all words of the bloc) are writtenbac), even if only a sin$le word has been chan$ed while the bloc) was in the cache#

;hen the addressed word in a ead operation is not in the cache, a read !issocc"rs# The bloc) of words that contains the re2"ested word is copied fro! the !ain



24/50

24

!e!ory into the cache# After the entire bloc) is loaded into the cache, the partic"lar wordre2"ested is forwarded to the processor#

Alternatively, this word !ay be sent to the processor as soon as it is read fro! the!ain !e!ory# The latter approach, which is called load-through, or early restart, red"cesthe processorHs waitin$ period so!ewhat, b"t at the e+pense of !ore co!ple+ circ"itry#

D"rin$ a ;rite operation, if the addressed word is not in the cache, a !rite missocc"rs# Then, if the write-thro"$h protocol is "sed, the infor!ation is written directly intothe !ain !e!ory# In the case of the write-bac) protocol, the bloc) containin$ theaddressed word is first bro"$ht into the cache, and then the desired word in the cache isoverwritten with the new infor!ation#

Aeing a Ca-e:



25/50

25

A55re Mapping in Ca-e:

. it- an eample illutrate t-e eet o 5ierent a-e mapping te-niFue.

.

The process of )eepin$ infor!ation of !oved data bloc)s fro! !ain !e!ory tocache !e!ory is )nown as !appin$# 6or e+a!ple1 Consider a cache consistin$ of 1%#loc$s of 5@ (> words, and ass"!es that the !ain



26/50

26

!e!ory is addressable by a F=, is loaded in the cache, it is stored in cache bloc) 5# Bloc)s FM, are stored incache bloc)


27/50

27

Aoiati2e mapping:

'ore fle+ible !appin$ techni2"e a !ain !e!ory bloc) can be placed into any cachebloc) position# In this case, ta$ bits are re2"ired to identify a !e!ory bloc) when it isresident in the cache# The ta$ bits of an address received fro! the processor are co!paredto the ta$ bits of each bloc) of the cache to see if the desired bloc) is present# This is called

the associative-!appin$ techni2"e#

It $ives co!plete freedo! in choosin$ the cache location in which to place the!e!ory bloc)# Th"s, the space in the cache can be "sed !ore efficiently# A new bloc) thathas to be bro"$ht into the cache has to replace (eect an e+istin$ bloc) only if the cache isf"ll# In this case, we need an al$orith! to select the bloc) to be replaced# 'any replace!ental$orith!s are possibleL the cost of an associative cache is hi$her than the cost of a direct-!apped cache beca"se of the need to search all ta$ patterns to deter!ine whether a$iven bloc) is in the cache# A search of this )ind is called an associative search# 6orperfor!ance reasons, the ta$s !"st be searched in parallel#

Associati%e'mappe cache(

&et@Aoiati2e mapping

A co!bination of the direct- and associative-!appin$ techni2"es can be "sed# Bloc)sof the cache are $ro"ped into sets, and the !appin$ allows a bloc) of the !ain !e!ory toreside in any bloc) of a specific set# 7ence, the contention proble! of the direct !ethod is



28/50


29/50

29

The physical !ain !e!ory is not as lar$e as the address space spanned by anaddress iss"ed by the processor# ;hen a pro$ra! does not co!pletely fit into the !ain!e!ory, the parts of it not c"rrently bein$ e+ec"ted are stored on secondary stora$edevices, s"ch as !a$netic dis)s# f co"rse, all parts of a pro$ra! that are event"allye+ec"ted are first bro"$ht into the !ain !e!ory#

;hen a new se$!ent of a pro$ra! is to be !oved into a f"ll !e!ory, it !"streplace another se$!ent already in the !e!ory# The operatin$ syste! !oves pro$ra!sand data a"to!atically between the !ain !e!ory and secondary stora$e# This process is)nown as swappin$# Th"s, the application pro$ra!!er does not need to be aware ofli!itations i!posed by the available !ain !e!ory#

Techni2"es that a"to!atically !ove pro$ra! and data bloc)s into the physical !ain!e!ory when they are re2"ired for e+ec"tion are called virt"al-!e!ory techni2"es#%ro$ra!s, and hence the processor, reference an instr"ction and data space that isindependent of the available physical !ain !e!ory space# The binary addresses that theprocessor iss"es for either instr"ctions or data are called virt"al or lo$ical addresses# Theseaddresses are translated into physical addresses by a co!bination of hardware and softwareco!ponents#

If a virt"al address refers to a part of the pro$ra! or data space that is c"rrently inthe physical !e!ory, then the contents of the appropriate location in the !ain !e!ory areaccessed i!!ediately# n the other hand, if the referenced address is not in the !ain!e!ory, its contents !"st be bro"$ht into a s"itable location in the !e!ory before theycan be "sed#

+irt!al memory organization

A55re Tranlation o Virtual memor/:

The process of translatin$ a virt"al address into physical address is )nown as addresstranslation# It can be done with the help of ''U# A si!ple !ethod for translatin$ virt"al



30/50

30

addresses into physical addresses is to ass"!e that all pro$ra!s and data are co!posed offi+ed-len$th "nits called pages, each of which consists of a bloc) of words that occ"pyconti$"o"s locations in the !ain !e!ory#

%a$es co!!only ran$e fro! > to


31/50

31

!ain !e!ory location of each pa$e is )ept in a pa$e table# This infor!ation incl"des the!ain !e!ory address where the pa$e is stored and the c"rrent stat"s of the pa$e# An areain the !ain !e!ory that can hold one pa$e is called apage "rame#

The startin$ address of the pa$e table is )ept in a page ta#le #ase register# Byaddin$ the virt"al pa$e n"!ber to the contents of this re$ister, the address of the

correspondin$ entry in the pa$e table is obtained# The contents of this location $ive thestartin$ address of the pa$e if that pa$e c"rrently resides in the !ain !e!ory#

+0. Deine t-e term memor/. Eplain 2ariou to implement aoiati2e memor/.

'any data-processin$ applications re2"ire the search of ite!s in a table stored in!e!ory# They "se obect na!es or n"!ber to identify the location of the na!ed orn"!bered obect within a !e!ory space# 6or e+a!ple, an acco"nt n"!ber !ay besearched in a file to deter!ine the holderHs na!e and acco"nt stat"s# To search an obect,the n"!ber of accesses to !e!ory depends on the location of the obect and the efficiencyof the search al$orith!#

The ti!e re2"ired to find an obect stored in !e!ory can be red"ced considerably ifobects are selected based on their contents, not on their locations# A !e!ory "nitaddressed by the content is called an associative !e!ory or content addressable 'e!ory(CA'#

This type of !e!ory is accessed si!"ltaneo"sly and in parallel on the basis of datacontent rather than by specific address or location# In $eneral, the instr"ctions which areavailable in a special )ind of !e!ories li)e cache, ' and /irt"al !e!ory are addressedby content and not by address location#

#loc* iagram of associati%e memory

The bloc) dia$ra! of an associative !e!ory it consists of !e!ory array with !atchlo$ic for ! n-bit words and associated re$isters# The ar$"!ent re$ister (A and )ey re$ister( each have n-bits per word# Each word in !e!ory is co!pared in parallel with thecontents of the ar$"!ent re$ister# The words !atch with the word stored in the ar$"!ent



32/50

32

re$ister set correspondin$ bits in the !atch re$ister# Therefore, readin$ can beacco!plished by a se2"ential access to !e!ory for those words whose correspondin$ bitsin the !atch re$ister have been set#

The )ey re$ister provides a !as) for choosin$ a partic"lar field or bits in thear$"!ent word# nly those bits in the ar$"!ent re$ister havin$


33/50

33

Internal organization of typical cell of associati%e memory

The internal or$ani3ation of a typical cell# It consists of flip-flop as a stora$eele!ent and the circ"it for readin$, writin$ and !atchin$ the cell# By !a)in$ the writesi$nal lo$ic


34/50

34

The entire !e!ory can be loaded with new infor!ation by addressin$ each location inse2"ence# This will !a)e the !e!ory device a rando! access !e!ory for writin$ and acontent addressable !e!ory for readin$# 7ere, the address for the inp"t can be decoded asin a rando! access !e!ory#

++. Diu Aeing %9! De2ie.

In co!p"tin$, inp"t0o"tp"t, or I0, refers to the co!!"nication between aninfor!ation processin$ syste!, and the o"tside world# Inp"ts are the si$nals or datareceived by the syste!, and o"tp"ts are the si$nals or data sent fro! it# I0 devices are"sed by a person to co!!"nicate with a co!p"ter#

o!e of the inp"t devices are )eyboard, !o"se, trac) ball, oy stic), to"ch screen,di$ital ca!era, webca!, i!a$e scanner, fin$erprint scanner, barcode reader, !icrophoneand so on# o!e of the o"tp"t devices are spea)ers, headphones, !onitors and printers#Devices for co!!"nication between co!p"ters, s"ch as !ode!s and networ) cards,typically serve for both inp"t and o"tp"t#

I0 devices can be connected to a co!p"ter thro"$h a sin$le b"s which enables the

e+chan$e of infor!ation# The b"s consists of three sets of lines "sed to carry address, data,and control si$nals# Each I0 device is assi$ned a "ni2"e set of addresses# ;hen theprocessor places a partic"lar address on the address lines, the device that reco$ni3es thisaddress responds to the co!!ands iss"ed on the control lines#

The processor re2"ests either a read or a write operation, and the re2"ested dataare transferred over the data lines# The si!ple arran$e!ent of I0 devices to processor and!e!ory with sin$le b"s#

Memor/@mappe5 %9!: The arran$e!ent of I0 devices and the !e!ory share thesa!e address space is called !e!ory-!apped I0# ;ith !e!ory-!apped I0, any !achineinstr"ction that can access !e!ory can be "sed to transfer data to or fro! an I0 device#

6or e+a!ple, if DATAIN is the address of the inp"t b"ffer associated with the)eyboard, the instr"ction

Mo2e DATA%,R0



35/50

35

reads the data fro! DATAIN and stores the! into processor re$ister # i!ilarly, theinstr"ction

Mo2e R0,DATA!#T

sends the contents of re$ister 5 to location DATAUT, which !ay be the o"tp"t data b"fferof a display "nit or a printer# 'ost co!p"ter syste!s "se !e!ory-!apped I0# o!eprocessors have special In and "t instr"ctions to perfor! I0 transfers#

The hardware re2"ired to connect an I0 device to the b"s# The address decoderenables the device to reco$ni3e its address when this address appears on the address lines#The data re$ister holds the data bein$ transferred to or fro! the processor# The stat"sre$ister contains infor!ation relevant to the operation of the I0 device#

Both the data and stat"s re$isters are connected to the data b"s and assi$ned"ni2"e addresses# The address decoder, the data and stat"s re$isters, and the controlcirc"itry re2"ired to coordinate I0 transfers constit"te the deviceHs interface circ"it#

I,O interface for an inp!t e%ice

I0 devices operate at speeds that are vastly different fro! that of the processor#;hen a h"!an operator is enterin$ characters at a )eyboard, the processor is capable ofe+ec"tin$ !illions of instr"ctions between s"ccessive character entries# An instr"ction thatreads a character fro! the )eyboard sho"ld be e+ec"ted only when a character is availablein the inp"t b"ffer of the )eyboard interface# An inp"t character is read only once#

6or an inp"t device s"ch as a )eyboard, a stat"s fla$, IN, is incl"ded in theinterface circ"it as part of the stat"s re$ister# This fla$ is set to < when a character isentered at the )eyboard and cleared to 5 once this character is read by the processor#7ence, by chec)in$ the IN fla$, the software can ens"re that it is always readin$ validdata# This is often acco!plished in a pro$ra! loop that repeatedly reads the stat"s re$isterand chec)s the state of IN# ;hen IN beco!es e2"al to


36/50

36

+*. Eplain Program@ontrolle5 %9!.

Consider a si!ple e+a!ple of I0 operations involvin$ a )eyboard and a displaydevice in a co!p"ter syste!# The fo"r re$isters are "sed in the data transfer operations#e$ister TATU contains two control fla$s, IN and UT, which provide stat"s infor!ation

for the )eyboard and the display "nit, respectively# The two fla$s IO and DIO in thisre$ister are "sed in con"nction with interr"pts# They, and the EN and DEN bits in re$isterCNT4, Data fro! the )eyboard are !ade available in the DATAIN re$ister, and data sentto the display are stored in the DATAUT re$ister#

Registers in *eyboar an isplay interfaces(

The pro$ra! reads a line of characters fro! the )eyboard and stores it in a !e!oryb"ffer startin$ at location 4INE# Then, it calls a s"bro"tine %CE to process the inp"tline# As each character is read, it is echoed bac) to the display# e$ister 5 is "sed as apointer to the !e!ory b"ffer area# The contents of 5 are "pdated "sin$ the A"toincre!entaddressin$ !ode so that s"ccessive characters are stored in s"ccessive !e!ory locations#

Each character is chec)ed to see if it is the Carria$e et"rn (C character, which has

the ACII code 5D (he+# If it is, a 4ine 6eed character (ACII code 5A is sent to !ove thec"rsor one line down on the display and s"bro"tine %CE is called# therwise, thepro$ra! loops bac) to wait for another character fro! the )eyboard#

In pro$ra!-controlled I0 the processor repeatedly chec)s a stat"s fla$ to achievethe re2"ired synchroni3ation between the processor and an inp"t or o"tp"t device# Theprocessor polls the device#

There are two other co!!only "sed !echanis!s for i!ple!entin$ I0 operations1Interr"pts and direct !e!ory access# In the case of interr"pts, synchroni3ation is achievedby havin$ the I0 device send a special si$nal over the b"s whenever it is ready for a datatransfer operation#

+3. -at i DMA Diu DMA ontroller an5 DMA traner ;it- 5iagram eplainDMA !peration.

A special control "nit is provided to allow transfer of a bloc) of data directly betweenan e+ternal device and the !ain !e!ory, witho"t contin"o"s intervention by the processor#This approach is called direct memory access, or D'A#



37/50

37

D'A transfers are perfor!ed by a control circ"it that is part of the I0 deviceinterface# ;e refer to this circ"it as a D'A controller# The D'A controller perfor!s thef"nctions that wo"ld nor!ally be carried o"t by the processor when accessin$ the !ain!e!ory# 6or each word transferred, it provides the !e!ory address and all the b"s si$nalsthat control data transfer# ince it has to transfer bloc)s of data, the D'A controller !"stincre!ent the !e!ory address for s"ccessive words and )eep trac) of the n"!ber of

transfers#

Altho"$h a D'A controller can transfer data witho"t intervention by the processor, itsoperation !"st be "nder the control of a pro$ra! e+ec"ted by the processor# To initiate thetransfer of a bloc) of words, the processor sends the startin$ address, the n"!ber of wordsin the bloc), and the direction of the transfer#

n receivin$ this infor!ation, the D'A controller proceeds to perfor! the re2"estedoperation# ;hen the entire bloc) has been transferred, the controller infor!s the processorby raisin$ an interr"pt si$nal#

;hile a D'A transfer is ta)in$ place, the pro$ra! that re2"ested the transfer cannotcontin"e, and the processor can be "sed to e+ec"te another pro$ra!# After the D'A

transfer is co!pleted, the processor can ret"rn to the pro$ra! that re2"ested the transfer#

I0 operations are always perfor!ed by the operatin$ syste! of the co!p"ter inresponse to a re2"est fro! an application pro$ra!# The is also responsible fors"spendin$ the e+ec"tion of one pro$ra! and startin$ another# Th"s, for an I0 operationinvolvin$ D'A, the p"ts the pro$ra! that re2"ested the transfer in the Bloc)ed stateinitiates the D'A operation, and starts the e+ec"tion of another pro$ra!#

;hen the transfer is co!pleted, the D'A controller infor!s the processor by sendin$an interr"pt re2"est# In response, the p"ts the s"spended pro$ra! in the "nnablestate so that it can be selected by the sched"ler to contin"e e+ec"tion#

DMA !perationSingle -ransfer&

Each tri$$er ca"ses a sin$le transfer# The !od"le will disable itself when D'A+P n"!berof transfers has occ"rred# The D'A+A and D'A+DA re$isters set the addresses to betransferred to and fro!#

#loc* -ransfer&

An entire bloc) is transferred on each tri$$er# The !od"le disables itself when this bloc)transfer is co!plete# This transfer halts the C%U, and will transfer each !e!ory location oneat a ti!e#

#!rst'#loc* -ransfer&This is very si!ilar to Bloc) Transfer !ode e+cept that the C%U and the D'A transfer can

interleave their operation# This red"ces the C%U to >5Q while the D'A is $oin$ on, b"t theC%U will not be stopped alto$ether#

Repeate Single -ransfer1The sa!e as in$le Transfer !ode above e+cept that the !od"le is not disabled when thetransfer is co!plete#

Repeate #loc* -ransfer&



38/50

38

The sa!e as Bloc) Transfer !ode above e+cept that the !od"le is not disabled when thetransfer is co!plete#Repeate #!rst'#loc* -ransfer&The sa!e as B"rst Bloc) Transfer !ode above e+cept that the !od"le is not disabled whenthe transfer is co!plete#

Registers in a "MA interface

D'A controller re$isters that are accessed by the processor to initiate transferoperations# Two re$isters are "sed for storin$ the startin$ address and the word co"nt# Thethird re$ister contains stat"s and control fla$s# The 0; bit deter!ines the direction of thetransfer# ;hen this bit is set to < by a pro$ra! instr"ction, the controller perfor!s a readoperation, that is, it transfers data fro! the !e!ory to the I0 device#

therwise, it perfor!s a write operation# ;hen the controller has co!pletedtransferrin$ a bloc) of data and is ready to receive another co!!and, it sets the Done fla$to


39/50

39

conflicts, an ar#itration proced"re is i!ple!ented on the b"s to coordinate the activities ofall devices re2"estin$ !e!ory transfers#

The device that initiates data transfers on the b"s at any $iven ti!e is called the #usmaster# ;hen the c"rrent !aster relin2"ishes control of the b"s, another device can ac2"irethis stat"s# B"s arbitration is the process by which the ne+t device to beco!e the b"s

!aster is selected and b"s !astership is transferred to it# The selection of the b"s !aster!"st ta)e into acco"nt the needs of vario"s devices by establishin$ a priority syste! for$ainin$ access to the b"s#

There are two approaches to b"s arbitration1

Centralize

"istrib!te.

Centrali'e5 aritration

The b"s arbiter !ay be the processor or a separate "nit connected to the b"s# Abasic arran$e!ent in which the processor contains the b"s arbitration circ"itry#

A simple arrangement for b!s arbitration !sing a aisy chain

The processor is nor!ally the b"s !aster "nless it $rants b"s !astership to one ofthe D'A controllers# A D'A controller indicates that it needs to beco!e the b"s !aster byactivatin$ the B"s-e2"est line, BL this is an open-drain line for the sa!e reasons that theInterr"pt- e2"est line is an open-drain line#

The si$nal on the B"s-e2"est line is the lo$ical of the b"s re2"ests fro! all thedevices connected to it# ;hen B"s-e2"est is activated, the processor activates the B"s-:rant si$nal, B:


40/50

40

After it releases the b"s, the processor res"!es b"s !astership# This fi$"re showsthe ca"sal relationships a!on$ the si$nals involved in the arbitration process# Details ofti!in$, which vary si$nificantly fro! one co!p"ter b"s to another, are not shown#

Se/!ence of signals !ring transfer of b!s mastership for the e%ices

Ditriute5 aritration:

Distrib"ted arbitration !eans that all devices waitin$ to "se the b"s have e2"alresponsibility in carryin$ o"t the arbitration process, witho"t "sin$ a central arbiter# Asi!ple !ethod for distrib"ted arbitration# Each device on the b"s is assi$ned a @- bitidentification n"!ber# ;hen one or !ore devices re2"est the b"s, they assert the tart-Arbitration si$nal and place their @-bit ill n"!bers on fo"r open-collector lines, AB5thro"$h AB# The drivers are of the open-collector type# 7ence, if the inp"t to one driver ise2"al to one and the inp"t to another driver connected to the sa!e b"s line is e2"al to 5

the b"s will be in the low-volta$e state# In other words, the connection perfor!s an f"nction in which lo$ic < wins#



41/50

41

A istrib!te arbitration scheme

Ass"!e that two devices, A and B, havin$ ID n"!bers F and =, respectively, arere2"estin$ the "se of the b"s# Device A trans!its the pattern 5


42/50

42

The Ethernet is a widely "sed local area networ), providin$ a hi$h-speed connectiona!on$ co!p"ters in a b"ildin$ or a "niversity ca!p"s# A $iven co!p"ter !ay "se !orethan one b"s standard# A typical %enti"! co!p"ter has both a %CI b"s and an IA b"s, th"sprovidin$ the "ser with a wide ran$e of devices to choose fro!#

PC% (Perip-eral Component %nteronnet):

The %CI b"s is a $ood e+a!ple of a syste! b"s# It s"pports the f"nctions fo"nd on aprocessor b"s b"t in a standardi3ed for!at that is independent of any partic"lar processor#Devices connected to the %CI b"s appear to the processor as if they were connected directlyto the processor b"s#

They are assi$ned addresses in the !e!ory address space of the processor# Early%Cs "sed the -bit JT b"s, whose si$nals closely !i!ic)ed those of IntelHs 5+=processors#

Data Traner:

'ost !e!ory transfers involve a b"rst of data rather than "st one word# The reasonis that !ode! processors incl"de a cache !e!ory# The %CI is desi$ned pri!arily to s"pportthis !ode of operation# A read or a write operation involvin$ a sin$le word is si!ply treatedas a b"rst of len$th one# The b"s s"pports three independent address spaces1 !e!ory, I0,and confi$"ration# The first two are self-e+planatory# The I0 address space is intended for"se with processors, s"ch as %enti"!, that have a separate I0 address space#



43/50

43

An example of a comp!ter system !sing ifferent interface stanars

De2ie oniguration

;hen an I0 device is connected to a co!p"ter, several actions are needed toconfi$"re both the device and the software that co!!"nicates with it# The %CI si!plifiesthis process by incorporatin$ in each I0 device interface a s!all confi$"ration '!e!ory that stores infor!ation abo"t that device# The confi$"ration 's of all devices areaccessible in the confi$"ration address space#

&C&% (&mall Computer &/tem %nterae)

The acrony! CI stands for !all Co!p"ter yste! Interface# It refers to astandard b"s defined by the A!erican National tandards Instit"te (ANI "nder thedesi$nation J#


44/50

44

Universal erial B"s (UB is a si!ple and low cost !echanis! to connect thedevices s"ch as )eyboards, !o"se, ca!eras, spea)ers, printer and display devices to theco!p"ter# The UB s"pports two speeds of operation, called low-speed (#5introd"ced a third speed of operation, called hi$h-speed (@5 !e$abits0s#

The UB is 2"ic)ly $ainin$ acceptance in the !ar)et place, and with the addition ofthe hi$h-speed capability it !ay well beco!e the interconnection !ethod of choice for !ostco!p"ter devices#

ob0ecti%es& %rovide a si!ple, low-cost, and easy to "se interconnection syste! that overco!es

the diffic"lties d"e to the li!ited n"!ber of I0 ports available on a co!p"ter Acco!!odate a wide ran$e of data transfer characteristics for I0 devices, incl"din$

telephone and Internet connections Enhance "ser convenience thro"$h a Gpl"$-and-playG !ode of operation

De2ie C-arateriti

The different )inds of devices !ay be connected to a co!p"ter cover a wide ran$e off"nctionality# The speed, vol"!e, and ti!in$ constraints associated with data transfers toand fro! s"ch devices vary si$nificantly# In the case of a )eyboard, one byte of data is$enerated every ti!e a )ey is pressed, which !ay happen at any ti!e# These data sho"ldbe transferred to the co!p"ter pro!ptly#

ince the event of pressin$ a )ey is not synchroni3ed to any other event in -co!p"ter syste!, the data $enerated by the )eyboard are called asynchronous#6"rther!ore, the rate at which the data are $enerated is 2"ite low# It is li!ited by the speedof the h"!an operator to abo"t


45/50

45

fre2"ency or distance arisin$ fro! data s)ew# Therefore, it is possible to provide a hi$h datatransfer bandwidth by "sin$ a hi$h cloc) fre2"ency# As pointed o"t earlier, the UB offersthree bit rates, ran$in$ fro!


46/50

46

.S# Split b!s operations(

The !ode of operation described above is observed for all devices operatin$ at eitherlow speed or f"ll speed# 7owever, one e+ception has been necessitated by the introd"ctionof hi$h speed operation in UB version >#5# Consider the sit"ation in 6i$"re F#@# 7"b A isconnected to the root h"b by a hi$h-speed lin)# This h"b serves one hi$h-speed device, C,and one low-speed device, D# Nor!ally, a !essa$e to device D wo"ld be sent at low speedfro! the root h"b#

A55reing:

I0 devices are nor!ally identified by assi$nin$ the! a "ni2"e !e!ory address# Infact, a device "s"ally has several addressable locations to enable the software to send andreceive control and stat"s infor!ation and to transfer data# ;hen a UB is connected to ahost co!p"ter, its root h"b is attached to the processor b"s, where it appears as a sin$le

device# The host software co!!"nicates with individ"al devices attached to the UB bysendin$ pac)ets of infor!ation, which the root h"b forwards to the appropriate device in theUB tree#

#&? Protool:

All infor!ation transferred over the UB is or$ani3ed in pac)ets, where a pac)etconsists of one or !ore bytes of infor!ation# There are !any types of pac)ets that perfor!a variety of control f"nctions# The infor!ation transferred on the UB can be divided intotwo broad cate$ories1 control and data#Control pac)ets perfor! s"ch tas)s as addressin$ a device to initiate data transfer,ac)nowled$in$ that data have been received correctly, or indicatin$ an error#

Data pac)ets carry infor!ation that is delivered to a device# 6or e+a!ple, p"t ando"tp"t data are transferred inside data pac)ets#



47/50

47

.S# pac*et format(

The fo"r %ID bits identify one of


48/50

48

detect and discard d"plicate pac)ets# 7i$h-speed data pac)ets are se2"entially n"!bered 5,, 5, and so on#

+6. Diu %9! 5e2ie

Ge/oar5:The co!p"ter )eyboard is "sed to enter te+t infor!ation into the co!p"ter, as when

yo" type the contents of a report# The )eyboard can also be "sed to type co!!andsdirectin$ the co!p"ter to perfor! certain actions# In addition to the )eys of the !ain

)eyboard, )eyboards "s"ally also have a n"!eric )eypad, a ban) of editin$ )eys, and a rowof f"nction )eys alon$ the top# 4aptop co!p"ters, which don*t have roo! for lar$e)eyboards, often incl"de an RfnS )ey so that other )eys can perfor! do"ble d"ty#

Moue:The !o"se pointin$ device sits on yo"r wor) s"rface and is !oved with yo"r hand#

In older !ice, a ball in the botto! of the !o"se rolls on the s"rface as yo" !ove the !o"seand internal rollers sense the ball !ove!ent and trans!it the infor!ation to the co!p"tervia the cord of the !o"se#

The newer optical !o"se does not "se a rollin$ ball, b"t instead "ses a li$ht and a s!alloptical sensor to detect the !otion of the !o"se by trac)in$ a tiny i!a$e of the des)s"rface# ptical !ice avoid the proble! of a dirty !o"se ball, which ca"ses re$"lar !ice to

roll a s!oothly if the !o"se ball and internal rollers are not cleaned fre2"ently#

&anner:

A scanner is a device that i!a$es a printed pa$e or $raphic by di$iti3in$ it, prod"cin$an i!a$e !ade of tiny pi+els of different bri$htness and color val"es which are representedn"!erically and sent to the co!p"ter# canners scan $raphics, b"t they can also scan pa$esof te+t which are then r"n thro"$h C (ptical Character eco$nition software thatidentifies the individ"al letter shapes and creates a te+t file of the pa$eHs contents#



49/50

49

Monitor:CT (Cathode ay T"be, 4CD (4i2"id Crystal Display

Printer:

4aser %rinter, In)et %rinter, Dot !atri+ printer

+7. Diu aout 2ariou t/pe o R!M.

' stands for ead nly 'e!ory# It is type of internal !e!ory# The data andinstr"ctions in ' are stored by the !an"fact"rer at the ti!e of its !an"fact"rin$# Thisdata and pro$ra!s cannot be chan$ed or deleted after wards# The data or instr"ctionsstored in ' can only be read b"t new data or instr"ctions cannot be written into it#

' stores data and instr"ctions per!anently# ;hen the power is t"rned off, theinstr"ctions stored in ' are not lost# That is the reason ' is called non-volatile!e!ory#

' is "sed to store fre2"ently "sed instr"ctions and data to control the basic inp"t &o"tp"t operations of the co!p"ter# 'ostly, fre2"ently "sed s!all pro$ra!s li)e operatin$syste! ro"tines and data, are stored into the '# ;hen the co!p"ter is switched on,instr"ctions in the ' are a"to!atically activated# These instr"ctions help the bootin$process of co!p"ter#

H PR!M

%' is pro$ra!!able '# o!eti!es we !ay want to write so!e data on the '# Ins"ch cases we "se %'# Data can be written on it "sin$ special e2"ip!ent# It is i!portantto note that data can be written on %' only once b"t it cannot be re!oved fro! the%'#

H EPR!M

E%' is pro$ra!!able ' fro! which data can be pro$ra!!ed and erased# Note thatpro$ra!!in$ and erasin$ is not li!ited to "st one ti!e# It is done "sin$ "ltra violet li$ht#The downside to this that i re2"ires additional hardware to pro$ra! it# E%' is now "sedin !ost bios syste!s# This provides fle+ibility for the pro$ra!!er#

H EEPR!M

EE%' is the ne+t $eneration of '# It ta)es E%' to the ne+t level# As co!pared toE%', EE%' can be pro$ra!!ed "sin$ software technolo$y# The "ser hi!self canpro$ra! the ' "sin$ syste! software# The !ain advanta$e of this is yo" donHt needspecial hardware to pro$ra! it# This saves the pro$ra!!er a lot of !oney# This has beco!ethe do!inatin$ force in the BI ' !ar)et# 'aority of the !otherboards these days

co!e with EE%'#

Anna #ni2erit/ Iuetion

Part A


50/50

50

># Define the ter! interr"pt# 8ef# No#1 >

co oftunit v

Documents