Communication Synthesis:

Buses and Network-on-Chip (NOC)

Dr. Eng. Amr T. Abdel-Hamid

ELECT 1002

Spring 2008

System

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ip

Desig

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The SoC nightmare

The architecture is tightly coupled

Source: Prof Jan Rabaey CS-252-2000 UC Berkeley

DMA CPU DSP

MemCtrl. Bridge

MPEGI oo

The “Board-on-a-Chip”Approach

C

System Bus

Peripheral Bus

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Very long wires

1 ns (1 GHz) 0.1 ns (10 GHz)

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Year 2005 Year 2010

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Why NoC?

Global wire delays

increase exponentially or linearly by inserting repeaters The delay may exceed one clock cycle after repeater insertion In ultra-deep submicron processes, 80% or more of the delay of

critical paths will be due to interconnections Communication structures need to be designed first and then followed by

functional blocks

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Homogeneous SoC (MP-SoC)

CPU

MEM

CPU

MEM

CPU

MEM

CPU

MEM

CPU

MEM

CPU

MEM

CPU

MEM

CPU

MEM

Interconnection network (BUS, XBAR)

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Why not bus? Shared medium arbitrated bus, the most frequently used on-chip interconnect

architectures Pros

Simple, low area cost, and extensibility Cons

The intrinsic parasitic resistance and capacitance can be quite high for a long bus line

Every additional IP block adds to parasitic capacitance and causes increased propagation delay

The number of IP blocks that can be connected by the bus is limited

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On-Chip Communication

Bus based interconnect Low cost Easier to Implement Flexible

Networks on Chip Layered Approach Buses replaced with Networked

architectures Better electrical properties Higher bandwidth Energy efficiency Scalable

Irregular architectures Regular ArchitecturesBus-based architectures

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Network on Chip

Software

Transport

Network

Wiring

Separation of concerns

Software

Transport

Network

Wiring

Data Link Layer

Communication-based Design Orthogonalizes function and communication Builds on well-known models-of-computation and correct-by-

construction synthesis flow Parallels layered approach exploited by communications community

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NoCWhat is Network-on-Chip (NoC)?

• Leveraging existing computer networking principles to improve inter-component intra-chip communications for SoC.

• Each on chip component connected by switch to a particular comm wire(s)

• Improvement over standard bus based interconnections for SoC architectures in terms of throughput

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SOC Current Trend

Explicitly parallel SoC architectures

Integrating huge amounts of Memory in chip designs

Distributed Shared Memory Environments

Should allow Interconnection centric design flow and better predictability Physical design Closure Wire delay dominates gate delay

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Design goal of NoC

High throughput Low latency Less energy consumption Small area requirements

Network-on-Chip Basics: Architectures Routing Strategies Evaluation

IP Core

CNI

Router Logic

To/From Network

Figure 1: NoC Architecture

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Routing: Circuit/Packet Switching

Circuit Switching

• Dedicated path, or circuit, is established over which data packets will travel

• Naturally lends itself to time-sensitive guaranteed service due to resource allocation

• Reservation of bandwidth decreases overall throughput and increases average delays

Packet Switching

• Intermediate routers are now responsible for the routing of individual packets through the network, rather than following a single path

• Provides for so-called best-effort services

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Routing: Wormhole/Virtual Cut ThroughWormhole Switching

• Message is divided up into smaller, fixed length flow units called flits

• Only first flit contains routing information, subsequent flits follow

• Buffer size is significantly reduced due to the limitation on the number of flits needed to be buffered at any given time

Virtual Cut Through Switching

• Much like Wormhole switching

• Header flit can travel ahead and undergo processing while remaining flits are still navigating the network

• Higher acceptance rates and lower latencies than Wormhole

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Wormhole Switching

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Routing: Contention

•Contention occurs when routers or IP blocks attempt to send data over the same link at the same time

• For Circuit switching, contention is resolved at the time of actual connection setup

• For packet switching, contention resolution is handled at a much finer level, by the router buffering and scheduling individual packets of information

• Better overall performance for packet switched networks at the cost of lack of service guarantee

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Architectures: SPIN• SPIN: Scalable, Programmable, Integrated Network

• Every level has same number switches

• Network grows like (NlogN)/8

• Trades area overhead and decreased power efficiency for higher throughput

• Illustrative of performance vs. power consumption

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Architectures: CLICHE

•CLICHÉ: Chip-Level Integration of Communicating Heterogeneous Elements

• Two-dimensional mesh network layout for NoC design

• All switches are connected to the four closest other switches and target resource block, except those switches on the edge of the layout

• Connections are two unidirectional links

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Architectures: Torus

•Similar to mesh based architectures

• Wires are wrapped around from the top component to the bottom and rightmost to leftmost

• Smaller hop count

• Higher bandwidth

• Decreased Contention

• Increased chip space usage

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Architectures: Folded Torus•Similar to Torus

•Torus, the long end-around connections can yield excessive delays

•Avoided by folding the torus

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Architectures: Octagon•Standard model: 8 components, 12 interconnects

• Design complexity increases linearly with number of nodes

• Largest packet travel distance is two hops

• High throughput

• Shortest path routing easy to implement

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Architectures: BFT•BFT: Butterfly Fat Tree

• Each node in tree model has coordinates (level, position) where level is depth and position is from left to right

• Leaves are component blocks

• Interior nodes are switches

• Four child ports per switch and two parent ports

•LogN levels, ith level has n/(2^i+1) switches, n = leaves (blocks)

• Use traffic aggregation to reduce congestion

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Network interface

Open Core Protocol (OCP) An interface standard between IP cores and the interconnection

fabric

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Packet Format

Type: Head, Data, Tail and CompleteVCID: Virtual Channel IdentifierRoute: ‘N’ bit route field with last 2 bits specifying the Route to be used in the next controller

00 - Left01 - Right

10 - Straight11 - Extract

Data: Actual Data field

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Routing Example

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Simulation

A simulator is used to investigate various metrics:

•Each system consists of 256 functional IP blocks

•Wormhole routing is used

•User can choose uniform and localized traffic

•Support both Poisson and self-similar message injection distributions

A flit is only one word (36 bits, 4 bits are for packet framing).

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Area comparison

SPIN and Octagon have a considerably higher silicon area overhead.

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Projected performance