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COMP541COMP541

Interrupts, DMA, Serial I/OInterrupts, DMA, Serial I/O

Montek SinghMontek Singh

April 18, 2012April 18, 2012

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InterruptsInterrupts Two main kindsTwo main kinds InternalInternal

Error when executing an instructionError when executing an instructionFloating point exceptionFloating point exceptionVirtual memory page faultVirtual memory page faultTrying to access protected memoryTrying to access protected memory Invalid opcode!Invalid opcode!

System call requested by softwareSystem call requested by softwareTo request OS servicesTo request OS services

ExternalExternal I/OI/O

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InternalInternal More complicated because two possible More complicated because two possible

actionsactions may abort instructionmay abort instruction

access to protected memory not allowedaccess to protected memory not allowed or, OS corrects the situation and restarts instructionor, OS corrects the situation and restarts instruction

e.g., virtual memory page faulte.g., virtual memory page fault

Question:Question: What happens for arithmetic overflow/divide-by-0?What happens for arithmetic overflow/divide-by-0?

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When Interrupt OccursWhen Interrupt Occurs Interrupt enable registerInterrupt enable register

Sometimes levels of interrupts individually Sometimes levels of interrupts individually enabled/disabledenabled/disabled

PC is changed to new locationPC is changed to new location One or more interrupt locations storedOne or more interrupt locations stored

““vectored interruptsvectored interrupts”” Or a fixed locationOr a fixed location

example: MIPS (e.g., 0xC000 0000)example: MIPS (e.g., 0xC000 0000)

Old PC saved to register or stackOld PC saved to register or stack Many machines have stack pointerMany machines have stack pointer

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RegistersRegisters Sometimes registers saved by Sometimes registers saved by hardwarehardware

Some machines have one or more sets of registersSome machines have one or more sets of registers

Often: software must save registersOften: software must save registers Push them onto stackPush them onto stack

Return from interruptReturn from interrupt Some CPUs provide a special instruction to return Some CPUs provide a special instruction to return

from interruptfrom interrupt““rfirfi”” or or ““iretiret””

Others use the standard procedure return instructionOthers use the standard procedure return instruction jr, ret, etc.jr, ret, etc.

Restore registers before returningRestore registers before returning

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Cause of InterruptCause of Interrupt Need way to determine what caused interruptNeed way to determine what caused interrupt

Note it can be more than one thingNote it can be more than one thing

Vectored InterruptsVectored Interrupts Different types cause branches to different locationsDifferent types cause branches to different locations Sometimes prioritizedSometimes prioritized

Register to store causeRegister to store cause ““Cause” registerCause” register

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Supervisory ModeSupervisory Mode Modern computers have user mode and one or Modern computers have user mode and one or

more “supervisory modes”more “supervisory modes” User mode restrictedUser mode restricted

CanCan’’t write to many system registers, such as t write to many system registers, such as interrupt enableinterrupt enable

CanCan’’t write to some parts of memoryt write to some parts of memory Usually I/O restrictedUsually I/O restricted

Interrupts cause switch to supervisory modeInterrupts cause switch to supervisory mode In this mode, software has access to several In this mode, software has access to several

privileged parts of the system privileged parts of the system e.g.: kernel memory, IE register, etc.e.g.: kernel memory, IE register, etc.

Question: Which interrupts?Question: Which interrupts?

Some Interrupt HardwareSome Interrupt Hardware An example An example

implementationimplementation Interrupts ORedInterrupts ORedResponse if IE and at Response if IE and at

end of instructionend of instructionAck interruptAck interruptVector address to PCVector address to PCSave PC on stackSave PC on stack

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Potential MicrocodePotential MicrocodeThe following is a typical sequence of actions The following is a typical sequence of actions

taken by the CPU upon triggering of an taken by the CPU upon triggering of an interrupt:interrupt:

SP SP SP – 1 SP – 1M[SP] M[SP] PC PCSP SP SP – 1SP – 1M[SP] M[SP] PSRPSR– PSR is processor status registerPSR is processor status register

EI EI 00INTACK INTACK 11PC PC IVADIVAD

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Return SimilarReturn Similar Very similar to return from procedureVery similar to return from procedure Some additional actionsSome additional actions

PSR holds IE bitPSR holds IE bit Restoring PSR turns interrupts onRestoring PSR turns interrupts on

Exception (from Patterson Hennessey, multicycle Exception (from Patterson Hennessey, multicycle MIPS)MIPS)

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Just two causes

PC – 4 stored

Branch to fixed addr

Undefined instruction and arithmetic overflow

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Restarting Instruction?Restarting Instruction? Imagine the interrupt (exception) was a page Imagine the interrupt (exception) was a page

faultfault Need to get the page, and then Need to get the page, and then rerunrerun the instruction the instruction

Keeping instructions simple/short helps out!Keeping instructions simple/short helps out! Otherwise may need to save some intermediate stateOtherwise may need to save some intermediate state

Imagine block-move instruction such as the Pentium MOVSImagine block-move instruction such as the Pentium MOVS– moves/copies an entire string (of variable length) in a single moves/copies an entire string (of variable length) in a single

instruction!instruction!

Types of I/OTypes of I/O

Programmed I/OProgrammed I/O

Direct Memory Access (DMA)Direct Memory Access (DMA)

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Direct Memory Access (DMA)Direct Memory Access (DMA) Programmed I/OProgrammed I/O is when CPU reads/writes is when CPU reads/writes

every wordevery word Problem: overhead is high; nothing else getting done Problem: overhead is high; nothing else getting done

on CPUon CPU Especially for mass-storage devices like diskEspecially for mass-storage devices like disk

DMA: Let device controller read/write directly DMA: Let device controller read/write directly to memoryto memory CPU goes about its usual business of executing other CPU goes about its usual business of executing other

instructionsinstructions typically cannot access memory while DMA is going on!typically cannot access memory while DMA is going on!

Challenges?Challenges?

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ProtocolProtocol DMA protocolDMA protocol

DMA device takes over main busDMA device takes over main bus Becomes Becomes bus masterbus master Asserts addressesAsserts addresses Basically interfaces to memory or memory controllerBasically interfaces to memory or memory controller

How?How? DMA device requests bus (assert BR)DMA device requests bus (assert BR) CPU grants request (assert BG)CPU grants request (assert BG) CPU takes its signals to Hi-ZCPU takes its signals to Hi-Z

now DMA can use its signals to connect with memorynow DMA can use its signals to connect with memory no conflict with CPU’s signals (they are floating)no conflict with CPU’s signals (they are floating)

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Transfer ModesTransfer Modes Several types of transfer modesSeveral types of transfer modes

ContinuousContinuous: DMA controller transfers all data (say a : DMA controller transfers all data (say a disk sector) at oncedisk sector) at onceAs many memory cycles as dataAs many memory cycles as data

BurstBurst: DMA controller cycle steals, takes a cycle at : DMA controller cycle steals, takes a cycle at end of every CPU instructionend of every CPU instruction

Note: today’s processors are more Note: today’s processors are more sophisticatedsophisticated there is a memory controller (“Northbridge”)there is a memory controller (“Northbridge”) sits in-between CPU and memorysits in-between CPU and memory Why? Memories are more complex, caches, etc.Why? Memories are more complex, caches, etc.

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End of DMAEnd of DMA Controller needs to inform CPUController needs to inform CPU

De-assert BRDe-assert BR Then CPU lowers BG and proceedsThen CPU lowers BG and proceeds

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DMA ControllerDMA Controller Needs typical I/O signalsNeeds typical I/O signals

Interrupt requestInterrupt request Status of deviceStatus of device

Also needs controls for DMA transferAlso needs controls for DMA transfer Memory addressMemory address Word countWord count

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Block DiagramBlock Diagram

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Typical Driver InterfaceTypical Driver Interface Software driversSoftware drivers

Set the memory addressSet the memory address Set word countSet word count Assert “GO” (usually bit in control word)Assert “GO” (usually bit in control word) DMA controller starts copying …DMA controller starts copying … … … and requests interrupt when transfer completeand requests interrupt when transfer complete

Trends in CommunicationsTrends in Communications Older bus standards, such as ISA and PCI, were Older bus standards, such as ISA and PCI, were

parallel (conventional parallel (conventional ““busbus””)) Newer (PCI Express) use serial channels Newer (PCI Express) use serial channels

(lanes)(lanes) So slots for slower devices can be x1So slots for slower devices can be x1 Slots for devices such as GPUs can be x16 (max x32 Slots for devices such as GPUs can be x16 (max x32

in spec)in spec)

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16 lane PCI-E (below)1 lane (right)

DisksDisks Change from ATA/IDE to SATAChange from ATA/IDE to SATA

IDE had 16 data channelsIDE had 16 data channels SATA has 2 twisted pair (xmit and recv)SATA has 2 twisted pair (xmit and recv)

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RS-232/UARTRS-232/UART Called Called ““AsynchronousAsynchronous””

But both sides have precise clocksBut both sides have precise clocks Agree on speedAgree on speed Receiver syncs during start bitReceiver syncs during start bit

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USBUSB One masterOne master

The PCThe PC

Idea was to have thin Idea was to have thin cables and plug and cables and plug and playplay

Specs include Specs include hardware and hardware and softwaresoftware We only cover We only cover

hardwarehardware

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USB – Packet serial I/OUSB – Packet serial I/O Four wires totalFour wires total +5v and GND+5v and GND Two signal wiresTwo signal wires

Twisted pairTwisted pair Differential signalingDifferential signaling Differential 1 is D+ > 2.8v and D- < 0.3vDifferential 1 is D+ > 2.8v and D- < 0.3v Differential 0 is oppositeDifferential 0 is opposite Also a single-ended zero when D+ & D- low (end of Also a single-ended zero when D+ & D- low (end of

packet, reset, disconnect)packet, reset, disconnect)

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SpeedSpeed Three speedsThree speeds

High is 480 Mb/sHigh is 480 Mb/s Full is 12 Mb/sFull is 12 Mb/s Low is 1.5 Mb/sLow is 1.5 Mb/s New Super Speed, 5Gb/s!!New Super Speed, 5Gb/s!!

Pull-up indicates full/lowPull-up indicates full/low High speed starts as full, then High speed starts as full, then

handshakes and transitionshandshakes and transitions High and low speeds interpret zeros High and low speeds interpret zeros

and ones inverted.and ones inverted.

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CodingCoding NRZINRZI

Non-Return to Zero InvertedNon-Return to Zero Inverted Transition if sending 0, none if sending 1Transition if sending 0, none if sending 1

Bit stuffingBit stuffing Since a string of 1s causes no transitions, Since a string of 1s causes no transitions,

synchronization may be lostsynchronization may be lost A zero is stuffed in after six consecutive onesA zero is stuffed in after six consecutive ones

Sync fieldSync field Each packet starts with a syncEach packet starts with a sync 8 bits: 000000018 bits: 00000001

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PacketsPackets WonWon’’t go into t go into

detailsdetails

SummarySummary Many types of I/OMany types of I/O

memory-mapped is most commonmemory-mapped is most commondifferent devices given different address rangesdifferent devices given different address ranges

many different device protocolsmany different device protocolsPS/2: keyboard, micePS/2: keyboard, miceRS-232: serial portsRS-232: serial portsUSB: most common todayUSB: most common todayalso Firewire, Thunderbolt, … also Firewire, Thunderbolt, … ethernetethernet

also monitors, displaysalso monitors, displayswe did VGA (other higher resolutions also possible)we did VGA (other higher resolutions also possible)DVI is most common todayDVI is most common today

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Conclusion of this courseConclusion of this course What did we learn this semester?What did we learn this semester?

Combinational logicCombinational logic Sequential logic, finite-state machinesSequential logic, finite-state machines Basic building blocksBasic building blocks

registers, countersregisters, countersadders, subtractors, ALUsadders, subtractors, ALUsmemories, and memory-mapped I/Omemories, and memory-mapped I/Odatapathsdatapaths

VerilogVeriloghierarchical designhierarchical designdisplay interfaces, input devices, debouncingdisplay interfaces, input devices, debouncing

CPUsCPUssingle-cycle, multicyclesingle-cycle, multicyclepipelining, hazards, forwarding, stallingpipelining, hazards, forwarding, stalling

Built an entire MIPS CPU!Built an entire MIPS CPU! 31

Some Tips for your final projectSome Tips for your final project Use MARS to assemble your program!Use MARS to assemble your program!

use: .text 0x80000000use: .text 0x80000000 then simply copy all the machine code into your projectthen simply copy all the machine code into your project

SLTSLT if you want to implement SLT, talk to me!if you want to implement SLT, talk to me!

BEQ, BNEBEQ, BNE make sure “delayed branching” is off in MARSmake sure “delayed branching” is off in MARS

JJ JAL, JRJAL, JR

not necessary, but could simplify your codenot necessary, but could simplify your code if you want to use procedure callsif you want to use procedure calls

PC=PC+4 (not 8) because our MIPS is unpipelined, no PC=PC+4 (not 8) because our MIPS is unpipelined, no delayed jumpsdelayed jumps

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TimelineTimeline April 19 (Thu):April 19 (Thu):

Test #1 graded, ready for pickupTest #1 graded, ready for pickup

April 20 (Fri):April 20 (Fri): First set of final project demosFirst set of final project demos HW #2 dueHW #2 due Test #2 (take home) releasedTest #2 (take home) released

April 23 (Mon):April 23 (Mon): Tentative grades for those already demo’edTentative grades for those already demo’ed Second set of final project demosSecond set of final project demos Hw #2 due (last chance)Hw #2 due (last chance)

April 25 (Wed):April 25 (Wed): Tentative grades for those already demo’edTentative grades for those already demo’ed Last chance to demo final projectLast chance to demo final project

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