comparchch12l09cachecoherencepart1
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Lesson 09:Cache Coherence Problem and Cache
synchronization solutions─ Part 1
Chapter 12: Multiprocessor Architectures
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Objective
• To understand cache coherence problem• To learn the methods used to solve it• To understand the synchronization
mechanisms for maintaining cache coherence• Cache-coherence problem protocol MESI
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Disadvantage of Bus shared systems
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Disadvantage of Bus shared systems
• Only some of the data in the memory directly accessible by each processor, since a processor can only read and write its local memory system
• Accessing data in another processor’s memory requires communication through the network
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Possibility that two or more copies of a given datum
• Two or more copies could exist in different processors’ memories
• The copies may result because of data sharing, because of process migration from one processor to another, or because of an I/O operation
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Cache coherence problem
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Cache coherence problem
• When two or more copies of a given datum exist in different processors’ memories, it may lead to different processors having different values for the same variable
• Major source of complexity in shared-memory systems
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Cache coherence problem
• Problem of inconsistency between a cached copy and the shared memory or between cached copies themselves due to the existence of multiple cached copies of data
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Cache Coherence Protocols─ snooping bus protocols
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Maintaining cache coherence using cache snooping
• Cache snooping easy in a bus-based multiprocessor
• Each processor in the system can observe the state of the memory bus, called cache snooping
• Cache snooping─ allows each processor to see any requests that other processors make to the main memory
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Cache coherence protocol of a shared memory multiprocessor
• Defines how the data may be shared and replicated across processors
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Memory-coupling (consistency) model
• Defines when the programs running on the processors will see operations executed on other processors
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Cache coherence protocol
• Defines the specific set of actions that are executed to keep each processor’s view of the memory system consistent
• Operates on cache lines of data at a time, communicating an entire line between processors when necessary, rather than just sending a single word
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Two categories of Cache-coherence protocols
• Snoopy bus protocols for shared buses • Directory based protocols for the multistage
networks
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Two categories of snooping bus protocols
• Invalidation-based protocols• Update-based protocols
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Invalidation based cache protocol
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Invalidation based protocols─MESI Protocol
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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MESI Protocol
• Commonly used invalidation-based cache-coherence protocol
• Each line in a processor’s cache assigned one of four states to track which caches have copies of the line
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Four possible tates of a cache line in MESI Protocol
• Cache line state─M, E or S or I (Modified, Exclusive, Shared, or Invalid)
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Invalidation based cache protocol
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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State I
• The invalid state means that the processor does not have a copy of the line
• Any access to the line will require that the shared-memory system send a request message to the memory that contains the line to get a copy of the line
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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State S
• The shared state means that the processor has a copy of the line, and that one or more other processors also have copies
• The processor may read from the line, but any attempt to write the line requires that the other copies of the line be invalidated
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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State E
• If a line is in the exclusive state, the processor is the only one that has a copy of the line, but it has not written the line since it acquired the copy
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Advantage of State E
• The definition of the exclusive unmodified state of data entirely avoids the transition to invalidations on write operations to unmodified non-shared blocks
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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State M
• The modified state means that the processor is the only one with a copy of the line, and it has written the line since it acquired the copy
• In both the exclusive and modified states, the processor may read and write the line freely
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Different snoopy bus protocols
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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The states in different snoopy bus protocols
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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The meaning of terms─ dirty and invalid dirty
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Summary
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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• Cache coherence problem• Maintenance of identical copies when a
copy is written and two or more copies already exist
• Snoopy bus protocols• Invalidation based snoopy bus protocols
We Learnt
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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End of Lesson 04 on Cache Coherence Problem and Cache
synchronization solutions─ Part 1