Compilation of Data on the Current TEC Analog

Electronics

--- J. Paradiso

Oct., 1983

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COMPILATION OF DETAILS ON CURRENT TEC ANALOG ELECTRONICS

--- J. ParadisoOct., 1983

CONTENTS .....

I) Overview

II) TEC PreamplifiersA) CE-3 Conventional first-stage preamplifierB) CB-4 Conventional second-stage preamplifier

_· .. ~ ~i' C) CE-3A All-anode first-stage preamplifierD) CB-4A All-anode second-stage preamplifierE) CE-3P First-stage preamplifier w. improved PW protection

III) Other Important CircuitsA) Differential AmplifierB) General Purpose Shaping AmplifierC) Fast Positive Fan-out

IV) Imported PreamplifiersA) Common-base preamplifierB) Slow charge-sensitive preamplifierC) Fast charge-sensitive preamplifier

·'· �

I) Overview

In order to avoid chaos and unnecessary entropy increase,all important information on the TEC analog circuitry has beenassembled in this writeup. The "conventional" TEC analog systemis diagrammed in Fig. (1) on the following page. Section II)of this report sketches the preamplifier models in current use,and Section III) describes additional circuitry needed toshape and process the signals. Each circuit descriptioncontains a brief writeup, schematic, and, if ertinent, printlayouts and additional diagrams. Component placement is notindicated on the print layouts; one must use an existingprototype or production model for reference.

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II) TEC Preamplifiers

All designs in use are based upon a common-emitter-w.

feedback first stage (CE-3) amplifier cascaded with a common-base

second stage (CB-4). The first-stage is kept inside the gasvolume of the test chamber and it drives a 100Q twisted pair

approx. 40 cm. to the exterior of the chamber, series terminatedinto the second-stage input. The second-stage outputs drive50Q cables to the counting room for further manipulation.

Design details follow....

II-A) CE-3 Conventional first-stage preamplifier

The schematic (Fig. 2) shows the anode (optimized for

negative input signals), and PW (optimized for positive input

signals) circuits; identical except for the use of NPNtransistors in the former, and PNP in the latter. The output

currently drives a 100Q twisted pair to a CB-4 second stage;

if a CB-4 is not used, one must DC isolate the terminationresistor from the line via a series capacitor. All transistors

are ST-23 -chips. This is an inverting, current-sensitive

amplifier.The printed circuit (Fig. 3) contains one anode and two

PW circuits.

Specs.

Rise-time: T = 3. nsec.r

Noise: 2000 e RMS over full bandwith

Input Impedance: Z. = 140Q (inc. input resistor)in

Power Diss.: P= 13 mW/channelD

·Gain: Anode: 32 dB = 5 mV/A (Assuming above inout impedance)PW: 29 dB = 4 mV/A -

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II-B) CB-4 Conventional Second-stage amplifier

The schematic (Fig. 4) shows the anode (optimized forpositive input signals) and PW (optimized for negative inputsignals) designs. The C3-4 is intended to be driven by the CE-3outputs, and it will drive 50Q cables.

Note: Each amplifier will drive up to 2 volts in theoptimized direction into 50Q, however the linearity of thecascade degrades after 500 mV of output (ref. writeup by H.Anders et. al.). The TEC is generally run below this limit,but if larger range is desired, a common-emitter-feedback stage(analagous to the first stage) may be a better choice. Onecould as well consider using a fast monolithic for the secondstage; however until techonology improves further, it is bestto keep the head amplifier (which is performance-critical)discrete.

The printed circuit layout (Fig. 5) contains one anodeand two PW circuits.

Specs ....

Rise-time: Tr< 3 nsec.

Input impedance: Z. 100Q (primarily the termination resistor)in

Power Diss.: P = 140 mW/channel

Gain: Anode: 13 dBPW: 12 dB

Gain of CE-3/CB-4 cascade (2 mV in CE-3, 320 mV out CB-4):Anode: 44 dB = 22 mV/pAPW: 40 dB = 15 mV/IA

Figure 4

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II-C) CE-3A All-anode first-stage preamplifier

As seen in the schematic (Fig. 6), this circuit is identicalto the CE-3 design, except for the the print layout (Fig. 7),which contains 3 anode channels (the two PW channels of theCE-3 are replaced). This circuit is intended to drive a CB-4A.

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Figure 6

FIRST STAGE PREAMPLIFIER

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II-D) CB-4A All-anode second-stage amplifier

As seen in the schematic (Fig. 8), this circuit isidentical to the CB-4 design, except for the print layout(Fig. 9), which contains 3 anode channels ( the two PW channelsof the CB-4 have been replaced). This circuit is intended tobe driven by a CE-3A.

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SECOND STAGE PREAMPLIFIER

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II-E) CE-3P First-stage preamplifier with improved PW protection

In order to better protect the PW channels (which seemprone to destructive breakdown), a modification of the CE-3pickup channels was made, where an anode-type NPN front-endreplaced the PW PNP front-ends (which seemed more breakdown-sensitive). This required an additional PNP transistor per PWchannel to buffer the NPN output and drive the negative PWoutput signals down the 100Q twisted pair. This transistor,however, raises the quiescent power dissipation of the PW channelsto approx. 24 mW/channel. The anode circuit remains unaltered.The schematic is given in Fig.10), but no print layout exists,since the modification was handwired onto the CE-3 boards.Due to better performance of the NPN front-end, this circuityields about 3 dB more gain in the PW channels over theconventional CE-3.

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III) OTHER IMPORTANT CIRCUITS

III-A) Differential Amplifier

Fig. 11 is a schematic of the circuit used to subtract

the two PW signals. The inverting and non-inverting inputs

to Al are balanced via two trimmer potentiometers (accessable

at the front panel). Trimmer capacitor T1 is adjusted to null

any overshoot at the amplifier output. The amplifier rise-time

is under 10 nsecs., and the "1-2" output will drive up to ±1 volt

P-P into a 50Q load.

Figs. 12 and 13 are the PC layout for a quad NIM module.

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III-B) General Purpose Shaper

Fig. 14 is a block diagram of the circuit used to shapeboth anode and PWD (Pickup-Wire Difference) signals. The firststage is a pole/zero differentiation (5-10 nsec) which clipsthe input signal and attenuates any RC tail from the amplifierresponse. This is followed by a fixed gain stage to restorethe signal amplitude, whereupon another pole/zero (T = 500 nsec.)is applied to compensate for the slow ion tail. The signal canthen be integrated if desired, and the gain and baseline ofthe output stage can be adjusted to fit any FADC input requirements.A baseline restorer is in DC feedback around the output stage tocompensate for any DC shifts. The schematic is given in Fig. 15.

Fig. 16 shows the location of all shaper adjustments onthe printed circuit. The differentiation time-constant (TC)of the first stage is adjusted to the point at which the signalbegins to be attenuated; the corresponding pole/zero (PZ) constantis adjusted to remove any undershoot (at the 10-20 nsec. level).The second-stage TC and PZ are then adjusted to remove the slow(= 500 nsec.) tail; the TC controls the timing at which thecorrection has effect (and must be adjusted to "balance" thetiming of the signal tail), and the PZ compensates forover/undershoot. There is a slight correlation between first-and second-stage differentiations; the process sketched aboveshould be repeated for optimum shaping.

The integration stage is not currently used (both potsfull off {where there is no effect}), but if desired, these potsmay be trimmed to "smooth" the signal.

All of the above adjustments should be performed with thegain pot set near minimum. After the signal shape is adjusted,use this pot to bring the signal amplitude up to the desired level.

The DC bias level at the output is adjusted 0 ±1 Voltby the bias pot. The baseline restorer compensation pot shouldbe adjusted to the point at which the shaper output begins tooscillate, and then backed off to a "inch" after the oscillationceases. It's always good practice to make this adjustmentfirst (especially if the shaper is oscillating; this is generallywhy). The hardware strap indicated in Fig. 15 selects apositive or negative bias increment (at present all units arewired positive).

The shaper accepts either polarity input signals up to300 mV P-P (beware of input stage saturation) and the output

will drive over ±1 volt into a 500 load.The output signal will rise in =7 nsec.Figs. 17 and 18 show the PC layout for a quad NIM module.

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III-C) Fast Positive Fan-Out

Fig. 19 shows the schematic for a circuit which isdesigned to fan out the second-stage anode amplifier (positive)signals. One such input drives two independent non-invertingoutputs and two independent inverting outputs. The outputs willdrive over 1 volt into a 50Q load, and rise in under 3 nsec(non-inverting), and 5 nsec (inverting). The circuit drops

30% in amplitude between input and outputs.Figs. 20 and 21 show the PC layouts for a quad NIM

module. One very useful feature of this circuit is that thesame layout can be used to accept either positive or negativeinput signals. To accept negative inputs, one need only substitutePNP transistors for NPN's (and vice-versa) and reverse thesupply voltages.

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IV) IMPORTED AMPLIFIERS

This section presents 3 amplifier designs developed atBNL which prove puite useful in TEC applications.

IV-A) Common-Base Preamplifier

Fig. 22 shows the schematic and Fig. 23 the layout ofa fast 2-stage common-base current-sensitive preamplifier.The CE-3/CB-4 cascade superceeds this for our TEC work (thePole/Zero correction required between the two common-basestages is a nuisance, especially when they are separatedy 50 cra. of twisted pair). The circuit is nonetheless a

classic, and is in use by the Hofer group at SIN.

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IV-B) Slow Charge-Sensitive Preamplifier

Fig. 24 shows the schematic and Fig.25 the PC layoutof a slow (rise-time = 40 nsecs) charge-sensitive amplifier(gain = 6600 e /mV). This amplifier is used in our tests tomonitor gas gain, thus is quite important. One must bewarehowever; the layouts already prepared at ETH are actuallybackwards, hence the FET connections are convoluted.

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IV-C) Fast Charge-Sensitive Preamplifier

Fig. 26 shows the schematic and Fig. 27 the layout of afaster (rise-time = 8 nsec.) charge-sensitive amplifier(gain = 13000 e /mV). This circuit is not currently in use,but is nonetheless quite handy. One must again watch the FETconnections (as above), since our prints at ETH seem to bereversed.....

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