Thin Solid Films 520 (2012) 3009–3012

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Complementary ring oscillator fabricated via direct laser-exposure andsolution-processing of a single-layer organic film

Christian Larsen, Jia Wang, Ludvig Edman ⁎The Organic Photonics and Electronics Group, Department of Physics, Umeå University, SE-901 87 Umeå, Sweden

⁎ Corresponding author. Tel.: +46 90 7865732; fax:E-mail address: ludvig.edman@physics.umu.se (L. Ed

0040-6090/$ – see front matter © 2011 Elsevier B.V. Alldoi:10.1016/j.tsf.2011.12.048

a b s t r a c t

a r t i c l e i n f o

Article history:Received 10 October 2011Received in revised form 14 December 2011Accepted 16 December 2011Available online 22 December 2011

Keywords:CMOSRing-oscillatorInverterOrganic thin-film transistorPatterningEnergy delay productP3HTPCBM

A complementary ring oscillator is realized by exposing a solution-processed single-layer organic film to area-selective laser-light exposure and solution development. The pristine film comprises a blend of two organicsemiconductors: p-type poly(3-hexylthiophene-2,5-diyl) (P3HT) and n-type [6,6]-phenyl C61 butyric acidmeth-yl ester (PCBM). The exposure transforms PCBM into an insoluble form, and the subsequent developmentselectively removes the non-exposed PCBMwhile leaving exposed PCBM and P3HT intact. The 5-step ring oscil-lator exhibits a frequency of 10 mHz, a power delay product of 2.0 μJ, and an energy delay product of 22 μJs.Opportunities for performance improvements of the scalable fabrication technique are highlighted in an accom-panying analysis.

© 2011 Elsevier B.V. All rights reserved.

1. Introduction

Organic thin-film transistors (OTFTs) promise to contribute to therealization of paradigm-shifting electronic applications, such asconformable and ultra-thin emissive displays [1, 2], low-cost radiofrequency identification tags [3], and electronic paper [4], due to attrac-tive properties such as low-temperature processability from solutionand mechanical flexibility. In order to qualify for these applications, itis important that the OTFTs can be combined into circuits, which simul-taneously fulfill the requirements of low power consumption, highperformance, and low-cost fabrication. From a power-consumptionand performance perspective, it is often desirable to utilize the comple-mentary metal oxide semiconductor (CMOS) technology, in which theelectronic circuit comprises a combination of p-type and n-type transis-tors [5]. However, a challenge with the CMOS technology from an OTFTpoint-of-view is that it is difficult to deposit different types of organicsemiconductors in close proximity over a large area in a reliable,scalable and low-cost manner [6]. A number of methods have beenused to approach this problem including vacuum deposition throughshadowmasks [7–13], photolithography [14],micro-injector deposition[15] and inkjet printing [16]. While producing high performing OTFTsthese methods are not ideal from the combined perspective ofreliability, scalability and potential for low-cost production. Here, we

+46 90 7866673.man).

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demonstrate that it is possible to fabricate a relatively complex circuit,a CMOS ring oscillator, with a notably robust, scalable and straightfor-ward method comprising solely solution processing and laser-lightexposure. We also present an analysis of the static and dynamicresponse of the constituent CMOS inverters, and point out a viablepath toward further improvements in oscillator performance.

2. Material and methods

[6,6]-phenyl C61 butyric acid methyl ester (PCBM; 99.5%, Solenneb.v.) and poly(3-hexylthiophene-2,5-diyl) (P3HT; Sigma-Aldrich,regioregular, electronic grade, 99.995% trace metal basis, Mn=30,000-60,000) were selected as the n-type and p-type semiconductors,respectively, and were separately dissolved in chlorobenzene (Sigma-Aldrich, anhydrous) in a 20 g/l concentration. A blend solution compris-ing PCBM and P3HT in a 5:1 mass ratio was spin-coated on a SiO2 gatedielectric (200 nm thickness) positioned on a p-Si substrate acting asthe gate electrode. The resulting active-material film was annealed ona hot plate at 100 °C for 3 min,where after an array of source-drain elec-trodes (Au, 30 nm thickness) were deposited on top of the film by ther-mal evaporation through a shadow mask to define a gate length andgate width of LG=50 μm and W=1.7 mm, respectively, for eachOTFT. At this point, the OTFTs were primarily n-type, since n-typePCBM is the majority component in the pristine active material.

For the selective conversion step, a shadow mask was utilized sothat the active material in OTFTs designed to be n-type was simulta-neously exposed to green laser light (λ=532 nm, p=60mW/cm2)

3010 C. Larsen et al. / Thin Solid Films 520 (2012) 3009–3012

for 30 min, while the designed p-type OTFTs were left non-exposed.Following the exposure, the entire OTFT array was developed byimmersion into a chloroform:acetone (1:7 volume ratio) developersolution for 30 s, and thereafter dried on a hot-plate at 100 °C for3 min. The tuned developer solution selectively removes the non-exposed PCBM from the blend film, while leaving the exposed (anddimerized [17]) PCBM and the P3HT intact. This has the importantand attractive consequence that the exposed OTFTs remain n-type,while the non-exposed OTFTs transform into being p-type, as onlyp-type P3HT remains in the active channel of the latter [18]. The remov-al of the majority component in the non-exposed transistors did notpractically influence the mechanical stability of the remaining film.The complementary transistors can be connected into an inverter cir-cuit, and a photograph of two such inverter devices is shown in Fig. 1,with the exposed regions being blue and the non-exposed regionsbeing orange-brown in color. OTFT and circuit measurements wereperformed with a Keithley SCS-4200 system, and capacitances weremeasured using a frequency response analyzer (Eco Chemie AutolabPGSTAT302/FRA2). The OTFT fabrication was performed in N2-filledgloveboxes ([O2]b10 ppm, [H2O]b1 ppm), and the measurementswere executed within a custom-made Faraday cage positioned in thesame glove box system.

3. Results

The non-exposed and developed transistors show p-type behavior,as only p-type P3HT remains in the active material, and a set of typicaloutput data is presented in Fig. 2(a). The exposed and developed tran-sistors are in contrast primarily n-type (see Fig. 2b), as dimerizedPCBMdominates in the active channel; but aminor ambipolar charactercan be observed as a super-linearly increasing drain current with drainvoltage at low gate voltages. The averagemobility and threshold voltagefor the herein studied transistors were calculated to beμp=1.3(±0.4)×10−4 cm2/Vs and VT,p=−14.8(±2.5) V, respectively,for the p-type transistors and μn=1.7(±0.8)×10−4 cm2/Vs andVT,n=19.4(±1.7) V, respectively, for the n-type transistors.

A p-type and an n-type transistor can be connected into a CMOSinverter circuit (see inset in Fig. 2c), and the operation of such a digitalinverter is depicted in Fig. 2(c) and (d). The static measurement inFig. 2(c) reveals a well-behaved inverter operation with a high gain of11(±1), and with a switching threshold at an input voltage ofVin≈30 V (see solid line). The observed peak in the supply current

1 mm

Fig. 1. Photograph of two inverter devices. The blue rectangular regions encompassingthe lower transistor channels comprise a blend of exposed PCBM and P3HT, while theremaining orange-brown regions consist solely of (non-exposed) P3HT.

(IDD, dotted line) at the switching point is expected based on that boththe p- and the n-type transistors are (weakly) conducting at this in-stant. A low IDD in the low-output state was also anticipated and ob-served, in consideration of that the p-type transistor is then biased inits sub-threshold region. The higher IDD in the high-output state is at-tributed to the slight ambipolar nature of the n-type transistor, and itis feasible that this leakage current can be further suppressed by, e.g.,optimization of the P3HT/PCBM blend ratio in the active-material film.

If an odd number of inverters is connected in series, with the outputof the last inverter connected to the input of the first, it is possible to re-alize a ring oscillator; a schematic of a 5-step ring oscillator circuit isshown in Fig. 3(a). Five discrete inverters were connected to completea 5-stage ring oscillator circuit and a representative snapshot of thetemporal behavior of the output voltage (top) and the supply current(bottom) for such a ring oscillator circuit while driven at VDD=50 V ispresented in Fig. 3(b). The frequency of operation is 10 mHz, and thesupply current oscillates around an average value of iDD≈15 nA.

The ring oscillator data also allows a precise calculation of theperformance and integration of the constituent inverter stages. Aseach inverter stage drives the next inverter stage in a sequential fashionwithin the ring-oscillator chain [19–22], the average inverter propaga-tion delay time (tp) can be calculated by dividing the measured oscilla-tion periodwith the number of inverter stages (N)multiplied by a factorof two. Moreover, the average power consumption of each inverterstage (Pav) can be determined by integrating the ring oscillator supplycurrent over a time period representing an integer number of oscilla-tions (T), multiplying with the supply voltage, and dividing with NT:

Pav ¼VDD

NT∫T0idd tð Þdt ð1Þ

tp and Pav, and consequently the ring oscillator performance, werefound to vary relatively strongly with VDD, and this dependence ispresented in Fig. 3(c). Furthermore, the value for Pav can be multipliedwith tp and tp

2 for the calculation of the power delay product (PDP)and the energy delay product (EDP), respectively [23]. The PDP repre-sents the average energy consumed per switching event, while theEDP combines the energy consumption with the switching perfor-mance, and is as such a good metric for comparing different transistortechnologies. The dependence of EDP and PDP on the supply voltage isshown in Fig. 3(d), and we find, e.g., that PDP=2.0 μJ and EDP=22 μJsat VDD=50 V.

4. Discussion

Although the main aim of this study is to demonstrate that it ispossible to realize advanced CMOS circuits by a straightforward andscalable approach comprising solution processing and direct laserlight exposure, we wish to finish off by pointing out opportunities forfuture improvements in performance of the technique. The frequencyof the ring oscillator can be estimated (considering the well-established equation for the gate delay [24]) as:

f ¼ IDSat2NCLVDD

ð2Þ

where IDSat is the average saturation current at |VGS|=|VDS|=VDD and CLis the total load capacitance per inverter. The latter can be separated intotwo parts, being the intrinsic channel capacitances (Ci) and a parasiticcapacitance (CP). The parasitic capacitance (per inverter stage) inturn has two distinguishable parts: the gate-source capacitances forthe p- and n-type transistors (Cgs,p and Cgs,n) and the common gate-drain capacitance (Cgd). By utilizing the Miller approximation, andreplacing the gate-drain capacitance positioned between two dynamicnodes (here, input and output) with a capacitance positioned betweena dynamic and a static node (here, input and ground) multiplied by afactor 2, the three constituent parasitic capacitances can be considered

(c)Idd

VoutVin

VDD

n

p

(d)

2 V/s

(a) (b)

2 V/s

0 25 50

0

50

0

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0 20 40 60

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−50 −25 0

−60

−50

−40

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t [s]

Vou

t [V

]

I DS [n

A]

VDS [V]

I DS [n

A]

I DD [n

A]

Vou

t [V

]

Vin

[V]

VDS [V]

Vin [V]

Fig. 2. Typical output characteristics of (a) a non-exposed and developed p-type transistor and (b) an exposed and developed n-type transistor, as characterized with a sweep rateof 2 V/s. The gate voltage was increased in steps of 10 V, starting at 0 V and ending at −50 V (a, lower trace) and +50 V (b, upper trace). (c) Static CMOS inverter characteristicsshowing the inverter output voltage (solid line) and the supply current (dotted line) as a function of input voltage at a slow scan rate of 1 V/s. (d) Transient CMOS inverter datashowing the step-function input voltage (dashed line) and the corresponding output voltage (solid line). The supply voltage was VDD=50 V in (c) and VDD=44 V in (d).

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connected in parallel, so that the total parasitic capacitance is given byCP=Cgs,n+Cgs,p+2Cgd. A measurement of the separate parasitic capac-itance contributions results in: CP=1.44(±0.15) nF, which should becompared with the, in this case, negligible intrinsic channel capaci-tance: Ci=14.7 pF. Thus, it is evident that the oscillator frequency canbe improved by orders ofmagnitude by simplyminimizing the parasitic

(c)

(a)

idd

vout

VDD

44 46 48

10

20

30

40

50

50

0

0.05

0.1

0.15

0.2

t p [s

]

Pav

[µW

]

VDD [V]

Fig. 3. (a) Circuit schematic of the 5-stage CMOS ring oscillator, and (b) the temporal evoluti(c) The propagation delay time (circle, solid line) and the average power consumption (squsolid line) and the energy delay product (diamond, dashed line) per inverter stage as a fun

overlap between the gate and the source/drain electrodeswithin the os-cillator circuit, e.g. by using electrodes patterned by photolithography.

Improvements in the dynamic performance can also be attained byan increase in IDSat and by a lowering of CL via a decrease of Ci(see Eq. (2)). The former can be effectuated by increasing the effectivemobility of the constituent semiconductors via optimization and/or

(d)

(b)

0 5 10 15

0

100

44 46 48 50

0

1

2

3

0

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i dd [n

A]

t [min]

PD

P [µ

J]

ED

P [µ

Js]

VDD [V]

0

50

Vou

t [V

]

on of the output voltage (top) and the supply current (bottom) measured at VDD=50 V.are, dashed line) as a function of supply voltage. (d) The power delay product (triangle,ction of supply voltage.

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improvements of the blend stoichiometry [25], the morphology, thefabrication procedure [26–28], and the dielectric interface [29], as wellas by gate length scaling. A decrease of the gate length will also resultin a decrease of the intrinsic load capacitance; and in this context it is in-teresting to note that we recently have shown that PCBM can be pat-terned by UV-light, and that it is possible to attain electronically activePCBM patterns with a smallest demonstrated feature size of 1 μm [30].

For a functional CMOS ring oscillator, it is further reasonable to as-sume that effectively all power consumption is due to capacitivepower dissipation originating from charging and discharging of theload capacitances. The energy needed to fully charge the load capacitor(in one inverter stage) isCLVDD2 , andwhen the inverter is oscillating at itsmaximum rate this energy will be consumed every 2× tp, which resultsin an average power consumption of Pav=CLVDD

2 /(2tp) [23]. To reducethe power consumption, a decrease of the supply voltage is the mostviable path toward improvement. This can be achieved by gate lengthscaling, increasing the intrinsic channel capacitance via a reduction ofthe dielectric thickness and by utilizing high dielectric constant (high-κ) insulatormaterials, e.g. Al2O3, HfO2, allowing the oscillator to operatewith lower supply voltage. For higher level circuit designs it is also nec-essary to take into account the static power consumption [4], as theslightly ambipolar n-type transistor (see Fig. 2b) will contribute anon-desired high off-current at logic-high output state (see Fig. 2c).The static power consumption of such designs can however be mini-mized by favoring the logic-low output state of the utilized logic.

5. Conclusions

In summary, we have applied a photolithographic technique on asingle-layer organic blend film for the realization of a CMOS oscillationcircuit, which when driven at a supply voltage of 50 V and an averagesupply current of 15 nA exhibits an oscillation frequency of 10 mHz, apower delay product of 2.0 μJ, and an energy delay product of 22 μJs. Itis notable that the patterning of the organic blend film was effectuatedwithout the use of a sacrificial photoresist material.

Acknowledgment

The authors acknowledge Kempestiftelserna, Carl Tryggers Stiftelse,and the Swedish Research Council (Vetenskapsrådet) for financialsupport. L.E. is a “Royal Swedish Academy of Sciences Research Fellow”

supported by a grant from the Knut and Alice Wallenberg Foundation.

Professor Robert Forchheimer at Linköping University is gratefullyacknowledged for stimulating discussions and valuable input.

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