complex instruction set computer

• complex instruction set computer

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Macintosh - Decline

1 Apple concluded that Intel's CISC (Complex Instruction Set Computer) architecture ultimately would not be

able to compete against RISC (Reduced Instruction Set Computer)

processors


DEC Alpha

1 Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by

Digital Equipment Corporation (DEC), designed to replace the 32-bit VAX complex instruction set computer

(CISC) ISA and its implementations


Instruction (computer science) - Classification of instruction sets

1 A complex instruction set computer (CISC) has many specialized

instructions, which may only be rarely used in practical programs


Instruction (computer science) - Design

1 The first was the CISC (Complex Instruction Set Computer), which had many different

instructions


Instruction (computer science) - Code density

1 (therefore retroactively named Complex Instruction Set Computers, Complex instruction set computer|

CISC)


X86 - Basic properties of the architecture

1 The x86 architecture is a variable instruction length, primarily Complex instruction set computer|CISC design

with emphasis on backward compatibility


Philips CD-i - Technical specifications

1 *16/32-bit Philips 68070|68070 Complex instruction set computer|CISC Chip (Motorola 68000|68000

core)


History of video game consoles (sixth generation) - Bits and system power

1 The Microsoft Xbox (console)|Xbox uses a 32-bit (general purpose)

Complex instruction set computer|CISC x86 architecture CPU, with an instruction set equal to that of the Coppermine core Mobile Celeron, though it has less cache memory (128kB) than the PC equivalent


Macintosh computer - Decline

1 Apple concluded that Intel's CISC (Complex Instruction Set Computer) architecture ultimately would not be able to compete against RISC

(Reduced Instruction Set Computer) processors.[http://web.archive.org/web/20071208100556/http://macwo

rld.co.uk/news/index.cfm?newsid=7045] While the Motorola 68040 offered the same features as the Intel 80486 and could on a clock-for-

clock basis significantly outperform the Intel chip, the 486 had the ability to be clocked significantly faster without suffering from

overheating problems, especially the clock-doubled i486DX2 which ran the CPU logic at twice the external bus speed, giving such equipped IBM compatible systems a significant performance lead over their

Macintosh equivalents.[http://www.bbs.ingedigit.com.ve/TechInfo/68040.Microproc

essor.html 68040 Microprocessor] Apple's product design and engineering didn't help matters as they restricted the use of the '040 to their expensive Quadras for a time while the 486 was readily available to OEMs as well as enthusiasts who put together their own machines


Microcode - The reason for microprogramming

1 The approach of increasingly complex microcode-implemented instruction sets was later called

Complex instruction set computer|CISC


Microcode - Microcode versus VLIW and RISC

1 A CPU that uses microcode generally takes several clock cycles to execute a single

instruction, one clock cycle for each step in the microprogram for that instruction. Some

Complex instruction set computer|CISC processors include instructions that can take a very long time to execute. Such variations interfere with both interrupt

latency (engineering)|latency and, what is far more important in modern systems,

pipelining.https://store.theartofservice.com/the-complex-instruction-set-computer-toolkit.html

Workstation - Decline of workstations

1 * High-performance Central processing unit|CPUs: while Reduced instruction set

computing|RISC in its early days (early 1980s) offered roughly an order-of-

magnitude performance improvement over Complex instruction set computer|CISC

processors of comparable cost, one particular family of CISC processors, Intel's x86, always had the edge in market share

and the economies of scale that this implied


Reduced instruction set computing - Hardware utilization

1 The attitude at the time was that hardware design was more mature than compiler

design so this was in itself also a reason to implement parts of the functionality in hardware or microcode rather than in a

memory constrained compiler (or its generated code) alone. After the advent of RISC, this philosophy became retroactively

known as Complex instruction set computer|complex instruction set

computing, or CISC.https://store.theartofservice.com/the-complex-instruction-set-computer-toolkit.html

Reduced instruction set computing - Hardware utilization

1 RISC was developed as an alternative to what is now known as Complex instruction set computer|CISC. Over the years, other

strategies have been implemented as alternatives to RISC and CISC. Some

examples are VLIW, Minimal instruction set computer|MISC, One instruction set computer|OISC, massively parallel

(computing)|massive parallel processing, systolic array, reconfigurable computing, and

dataflow architecture.


No instruction set computing - History

1 In the past, microprocessor design technology evolved from complex instruction set computer (CISC) to reduced instruction set computer

(RISC)


Complex instruction set computing

1 A 'complex instruction set computer' ('CISC' ) is a computer

where single instruction set architecture|instructions can execute several low-level operations (such as

a load from Memory (computers)|memory, an arithmetic operator (programming)|operation, and a

memory (computers)|memory store) and/or are capable of multi-step operations or addressing modes

within single instructions


48-bit - Addressing

1 The IBM System/38 and the AS/400, in its Complex instruction set

computer|CISC variants, are 48-bit addressing systems. The address size used in logical block addressing was

increased to 48 bits with the introduction of AT Attachment#ATA standards versions, transfer rates,

and features|ATA-6.


Bonnell (microarchitecture)

1 Like many other x86 microprocessors, it translates x86

instructions (Complex instruction set computer|CISC instructions) into

simpler internal operations (sometimes referred to as micro-ops, effectively Reduced instruction set computer|RISC style instructions)

prior to execution


QEMU - Hardware-assisted emulation

1 The MIPS architecture|MIPS-compatible Loongson-3 processor adds 200 new instructions to help QEMU translate x86 instructions; those

new instructions lower the overhead of executing x86/Complex instruction set

computer|CISC-style instructions in the MIPS pipeline. With additional improvements in QEMU by the Chinese Academy of Sciences, Loongson-3 achieves an average of 70% the performance of executing native binaries while running x86

binaries from nine benchmarks.


ZEnterprise 196 - zEnterprise EC12

1 The 'zEnterprise EC12' (zEC12) is based on the IBM zEC12

(microprocessor)|zEC12 chip, a 5.5GHz hexa-core Out-of-order execution|out-of-order Complex

instruction set computer|CISC-based z/Architecture|zArchitecture

processor


ZEnterprise 196 - zEnterprise 114

1 The 'zEnterprise 114' (z114) is powered by up to 14 microprocessors

running at 3.8GHz Out-of-order execution|out-of-order Complex

instruction set computer|CISC-based z/Architecture|zArchitecture

processor


zEnterprise 196

1 The 'zEnterprise 196's' microprocessor is the IBM z196

(microprocessor)|z196 chip, a 5.2GHz quad-core Out-of-order execution|

out-of-order Complex instruction set computer|CISC-based z/Architecture

processor


ISeries - Instruction set

1 This is how application objects compiled on one processor family

(e.g., the original Complex Instruction Set Computer|CISC

AS/400 48-bit processors) could be moved to a new processor (e.g.,

PowerPC 64-bit) without re-compilation


ISeries - Instruction set

1 The IBM System i's instruction set defines all pointers as 48-bit. This was the original

design feature of the System/38 (S/38) in the mid 1970s planning for future use of faster

processors, memory and an expanded address space. The original AS/400 Complex instruction set computer|CISC models used the same 48-bit address space as the S/38. The address space was expanded in 1995 when the RISC PowerPC RS64 64-bit CPU

processor replaced the 48-bit CISC processor.


Itanium - High-end server market

1 When first released in 2001, Itanium's performance, compared to better-established Reduced Instruction Set Computer|RISC and

Complex Instruction Set Computer|CISC processors, was disappointing. Emulation to run existing x86 applications and operating

systems was particularly poor, with one benchmark in 2001 reporting that it was

equivalent at best to a 100Hertz|MHz Pentium in this mode (1.1Hertz|GHz Pentiums

were on the market at that time).


PA-RISC - History

1 In the late 1980s HP was building four series of computers, all based on

Complex instruction set computer|CISC CPUs


M68k

1 The Motorola '680x0'/'m68000'/'68000' is a family

of 32-bit Complex instruction set computer|CISC microprocessors


Processor architecture - Instruction set choice

1 Some labels used to denote classes of CPU architectures are not

particularly descriptive, especially so the CISC label; many early designs

retroactively denoted Complex instruction set computer|CISC are in

fact significantly simpler than modern RISC processors (in several

respects).


Binary translation - Dynamic binary translation

1 * Digital Equipment Corporation|DEC achieved similar success with its

translation tools to help users migrate from the Complex instruction set computer|CISC VAX architecture

to the DEC Alpha|Alpha RISC architecture.


HP3000 - Classic and PA-RISC 3000 hardware

1 The earlier Classic machines were based on a custom Complex instruction set computer|

CISC processor. From about 1988 onward, HP 3000s using PA-RISC processors began

shipping in volume. By 1995 these PA-RISC systems effectively displaced the older family of machines from use. As with all technology shifts, there remained a significant residue of

older machines in service. Even today, original Classic 3000s work in production in a

few locations.


VAX

1 A 32-bit complex instruction set computer based on DEC's earlier

PDP-11, VAX ('Virtual Address eXtension'), was designed to extend

or replace DEC's various Programmed Data Processor|PDP

ISAs. The VAX architecture's primary features were virtual addressing (for

example Paging|demand paged virtual memory) and its orthogonal

instruction set.https://store.theartofservice.com/the-complex-instruction-set-computer-toolkit.html

Clipper architecture

1 The Clipper architecture used a simplified instruction set compared to earlier Complex instruction set computer|CISC architectures,

but it did incorporate some more complicated instructions than were present in other contemporary RISC processors. These

instructions were implemented in a so-called Macro Instruction Read-only memory|ROM

within the Clipper CPU. This scheme allowed the Clipper to have somewhat higher code

density than other RISC CPUs.


6502 microprocessor - Indirect addressing

1 Furthermore, orthogonal instruction set|orthogonality is equally often

associated with Complex instruction set computer|CISC


Apple–Intel transition - Hardware-oriented

1 Proponents have responded by saying that the x86 architecture has

evolved greatly since the original 8086 was introduced, and that CPUs in general have combined RISC and Complex instruction set computer|CISC philosophies in their internal designs for some time, making the

distinction obsolete


AIM alliance

1 It was thought that the Complex instruction set computer|CISC processors from Intel were an

evolutionary dead-end in microprocessor design, and that

since RISC was the future, the next few years were a period of great

opportunity


Power Architecture - History

1 In the early 1990s IBM sought to replace the Complex instruction set

computer|CISC based AS/400 minicomputers with a RISC

architecture


68000

1 The 'Motorola 68000' ('sixty-eight-thousand'; also called the 'Motorola

68k', sixty-eight-k) is a 16/32-bit Complex instruction set computer|CISC microprocessor core designed

and marketed by Motorola Semiconductor Products Sector (now

Freescale Semiconductor)


System call - Typical implementations

1 For many RISC processors this is the only technique provided, but

Complex instruction set computer|CISC architectures such as x86 support additional techniques


Disassembly

1 Disassembly is not an exact science: on Complex instruction set computer|CISC

platforms with variable-width instructions, or in the presence of self-modifying code, it

is possible for a single program to have two or more reasonable disassemblies. Determining which instructions would

actually be encountered during a run of the program Reduction (complexity)|reduces to

the proven-unsolvable halting problem.


CPU design - Details

1 Key CPU architectural innovations include index register, CPU cache|cache, virtual memory, instruction pipelining, superscalar, Complex instruction set computer|CISC,

Reduced instruction set computer|RISC, virtual machine, emulators, microprogram, and Stack (data

structure)|stack.


Open64 - The infrastructure

1 and code generator (CG). Despite being initially written for a single computer

architecture, Open64 has proven that it can generate efficient code for Complex instruction set computer|CISC, Reduced instruction set computer|RISC, and Very long instruction word|VLIW architectures,

including MIPS architecture|MIPS, x86, Itanium|IA-64, ARM architecture|ARM,

and others.


Multi-Programming Executive

1 It runs the HP 3000 family of computers, which originally used HP

custom 16 bit stack architecture Complex instruction set computer|CISC Central processing unit|CPUs and were later migrated to PA-RISC

where the operating system was called 'MPE/XL'


Address mode - Caveats

1 For example, some complex instruction set computer (CISC)

computer architectures, such as the Digital Equipment Corporation|Digital

Equipment Corporation (DEC) VAX, treat registers and value (computer

science)|literal or immediate constants as just another addressing

mode


Very long instruction word - History

1 This was partly inspired by the difficulty Fisher observed at Yale of

compiling for architectures like Floating Point Systems' FPS164,

which had a complex instruction set architecture (Complex instruction set

computer|CISC) that separated instruction initiation from the

instructions that saved the result, requiring very complicated

scheduling algorithmshttps://store.theartofservice.com/the-complex-instruction-set-computer-toolkit.html

VAX

1 A 32-bit complex instruction set computer based on DEC's earlier

PDP-11, VAX (virtual address extension) was designed to extend or replace DEC's various Programmed Data Processor|PDP ISAs. The VAX

architecture's primary features were virtual addressing (for example Paging|demand paged virtual memory) and its orthogonal

instruction set.https://store.theartofservice.com/the-complex-instruction-set-computer-toolkit.html

Visual Instruction Set - Differences vs x86

1 This design is very different from comparable extensions on Complex

instruction set computer|CISC processors, such as MMX (instruction

set)|MMX, Streaming SIMD Extensions|SSE, SSE2, SSE3, SSE4,

3DNow!.


CDC 6600 - Description

1 A typical CPU of the era had a Complex instruction set computer|

complex instruction set, which included instructions to handle all the normal housekeeping tasks such as memory access and input/output


GEC 4000 series - Instruction set

1 The 4000 series has a Complex Instruction Set Computer|CISC

instruction set. It has 8-bit bytes, Endianness|big-endian, byte-Memory address|addressable memory, two's complement arithmetic, IBM Floating Point Architecture|base-16 excess-64 floating point format (same as IBM

System/360).


MIPS instruction set - Licensable architecture

1 This proved fairly successful due to the simplicity of the core, which

allowed it to be used in a number of applications that would have

formerly used much less capable Complex instruction set computer|CISC designs of similar gate count

and price—the two are strongly related; the price of a CPU is

generally related to the number of gates and the number of external

pins


Micro-operation - Overview

1 More recently, μops have also been employed in a different way in order to let modern Complex

instruction set computer|CISC processors more easily handle asynchronous parallel and speculative

execution: As with traditional microcode, one or more table lookups (or equivalent) is done to locate the

appropriate μop-sequence based on the encoding and semantics of the machine instruction (the decoding or

translation step), however, instead of having rigid μop-sequences controlling the CPU directly from a microcode-Read-only memory|ROM, μops are here dynamically issued, that is, buffered in rather long

sequences before being executed.


NS320xx - Architecture

1 The instruction set was very much in the Complex instruction set computer|CISC model,

with 2-operand instructions, memory-to-memory operations, flexible addressing modes, and

variable-length byte-aligned instruction encoding. Addressing modes could involve up

to two displacements and two memory indirections per operand as well as scaled indexing, making the longest conceivable instruction 23 bytes. The actual number of instructions was much lower than that of

contemporary RISC processors.


PA-RISC - History

1 In the late 1980s, HP was building four series of computers, all based on

Complex instruction set computer|CISC CPUs


Bell Northern Research - The Digital Switch

1 BNR's products were architecturally based on Complex Instruction Set Computer|Complex Instruction Set

(Complex Instruction Set Computer|CISC) architectures prevalent in the 1970s, and on a series of underlying

technologies


Instruction set architecture - Classification of instruction sets

1 A complex instruction set computer (CISC) has many specialized

instructions, some of which may only be rarely used in practical programs


IBM Future Systems project - Processor

1 Another principle was the use of very high-level complex instructions to be implemented

in microcode. As an example, one of the instructions, CreateEncapsulatedModule, was a complete linkage editor. Other instructions were designed to support the internal data structures and operations of programming languages such as FORTRAN, COBOL, and PL/I. In effect, FS was designed to be the

ultimate complex instruction set computer (Complex instruction set computer|CISC).


Dis virtual machine

1 In computing, the 'Dis virtual machine' provides the execution

environment for application code in the Inferno (operating system)|

Inferno operating-system. Its design, based on a register machine, closely

models complex instruction set computer|CISC-like architectures.


IBM zEnterprise System - zEnterprise 196

1 The 'zEnterprise 196's' microprocessor is the IBM z196|z196

chip, a 5.2GHz quad-core Out-of-order execution|out-of-order Complex instruction set computer|CISC-based

z/Architecture processor


Digital Equipment - 32-bit MIPS and 64-bit Alpha systems

1 This was a 64-bit RISC architecture (as opposed to the 32-bit Complex

instruction set computer|CISC architecture used in the VAX) and

one of the first pure (not an extension of an earlier 32-bit

architecture) 64-bit microprocessor architectures and implementations


Alpha processor

1 'Alpha', originally known as 'Alpha AXP', is a 64-bit reduced instruction set computing (RISC)

instruction set developed by Digital Equipment Corporation (DEC),

designed to replace their 32-bit VAX complex instruction set computer

(CISC) instruction set


MC68000

1 The 'Motorola 68000' ('sixty-eight-thousand'; also called the 'm68k' or

'Motorola 68k', sixty-eight-k) is a 16/32-bit Complex instruction set

computer|CISC microprocessor core designed and marketed by Motorola Semiconductor Products Sector (now

Freescale Semiconductor)


Megahertz myth - Background

1 The x86 Complex instruction set computer|CISC based CPU

architecture which Intel introduced in 1978 was used as the standard for

the DOS based IBM PC, and developments of it still continue to dominate the Microsoft Windows

market


Apple Mac - Transition to PowerPC

1 Apple concluded that Intel's CISC (Complex Instruction Set Computer) architecture ultimately would not be

able to compete against RISC (Reduced Instruction Set Computer)

processors


Compiler optimization - Factors affecting optimization

1 *RISC vs Complex instruction set computer|CISC: CISC instruction sets

often have variable instruction lengths, often have a larger number of possible instructions that can be

used, and each instruction could take differing amounts of time


Compiler optimization - Code generator optimizations

1 ;Instruction selection: Most architectures, particularly Complex

instruction set computer|CISC architectures and those with many

addressing modes, offer several different ways of performing a

particular operation, using entirely different sequences of instructions


Toshiba TLCS

1 The 'Toshiba TLCS' series is a family of Complex instruction set computer|

CISC and Reduced instruction set computer|RISC microcontrollers from

Toshiba.


Freescale 68HC11

1 It is a Complex instruction set computer|CISC microcontroller


COP8

1 The 'COP8' microcontroller from National Semiconductor is an 8 bit Complex instruction set computer|CISC core microcontroller, whose

main features are:


R8C

1 The Renesas '[http://www.renesas.com/products/mpumcu/r8c/index.jsp R8C]' is a 16-bit microcontroller that

was developed as a smaller and cheaper version of the Renesas M16C . It retains the M16C's 16-

bit Complex instruction set computer|CISC architecture and instruction set, but trades size for speed by cutting the internal data bus from 16 bits to 8 bits. It is available in a number of

different versions with varying amounts of flash memory and Static random access memory|

SRAM.


CDC Cyber - Cyber 200 series

1 It is worth noting that the instruction set would be considered V-Complex instruction set computer|CISC (very

complex instruction set) among modern processors


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