content addressable memories (cams)

7/27/2019 Content Addressable Memories (CAMs)

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Content Addressable

Memories (CAMs)

(Associative Memories)


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Content Addressable Memories

(CAMs)

CAM high-level block diagram


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Match operations

U "Mask" registru je "1" na bitskim pozicijama na kojima se proverava slaganje sadraja

Navedena je samo adresa

najveeg prioriteta


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Asociativna elija realizovana MOS tranzistorima

(SLII - Selektorska linija i Ispitni izlaz)

Operacija IL SLII /Z Z komentar

WRITE 0 0 V V-

0

WRITE 1 0 V 0 V-

MASK WRITE 0 V V- V-READ 0 0 V V

-V

-kroz Z tece struja 300A

READ 1 0 V V-

V-

kroz /Z tece struja 300A

ISPITIVANJE 0 V 0-

V-

0 neslaganje: kroz SLII tece 100A

ISPITIVANJE 1 V 0-

0 V-

neslaganje: kroz SLII tece 100A

Mask ISPITIV. V 0 0 0

NEAKTIVNO 0 0 X X

V- : slaba logika jedinica (linija preko otpornika R vezana na +V)

0- : slaba logika nula (linija preko otpornika R vezana na potencijal mase)


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/Z Z

SLII

IL

GND

+V

Interrogate

RD, WR, Standby

GND

+V

InterrogateRD, WR

InterrogateOut - Flag

GND

+V

Interrogate

RD, WR

Interrogate

Out - Flag

GND

+V

Interrogate

RD, WR

InterrogateOut - Flag

- +

+V+VDataOUT

DataOUT

- +

+V+VDataOUT

Iner.1Write 1

Mask Iner.

Write 0Read

Inter.0Masked WR

Standby

Write 1Read

Inter.1Masked WR

Standby

Iner.0Write 0

Mask Iner.

/Z Z

SLII

IL

/Z Z

SLII

IL

/Z Z

SLII

IL

/Z Z

SLII

IL

/Z Z

SLII

IL

Organizacija CAM-e


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Static CAM CMOS Memory Cell

CAM

Bit

Word

Bit

CAM

Bit Bit

CAM

Word

Wired-NOR Match Line

MatchM1

M2

M7M6

M4 M5M8 M9

M3

intSWord

CAM

Bit Bit

S


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CAM Structure

match

WLbit bit

word line

of data array

Read/Write Circuitry

Hit

match

match

match

match

match/write data

WL

WL

WL

WL

precharge/match


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CSE477 L25 Memory Peripheral.8 Irwin&Vijay, PSU, 2002

SecondLevel

Cache(SRAM)

Review: A Typical Memory Hierarch y

Control

Datapath

SecondaryMemory

(Disk)

On-Chip Components

RegFile

MainMemory

(DRAM)Data

Ca

che

Instr

Cache

ITLB

DT

LB

eDRAM

Speed (ns): .1s 1s 10s 100s 1,000s

Size (bytes): 100s Ks 10Ks Ms Ts

Cost: highest lowest

By taking advantage of the principle of locality:

z Present the user with as much memory as is available in thecheapest technology.

z Provide access at the speed offered by the fastest technology.


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Address issued by the data path has to be mapped (in

hardware) into a cache address

Cache block (aka line) unit of read/write information incache

Cache mapping strategiesz Direct mapped

- A word can be in only one block in the cache, so only have to compare its

tag against that blocks tagz Block set associative

- A word can be in two (or four or eight ), so have to compare its tagagainst the tags of those two (or four or eight ) cache blocks

z Fully associative

- A word can be in any block in the cache, so have to compare its tagagainst the tags of all of the blocks in the cache

Caches

which word in the cache block

which cache block in the set

tag which word in the cache block

which cache block in the set

tag



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Two-Way B lock Set Assoc iative Cache

Tag Data

=

Tag Data

=

Address issued by CPU

Hit Desired word

Set 1 Set 2


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Trans lation Lookaside Buffers (TLBs)

Small caches used to speed up address translation inprocessors with virtual memory

All addresses have to be translated before cache

access

I$ can be virtually indexed/virtually tagged


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TLB Struc ture

Address issued by CPU (page size = index bits + byte select bits)

Tag Data

=

Tag Data

=

Hit Desired word

VA Tag PA

Most TLBs are small(

content addressable memories (cams)

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