ATCA based LLRF system design review

3.12.2007 DESY

Control servers for ATCA based LLRF Control servers for ATCA based LLRF system system

Piotr Pucyk - DESY, Warsaw University of Technology

Jaroslaw Szewinski – Warsaw University of Technology

2ATCA based LLRF system design review

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Agenda

• Requirements• LLRF servers classification• ATCA computation power for LLRF servers• Servers topology in ATCA based LLRF system • Possible control systems• Development environment• Time schedule and summary

3ATCA based LLRF system design review

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Requirements

• What servers should do and should not do ?

Missing contribution from Jaroslaw Szewinski

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What control software do we need?

• Finite state machines for automation• Front-end servers for hardware

maintenance, configuration and diagnostics

• Front-end servers for controller and low level applications (execution nodes for state machines)

• Middle layer servers for high level applications

• DAQ servers or interfaces to DAQ• GUI panels, interfaces to Matlab, C,

etc.

Diagnostics maintenance

Diagnostics maintenance

End-node for FSM, controller server

End-node for FSM, controller server

High level apps, FSM

High level apps, FSM

DAQ

GUI, external apps

GUI, external apps

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Different CPUs in ATCA based LLRF systemEmbedded processors

AMC module processors

ATCA blades mainframes

Computation power

• Huge processing power

• DAQ, storage

• Post processing

• GbE

+ server class processing power

- No PCIe until now

+ serious processing power

- uses AMC slot on carrier

+ PCIe, GbE

- Low processing power

- FPGA resources

+ close to the hardware

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FPGA

Possible topology of LLRF servers

AMC CPU

IO AMC (FPGA)

FPGA embedded

CPU

ATCA Carrier board

CPU

ATCA CPU blade

CPU

Mainframe blades

CPU CPU CPU CPU

CPU CPU CPU CPU

CPU CPU CPU CPU

CPU CPU CPU CPU

PCIe

GbE

GbE

Front-end middle layerSimple FSM

Front-end middle layerSimple FSM

Front-end

Front-end

Middle layer FSMFront-end

Middle layer FSMFront-end

FSM, DAQ

FSM, DAQ

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Possible control systems

• DOOCS• EPICS• TINE• Dedicated software

Missing contribution from Jaroslaw Szewinski

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What we can reuse, what we have to develop

• Reuse

– Old communication scheme (one software interface – many hardware drivers), memory description map

– Tools for debugging and configuration

– Some existing server’s source code

• New development

– Diagnostics, maintenance interfaces (inc. IPMI, crate management)

– FSM framework for high level apps

– New communication channels

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Development environment & tools

• Linux platform• Language parsers, server wizards• Scripting languages• …

Missing contribution from Jaroslaw Szewinski

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Schedule, manpower

• Before we start:– Development environment, control system, communication

libraries, FSM framework.• Development schedule strongly depends on other tasks

– Configuration and maintenance servers (when carrier board and at least one AMC is debugged and ready for firmware implementation - 3-5.2008 ?)

– Finite state machines and procedures – starting from 1.2008 ? – Controller server, and low level applications interface servers

(parallel to controller development and low level applications)• Minimum Manpower

– 1 fulltime programmer for front-ends, 1 fulltime for FSM and high level apps, 1-2 students for help

– A lot of support from MCS group !!!

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Backup slides

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Old System Scheme

FPGA

LPT

VME

???

Memory map descriptionFile / parser

TCP Server

Hardware Channels EngineUser

Applications

Inte

rnal In

terfa

ce

Eth

OtherApplication

s

TCP/IP

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Linux on PowerPC

User applications access hardware through the driver

Kernel mode driver has access to the FPGA

FPGA has defined hardware interface

Virtex II PRO

Linuxon PPC

Hardware

FPGA II Core

Client onremote

machine

Kernelmode

Internal Interface bus

driver

Usermode

TCPserver

TC

P/IP

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DOOCS patterns

http://flash.desy.de/sites/site_vuvfel/content/e403/e1644/e1136/e1137/infoboxContent1796/tesla2006-10.pdf

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DOOCS patterns (2)