copyright © 2009 intel corporation. all rights reserved. intelligent performance april 15th, 2009...
TRANSCRIPT
Copyright © 2009 Intel Corporation. All rights reserved.
Intelligent PerformanceIntelligent Performance
April 15th, 2009April 15th, 2009Basarim 09Basarim 09National HPC ConferenceNational HPC ConferenceAnkara, TurkeyAnkara, Turkey
Stephan GillichStephan GillichDirector HPCDirector HPCEMEA Enterprise MarketingEMEA Enterprise MarketingIntel GmbHIntel GmbH
Copyright © 2009 Intel Corporation. All rights reserved.
Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice. All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to
deviate from published specifications. Current characterized errata are available on request. This document may contain information on products in the design phase of development. The information here is subject to change
without notice. Do not finalize a design with this information. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Wireless connectivity and some features may require you to purchase additional software, services or external hardware. Nehalem, Penryn, Westmere, Sandy Bridge and other code names featured are used internally within Intel to identify products that are in
development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user
Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance.
Intel, Intel Inside, Pentium, Xeon, Core and the Intel logo are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008 Intel Corporation.
Copyright © 2009 Intel Corporation. All rights reserved.
Agenda
HPC demand for performance and more
Meeting the HPC challenges: Everywhere– Today
– Tomorrow
– With HW, SW
Copyright © 2009 Intel Corporation. All rights reserved.
A look at CERN’s Computing Growth
0
20
80
100
2007 2008 2009 2010 2011 2012 2013
Source: CERN, Sverre Jarp
40
60
120 Tape Space (PetaByte)
Disk Space (PetaByte)
Computing
21,500 Cores @ 1400 SI2K per core
Lots of computing (45% CAGR), lots of data; no upper boundary!
Copyright © 2009 Intel Corporation. All rights reserved.
Insatiable Demand for Insatiable Demand for Performance, Density, and Efficiency Performance, Density, and Efficiency
Intel Power Reduction Over Time*Demand For Performance (as per Top500)
1970 1980 1990 2000 2005 20101.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1 PFlops
1 TFlops
1 GFlops100 MFlops
100 PFlops1 EFlops
1993 20171999 2005 2011 2023
1 ZFlops
2029Source: Top500.org
Massive Reduction In Massive Reduction In Energy per Transistor* Over 30+ YearsEnergy per Transistor* Over 30+ Years
Copyright © 2009 Intel Corporation. All rights reserved.
Intelligent Performance Intelligent Performance
VersatilityVersatility
Ease of useEase of use
Meeting Today’s HPC Challenges Meeting Today’s HPC Challenges
Genomics Research
Medical Imaging
Weather Prediction
Oil Exploration Design Simulation
Financial Analysis
Democratization of HPCDemocratization of HPC
Copyright © 2009 Intel Corporation. All rights reserved.
IntelArchitecture
Core
New Materials and DesignsNew Materials and Designs
Single Core EnhancementsSingle Core Enhancements
Platform EnhancementsPlatform Enhancements
Scaling technologyScaling technology
Multi to Many-Core Multi to Many-Core
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
IntelArchitecture
Core
Tri-Gate, Nanotubes Tri-Gate, Nanotubes
MMX SSE AVX MMX SSE AVX
PCIe, IMC, QPI, SOC PCIe, IMC, QPI, SOC
Scaling technologyScaling technology
Dual Quad …Dual Quad …
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Delivering Leadership Multi-Core PerformanceDelivering Leadership Multi-Core Performance
Silicon and Architecture Advances Unleash Performance
2 Y
EA
RS
2 Y
EA
RS
45nm
32nm
Shrink/DerivativeWestmere
New MicroarchitectureSandy Bridge
65nm
2 Y
EA
RS Shrink/Derivative
PentiumD· Intel® Xeon®
New MicroarchitectureIntel® Core™ Microarchitecture
Shrink/Derivative Intel® Xeon® 54XX Series
New MicroarchitectureIntel® Xeon 5500 Series
(Nehalem)
“Tick Tock” (Shrink) (Innovate) “Tick Tock”
(Shrink) (Innovate)
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel® Xeon® 5500 PlatformIntel® Xeon® 5500 Platform
Intel® 5520 Chipset
NEW!NEW! Intel® Data Center
ManagerNEW!NEW!
NEW!NEW!
Intel® Node Manager
TechnologyPCI Express* 2.0
ICH 9/10Intel® X25-ESSDs
Intel® 82599 10GbE Controller
NEW!NEW!
Platform improvements - Ready for Future 32nm Platform improvements - Ready for Future 32nm ProductsProducts
New Memory New Memory SubsystemSubsystem
Intel® Quick-Path Intel® Quick-Path InterconnectInterconnect
Intel® Intelligent Intel® Intelligent Power TechnologyPower Technology
New I/O SubsystemNew I/O Subsystem
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel® Xeon® 5500: Intel® Xeon® 5500: Intelligence Built-InIntelligence Built-In
Adapts To Your Application and User EnvironmentAdapts To Your Application and User Environment
Power Power ConstrainedConstrained
PerformancePerformanceCriticalCritical
NativeNative VirtualizedVirtualized
HighlyHighlyParallelParallel
Frequency Frequency SensitiveSensitive
Performance On-Demand
Intel® Nehalem MicroarchitectureIntel® Turbo Boost TechnologyIntel® Hyper-Threading Technology
Intel® Intelligent Power TechnologyIntegrated Power GatesAutomated Low-Power StatesIntel® Node Manager Technology
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel Turbo Boost Technology Overview
CPUs typically operate at a fixed max frequency regardless of the workload
For the most demanding workloads, the CPU operates closer to its power limitations
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010 CPU SpeedCPU Speed
MaxPower
RatedSpeed
PowerPower
OperatingPower
Core 0 Core 1
Core 3Core 2
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel Turbo Boost Technology Overview
However, most applications allow the CPU to operate below maximum power
Power headroom may also be available if cores are in idle mode
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
Core 0 Core 1
Core 3Core 2 CPU SpeedCPU Speed
MaxPower
RatedSpeed
PowerPower
OperatingPower POWER
HEADROOM
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel Turbo Boost Technology Overview
Turbo Boost speeds up the CPU to utilize any available power headroom
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
Core 0 Core 1
Core 3Core 2 CPU SpeedCPU Speed
MaxPower
RatedSpeed
PowerPower
OperatingPower
TURBOBOOST
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel Turbo Boost Technology
Turbo Boost speeds up the CPU to utilize any available power headroom
With fewer cores active and more headroom, the CPU can reach even higher frequencies
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
10001001 101010101 10001010 01010101 00001101 10101010
Core 0 Core 1
CPU SpeedCPU Speed
MaxPower
RatedSpeed
PowerPower
OperatingPower
TURBOBOOST
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intel® Turbo Boost Technology – Delivers More Intelligent Performance Automatically
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Performance SummaryIntel® Xeon® Processor 5500 Series (Nehalem-EP)
Compelling Performance Gains Across the BoardCompelling Performance Gains Across the Board
SPECfp_rate downbin data SPECint_rate downbin data
Technical Compute Servers
FiniteElementAnalysis
CompFluid
Dynamics
EnergyFloating
Point
Memory Bandwidth
Intel Xeon X5570 (2.93 GHz) vs. Intel Xeon X5482 (3.20GHz)
Weather
Source: Published/submitted/approved results March 30, 2009. See backup for additional details
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Early reality.....
“Application performance is critical to the work we carry out at the Forschungszentrum Jülich. ... Clearly, the greater application performance we can achieve the greater understanding we receive. ...Crucial for application performance in HPC is memory bandwidth and IO performance. The Intel® Xeon® processor 5500 series definitely is a leap ahead in both respects. Therefore JSC decided to base the next-generation general-purpose supercomputer JuRoPA on this processor.”Dr. Norbert Eicker, Forschungszentrum Jülich,
“Application performance is critical to the work we carry out at the Forschungszentrum Jülich. ... Clearly, the greater application performance we can achieve the greater understanding we receive. ...Crucial for application performance in HPC is memory bandwidth and IO performance. The Intel® Xeon® processor 5500 series definitely is a leap ahead in both respects. Therefore JSC decided to base the next-generation general-purpose supercomputer JuRoPA on this processor.”Dr. Norbert Eicker, Forschungszentrum Jülich,
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
Intel® Xeon 5500 Intel® Xeon 5500 Putting More Brainpower into the HPC DatacenterPutting More Brainpower into the HPC Datacenter
Source: Intel estimates and measurements as of Nov 2008. Performance comparison using SPECfp_rate _base2006. Use this slide in conjunction with backup slide.
Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations
Results have been estimated based on internal Intel analysis and are provided for informational purposes only. Any difference in system hardware or software design or configuration may affect actual performance.
4 X Performance4 X PerformanceLess Power, Same SpaceLess Power, Same Space
New Intel Xeon® 5500 Series New Intel Xeon® 5500 Series Dual-core Intel Xeon® 5160 Dual-core Intel Xeon® 5160 Processor (Woodcrest) Processor (Woodcrest)
2009: 1,000 servers 2006: 1,000 servers
Intelligent Intelligent
PerformancePerformance
020406080
100120140160180200
WCD NHM
Copyright © 2009 Intel Corporation. All rights reserved.
Intel Technology is Changing HPCIntel Technology is Changing HPCTCO, Performance, ReliabilityTCO, Performance, Reliability
ExtremePerformance
PowerEfficient
ReduceSystem Cost
IncreasedReliability
10GbE10GbESolid State DiskSolid State Disk
€ Intel IT evaluation results.
Optimize Performance for Optimize Performance for I/O Intensive Apps and I/O Intensive Apps and Boot Drive ReplacementBoot Drive Replacement
Bridging the Gap Between Bridging the Gap Between 1GbE and Infiniband®1GbE and Infiniband®
Copyright © 2009 Intel Corporation. All rights reserved.
The Challenge The Challenge Parallel ProgrammingParallel Programming
?
Irregular Patterns, Data Structures and Serial Algorithms
Increasing Cores Vector Instructions Cache and Interconnect Latency
Scale to Multi-Core Today → HardScale to Many-Core Tomorrow → Harder
VersatilityVersatility
Copyright © 2009 Intel Corporation. All rights reserved.
One Development EnvironmentOne Development Environment
Simplify Your DevelopmentSimplify Your Development
PerformancePerformanceOptimize/TuneOptimize/Tune
DevelopmentDevelopmentIntroduce ParallelismIntroduce Parallelism
ConfidenceConfidenceCorrectnessCorrectness
InsightInsightArchitectural AnalysisArchitectural Analysis
Windows*; Linux*; Mac OS*
VersatilityVersatility
Copyright © 2009 Intel Corporation. All rights reserved.
Example: Intel® Trace AnalyzerExample: Intel® Trace Analyzer
Comparison of function and
process profile data
Can show user defined blocks of
code
Show overall MPI process-to-
process communication
information
Event Timeline for each MPI
Process
Comparison of two timeline
traces
Copyright © 2009 Intel Corporation. All rights reserved.
ICR – Intel® Cluster ReadyICR – Intel® Cluster Ready
Simplify Simplify Management Management
with Intel® Cluster with Intel® Cluster CheckerCheckerSimplify Simplify
DeploymentDeploymentwith registered with registered
applicationsapplicationsSimplify Simplify ManufacturingManufacturing
with defined recipes with defined recipes and Intel® Cluster and Intel® Cluster Checker to validateChecker to validate
Simplify Simplify PurchasingPurchasingwith certified with certified
cluster cluster configurationsconfigurations
Simplifying Your Cluster Simplifying Your Cluster
What is ICR?What is ICR?A specification to help OEM’s & A specification to help OEM’s &
Integrators & iSVs and end users Integrators & iSVs and end users to manufacture, deploy and use to manufacture, deploy and use
HPC clusters HPC clusters
Ease of useEase of use
Copyright © 2009 Intel Corporation. All rights reserved.
What These Changes MeanWhat These Changes Mean Manufacturing Manufacturing
Then (90’s) Now (2009)1 Modal & Transient Analysis/Day
100’s Modal & Transient Analyses/Day enabling multivariate design optimization (previously not possible)
<1M cell Computational Fluids Model
1+B cell Computational Fluids Modelwhere refined resolution enables quantification of certain phenomena that was previously not possible
Multiple days to process digital mock up in low-quality photorealistic imagery
Real-time high-quality photorealistic visualization on a dual processor workstation enabling design review usage not previously possible
HPC Technology Changing Design CadenceAlmost Possible To Optimize On The Fly
Intelligent Intelligent
PerformancePerformance
Copyright © 2009 Intel Corporation. All rights reserved.
The Future Looks BrightThe Future Looks Bright
Breakthrough Technology Year After YearBreakthrough Technology Year After Year
45nm 45nm –Intel® Xeon 5400Intel® Xeon 5400–Intel® Xeon 5500Intel® Xeon 5500–Nehalem EXNehalem EX
FutureFutureA leap ahead in A leap ahead in
technologytechnology
22nm 22nm Continue to deliver Continue to deliver
world class world class processor processor
technologytechnology
32nm 32nm –Westmere – Westmere – more coresmore cores–Sandy Bridge – Sandy Bridge – higher integrationhigher integration
Silicon and Silicon and Software Software
Tools Tools Unleash Unleash
Performance Performance
Scaling Scaling Performance Performance
forwardforward
Copyright © 2009 Intel Corporation. All rights reserved.
Nehalem-EXNehalem-EXThe Next Step in Large Scale HPCThe Next Step in Large Scale HPC
High Performance HPCHigh Performance HPC– Up to 8 cores per socket Up to 8 cores per socket – 24MB shared last level cache24MB shared last level cache– 4 full width QPI 4 full width QPI – Integrated memory controllerIntegrated memory controller
– 4 memory channels per socket4 memory channels per socket– Up to 16 DIMMs per socketUp to 16 DIMMs per socket– Registered DDR3 memory Registered DDR3 memory
Intelligent Performance Intelligent Performance – Intel® Turbo Boost TechnologyIntel® Turbo Boost Technology– Hyper-Threading technologyHyper-Threading technology– More and lower power CPU statesMore and lower power CPU states
More Scalability, Cores, and Memory CapacityMore Scalability, Cores, and Memory Capacity
Schedule: Target Q4’09 Production Availability.Schedule: Target Q4’09 Production Availability.
4 Intel® 4 Intel® Scalable Scalable Memory Memory
InterconnectsInterconnects
4 Full-width 4 Full-width Intel® Intel®
QuickPath QuickPath InterconnectsInterconnects
Scaling Scaling Performance Performance
forwardforward
Copyright © 2009 Intel Corporation. All rights reserved.
Westmere
Copyright © 2009 Intel Corporation. All rights reserved.
Intel® AVX: A future 256-bit vector extension to SSE that benefits floating point intensive applications
Enhanced Data RearrangementUse the new 256 bit primitives to broadcast, mask loads and do data permutes
Wider VectorsIncreased from 128 bit to 256 bit
Organize, access and pull only necessary data more quickly and efficiently
Up to 2x peak FLOP output
KEY FEATURES BENEFITS
Fewer register copies More opportunities for parallel loads and compute operations, smaller code size
Three Operand, Non Destructive SyntaxDesigned for efficiency and future extensibility
Copyright © 2009 Intel Corporation. All rights reserved.
Scaling Performance Forward
Enabling you to:
– Accelerate computational performance
– Utilize an architecture that is best for your Application
– Employ a uniform development tool across all architectures
30
Scale Performance Forward To Multi & Many Core Solutions
30
………………
………………
ResearchResearch
No indication of
Actual product or dev. No indication of
Actual product or dev. ................
Copyright © 2009 Intel Corporation. All rights reserved.
Research: Ct: A Throughput Programming Research: Ct: A Throughput Programming LanguageLanguage
1 1 0 00 1 0 1 0 1 0 00 0 1 1
1 1 0 00 1 0 1 0 1 0 00 0 1 1+
Thread 4
0 0 1 1
0 0 1 1+
Thread 3
0 1 0 0
0 1 0 0+
Thread 2
0 0 0 1
0 0 0 1+
Thread 1
1 1 0 1
1 1 0 1+
Ct JIT Compiler:
Auto-vectorization, SSE, AVX, Core 1
SIMD Unit
Core 2
SIMD Unit
Core 3
SIMD Unit
Core 4
SIMD Unit
Programmer Thinks Serially; Ct Exploits Parallelism
Ct Parallel Runtime:
Auto-Scale to Increasing Cores
User Writes Serial-LikeCore Independent C++ Code
TVEC<F32> a(src1), b(src2);
TVEC<F32> c = a + b;
c.copyOt(dest);
TVEC<F32> a(src1), b(src2);
TVEC<F32> c = a + b;
c.copyOt(dest);
Primary Data Abstraction is the Nested Vector
Supports Dense, Sparse, and Irregular Data
Copyright © 2009 Intel Corporation. All rights reserved.
Larrabee is Intel’s first many core processor Larrabee is Intel’s first many core processor under development under development – Targets throughput computingTargets throughput computing– First implementation targets enthusiast graphicsFirst implementation targets enthusiast graphics
IA programmabilityIA programmability Programmable graphics piplineProgrammable graphics pipline
Efficient inter-block communicationEfficient inter-block communication C++ Prototype Libray released in March 09C++ Prototype Libray released in March 09
Throughput Computing: Throughput Computing: A Many Core Processor Architecture. LARRABEEA Many Core Processor Architecture. LARRABEE
VECTORIA COREVECTORIA CORE
INTERPROCESSOR NETWORKINTERPROCESSOR NETWORK
INTERPROCESSOR NETWORKINTERPROCESSOR NETWORK
FIX
ED
FU
NC
TIO
N L
OG
ICFI
XE
D F
UN
CTIO
N L
OG
IC
MEM
OR
Y a
nd I/O
IN
TER
FAC
ES
MEM
OR
Y a
nd I/O
IN
TER
FAC
ES
VECTORIA COREVECTORIA CORE
VECTORIA COREVECTORIA CORE
VECTORIA COREVECTORIA CORE
VECTORIA COREVECTORIA CORE
VECTORIA COREVECTORIA CORE
VECTORIA COREVECTORIA CORE
VECTORIA COREVECTORIA CORE
COHERENTCACHE
COHERENTCACHE
……
……
……
……
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
COHERENTCACHE
3232
Copyright © 2009 Intel Corporation. All rights reserved.
Terascale Experimental HardwareTerascale Experimental Hardware
Polaris
DRAM
Package
denser than C4 pitch
C4 pitch
256 KB SRAM per core256 KB SRAM per core4X C4 bump density4X C4 bump density
3200 thru-silicon vias3200 thru-silicon vias
Thru-Silicon Via
22 m
m
13.75 mm
CORE
ROUTER
80 Cores80 Cores1 TFLOP at 62 Watts1 TFLOP at 62 Watts256 GB/s bisection256 GB/s bisection
Optical Fiber
Multiplexer
Modulators
Hybrid lasers
40 Gbps Modulator40 Gbps Modulator
Tera-Bits: Tera-Bits: Si PhotonicsSi Photonics
ResearchResearch
Tera-Bytes: 3D Stacked MemoryTera-Bytes: 3D Stacked MemoryTera-Flops: Polaris PrototypeTera-Flops: Polaris Prototype
PackageMemory
Polaris with Cu bumpPolaris with Cu bump PolarisPolaris
Time To Solution = +
Memory Capacity * Bandwidth
Time To Compute + Time For I/O +
Time For Interconnect
ResearchResearch
Copyright © 2009 Intel Corporation. All rights reserved.
Research in Europe
Intel Strengthens Commitment to European Research
Jan. 29 -- With more than 800 R&D professionals in Europe, ...... ......Intel has also formed partnerships with leading European research institutes, including the Interuniversity Microelectronics Centre (IMEC) in Belgium, France's CEA Leti Laboratory and others including the Fraunhofer institutes in Germany. Together with the National University of Ireland, Intel leads one of the broadest open innovation initiatives in the IT industry through the Innovation Value Institute. Since 2003 Intel has also been collaborating with CERN on OpenLab I. Participation has recently been extended to include OpenLab III .....
Intel Strengthens Commitment to European Research
Jan. 29 -- With more than 800 R&D professionals in Europe, ...... ......Intel has also formed partnerships with leading European research institutes, including the Interuniversity Microelectronics Centre (IMEC) in Belgium, France's CEA Leti Laboratory and others including the Fraunhofer institutes in Germany. Together with the National University of Ireland, Intel leads one of the broadest open innovation initiatives in the IT industry through the Innovation Value Institute. Since 2003 Intel has also been collaborating with CERN on OpenLab I. Participation has recently been extended to include OpenLab III .....
Own labs, e.g. In Braunschweig, Cologne, Ulm....
Many collaborations with Research Centerse.g. with those in PRACE
EMEA HPC Roundtable
Increased effort in TurkeyEGEE, Intel event, ...
Own labs, e.g. In Braunschweig, Cologne, Ulm....
Many collaborations with Research Centerse.g. with those in PRACE
EMEA HPC Roundtable
Increased effort in TurkeyEGEE, Intel event, ...
Copyright © 2009 Intel Corporation. All rights reserved.
Intel’s Grid Activities
Developed prototype Grid components– Simplify creation of portable Grid applications– Enables management and use of virtualized
Grid resources (CERN cooperation)– Further development by the Unicore family
of projects (FZ Juelich)
Engage with Grid experts and users– European–union funded R&D projects (UniGrids,
NextGRID, SimDAT)
Interact with ecosystem, standards bodies– Open Grid Forum (technical influence, board membership)– Cloud computing as next steps
– July08: Intel, HP, Yahoo create cloud-computing labs A global cloud infrastructure for researchers will help advance the technology, according to the companies
Copyright © 2009 Intel Corporation. All rights reserved.
Solving Your HPC ChallengesSolving Your HPC Challenges
Source: Intel internal measurements, January 2009. For notes and disclaimers, see performance and legal information slides at end of this presentation.
– Certified cluster configurations to simplify Certified cluster configurations to simplify cluster deploymentcluster deployment
– Easily optimize application performance and Easily optimize application performance and eliminate the need to increase software eliminate the need to increase software resourcesresources
– Develop highly portable, parallel softwareDevelop highly portable, parallel software
– Huge performance gains to decrease time Huge performance gains to decrease time to discoveryto discovery
– Improved power technology to provide a Improved power technology to provide a more efficient data center solutionmore efficient data center solution
Intelligent Intelligent PerformancePerformance
Software Software VersatilityVersatility
DeploymentDeploymentEase of UseEase of Use
Scaling Performance ForwardScaling Performance Forward
Copyright © 2009 Intel Corporation. All rights reserved.
Intel in High Performance Computing
A Long Term Commitment to HPC SolutionsA Long Term Commitment to HPC Solutions
Dedicated,renowned expertise
Large scaleclustersfor test and optimization
Broad SW tools portfolio
TerascaleResearch
Leading performance, performance/watt
DefinedHPCapplicationplatform
Platform building blocks
ManufacturingProcess
Copyright © 2009 Intel Corporation. All rights reserved.
HPC @ Intel
Intelligent PerformanceIntelligent Performance
Have a successful conferenceHave a successful conference