copyright © 2011 intel corporation. all rights reserved. openlab confidential cern openlab ict...

Copyright © 2011 Intel Corporation. All rights reserved. Openlab Confidential

CERN openlab ICT Challenges workshop

Claudio Bellini

Business Development Manager Intel

Dec, 2013

TO C O M P E T E , YO U M U S T C O M P U T E !TO C O M P E T E , YO U M U S T C O M P U T E !


Agenda

Openlab collaboration Intel technology evolution Intel openlab engagement Q&A

2


Openlab

Great collaboration from openlab

– Engineering feedback on Intel products– S/w collaboration with HEP community– Dissemination seminars and workshop – Communication program


Innovation

Interconnect

MemoryProcessor Performance

Reliability& Resiliency Standard

Programming Model for Parallelism

PowerEfficiency


Manufacturing technology and power efficiency

At NTV, leakage power is substantial portion of the total power

0%

10%

20%

30%

40%

50%

60%

45nm 32nm 22nm 14nm 10nm 7nm 5nm

SD L

eaka

ge P

ower

100% Vdd

75% Vdd

50% Vdd

40% Vdd Increasing Variations

Product Baseline

Memory

VR

CPU CoreVRSys

AgentVRIOVR

PLLVR

Die

IVRIntegrated Voltage Regulator

Network Integration

New memory architecture and system memory

hierarchy

Siph communication


Ecosystem

Collaborating to accelerate the pace of discovery

For More information visit the Intel® Academic Program at:

Intel® Parallel Computing Centers

http: //software.intel.com/academic

Building the Next Wave of HPC Users

… with more to comeExaScale Computing

Research Lab, Paris

Performance and scalability of Exascale

applications

Tools for performance characterization

Comms avoiding algorithms

Architectural simulation

Scalable kernels and RT

ExaScience Lab,

Leuven

Scalable RTS and tools

New algorithms

Intel and BSC Exascale

Lab, Barcelona

ExaCluster Lab,

Jülich

Exascale cluster scalability

and reliability


Transformation of Intel

9

PC Chip CompanyComputingSolutions Provider

ServicesSoftwarePlatformSilicon

“Intel is changing to a full computing solutions company”

– Paul S. Otellini, CEO, Intel


Internet of Things : Software Innovation

Intel® Distribution of Apache Hadoop InfiniBand Interconnect

Hadoop Compute Nodes

Lustre Storage Nodes

Enterprise Edition Lustre

Intel Distribution Hadoop

http://www.google.com/url?sa=i&source=images&cd=&cad=rja&docid=VsE3zej3vik20M&tbnid=_oHQ4mUT4HCqAM:&ved=0CAgQjRwwAA&url=http://ieeenano2011.org/sponsors/sponsors-and-exhibitors/intel-logo/&ei=-_w4UZW-MomArAHm3oDYCA&psig=AFQjCNHKHnLMKWR3eHpPifd2UO0SPnhjqg&ust=1362775675881654


Intel engagement with openlab

DCSG : DataCenter and Connected System

Group EMO : Emea Marketing Organization SSG : Software and Solution Group

ILE : Intel Lab Europe

Thank You

12


Backup


IA Ecosystem Breadth and Depth

SoftwareBuilding Blocks

Processors

Focused on Single Thread and Parallel Codes

HardwareBuilding Blocks

FabricsCoprocessors

Focused on Highly Parallel and Vectorized Codes

Intel® Ethernet Products

Rack Optimized Servers Software and ServicesPedestals & Workstations RAID Solutions Systems

End Customers

Customer Reference BoardsSystem Validation Boards

Linux

Open FabricsCompiler

Open SHMEM

GCC Compiler Many Others

OpenMPI

POCs & Targeted Services


Legal DisclaimerINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

• Intel may make changes to specifications and product descriptions at any time, without notice.

• All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice.

• Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request.

• Penryn, Nehalem, Westmere, Sandy Bridge, and other code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user

• Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance.

• Intel, Xeon, Netburst, Core, VTune, and the Intel logo are trademarks of Intel Corporation in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Copyright © 2010 Intel Corporation.

copyright © 2011 intel corporation. all rights reserved. openlab confidential cern openlab ict...

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