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Copyright Agrawal & Srivaths, 2Copyright Agrawal & Srivaths, 2007007
Low-Power Design and Test, Lecture 5Low-Power Design and Test, Lecture 5 11
Low-Power Design and TestLow-Power Design and Test
Gate-Level Power Gate-Level Power OptimizationOptimization
Vishwani D. AgrawalVishwani D. AgrawalAuburn University, USAAuburn University, [email protected]@eng.auburn.edu
Srivaths RaviSrivaths RaviTexas Instruments IndiaTexas Instruments India
[email protected]@ti.com
Hyderabad, July 30-31, 2007http://www.eng.auburn.edu/~vagrawal/hyd.html
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 2
Components of PowerComponents of Power DynamicDynamic
Signal transitionsSignal transitions Logic activityLogic activity GlitchesGlitches
Short-circuitShort-circuit StaticStatic
LeakageLeakage
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 3
Power of a TransitionPower of a Transition
VVDDDD
GroundGround
CL
R
R
Dynamic Power
= CLVDD2/2 + Psc
Vi
Vo
isc
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 4
Dynamic PowerDynamic Power Each transition of a gate consumes Each transition of a gate consumes CV CV
22/2./2. Methods of power saving:Methods of power saving:
Minimize load capacitancesMinimize load capacitances Transistor sizingTransistor sizing Library-based gate selectionLibrary-based gate selection
Reduce transitionsReduce transitions Logic designLogic design Glitch reductionGlitch reduction
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 5
Glitch Power ReductionGlitch Power Reduction Design a digital circuit for minimum transient Design a digital circuit for minimum transient
energy consumption by eliminating hazardsenergy consumption by eliminating hazards
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 6
Theorem 1Theorem 1 For correct operation with minimum energy For correct operation with minimum energy
consumption, a Boolean gate must produce consumption, a Boolean gate must produce no more than no more than oneone event per transition. event per transition.
Output logic state changesOne transition is necessary
Output logic state unchangedNo transition is necessary
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 7
Event PropagationEvent Propagation
2 4 61
1 3
5
3
10
0
0
2
2
Path P1
P2
Path P3
Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 8
Inertial Delay of an InverterInertial Delay of an Inverter
dHL dLH
dHL+dLH
d = ──── 2
Vin
Vout
time
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 9
Multi-Input GateMulti-Input Gate
Delay = d
A
B
C
A
B
C d d Hazard or glitch
DPD
DPD: Differential path delay
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 10
Balanced Path DelaysBalanced Path Delays
Delay = d
A
B
C
A
B
C d No glitch
DPD
Delay buffer
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 11
Glitch Filtering by InertiaGlitch Filtering by Inertia
Delay ≥ DPD
A
B
C
A
B
C
d =DPD
Filtered glitch
DPD
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 12
Given that events occur at the input of a gate with Given that events occur at the input of a gate with inertial delay inertial delay dd at times, at times, tt11 ≤ . . . ≤ ≤ . . . ≤ ttnn , the number , the number of events at the gate output cannot exceedof events at the gate output cannot exceed
Theorem 2Theorem 2
min ( min ( n n , 1 + ), 1 + )ttnn – t – t11
----------------dd
ttnn - t - t11
tt11 t t22 t t33 t tnn timetime
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 13
Minimum Transient DesignMinimum Transient Design
Minimum transient energy condition for a Minimum transient energy condition for a Boolean gate:Boolean gate:
| t| tii - t - tjj | < d | < d
Where tWhere tii and t and tjj are arrival times of input are arrival times of input
events and d is the inertial delay of gateevents and d is the inertial delay of gate
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 14
Balanced Delay MethodBalanced Delay Method
All input events arrive simultaneouslyAll input events arrive simultaneously Overall circuit delay not increasedOverall circuit delay not increased Delay buffers may have to be insertedDelay buffers may have to be inserted
11 111111 11
111111
33
11 11
No increase in critical path delay
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 15
Hazard Filter MethodHazard Filter Method Gate delay is made greater than maximum input Gate delay is made greater than maximum input
path delay differencepath delay difference No delay buffers needed No delay buffers needed (least transient energy)(least transient energy) Overall circuit delay may increaseOverall circuit delay may increase
11 111111 11
33111111 11
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 16
Designing a Glitch-Free Designing a Glitch-Free CircuitCircuit
Maintain specified critical path delay.Maintain specified critical path delay. Glitch suppressed at all gates byGlitch suppressed at all gates by
Path delay balancingPath delay balancing Glitch filtering by increasing inertial delay of gatesGlitch filtering by increasing inertial delay of gates
A linear program optimally combines all objectives.A linear program optimally combines all objectives.
D
Delay = d1
Delay = d2
|d1 – d2| < D
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 17
Benchmark CircuitsBenchmark Circuits
Circuit
ALU4
C880
C6288
c7552
Max-delay(gates)
715
2448
4794
4386
No. ofBuffers
5 0
6234
294120
366111
Average
0.800.79
0.680.68
0.400.36
0.44 0.42
Peak
0.680.67
0.540.52
0.360.34
0.34 0.32
Normalized Power
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 18
Four-Bit ALUFour-Bit ALU
maxdelaymaxdelay Buffers insertedBuffers inserted
77 55
1010 22
1212 11
1515 00
Maximum Power Savings (zero-buffer design):
Peak = 33 %, Average = 21 %
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 19
ALU4: Original and Low-PowerALU4: Original and Low-Power
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 20
C7552 Circuit: Spice C7552 Circuit: Spice SimulationSimulation
Power Saving: Average 58%, Peak 68%Power Saving: Average 58%, Peak 68%
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 21
ReferencesReferences R. Fourer, D. M. Gay and B. W. Kernighan, R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling AMPL: A Modeling
Language for Mathematical ProgrammingLanguage for Mathematical Programming, South San Francisco: , South San Francisco: The Scientific Press, 1993.The Scientific Press, 1993.
M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Power,” Proc. ProRISC WorkshopProc. ProRISC Workshop, Mierlo, The Netherlands, Nov. , Mierlo, The Netherlands, Nov. 1996, pp. 183-188.1996, pp. 183-188.
V. D. Agrawal, “Low Power Design by Hazard Filtering,” V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. Proc. 1010thth Int’l Conf. VLSI DesignInt’l Conf. VLSI Design, Jan. 1997, pp. 193-197., Jan. 1997, pp. 193-197.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Programming Method,” Proc. Proc. 1212thth Int’l Conf. VLSI Design Int’l Conf. VLSI Design, Jan. , Jan. 1999, pp. 434-439.1999, pp. 434-439.
M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51.pp. 45-51.
T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum DynamicT. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Program,” Proc.Proc. 16 16thth Int’l Conf. VLSI DesignInt’l Conf. VLSI Design, Jan. 2003, pp. 527-, Jan. 2003, pp. 527-532.532.
T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” CMOS Logic for Low Power Design,” Proc.Proc. 18 18thth Int’l Conf. VLSI Int’l Conf. VLSI DesignDesign, Jan. 2005, pp. 596-603., Jan. 2005, pp. 596-603.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 22
Components of PowerComponents of Power DynamicDynamic
Signal transitionsSignal transitions Logic activityLogic activity GlitchesGlitches
Short-circuitShort-circuit StaticStatic
LeakageLeakage
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 23
Subthreshold ConductionSubthreshold ConductionVgs – Vth -Vds
Ids = I0 exp( ───── ) × (1– exp ── ) nVT VT
Sunthreshold slope
0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs
Ids
1mA100μA10μA1μA
100nA10nA1nA
100pA10pA
Vth
Sub
thre
shol
dre
gion
Saturation region
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 24
Thermal Voltage, Thermal Voltage, vvTT
VT = kT/q = 26 mV, at room temperature.
When Vds is several times greater than VT
Vgs – Vth Ids = I0 exp( ───── )
nVT
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 25
Leakage CurrentLeakage Current
Leakage current equals Leakage current equals IIdsds when when VVgsgs= 0= 0
Leakage current, Leakage current, IIdsds = = II00 exp(exp(-V-Vthth/nV/nVTT))
At cutoff, At cutoff, VVgsgs = = VVth th , and , and IIdsds = = II00
Lowering leakage to 10Lowering leakage to 10--bbII00
VVthth = = bnVbnVT T ln 10 = 1.5ln 10 = 1.5b b × 26 ln 10 = 90× 26 ln 10 = 90bb mVmV
Example: To lower leakage to Example: To lower leakage to II00/1,000/1,000
VVthth = 270 mV = 270 mV
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 26
Threshold VoltageThreshold Voltage VVthth = = VVt0t0 + + γγ[([(ΦΦss++VVsbsb))½½- - ΦΦss
½½]]
VVt0t0 is threshold voltage when source is at is threshold voltage when source is at body potential (body potential (0.4 V for 180nm process0.4 V for 180nm process))
ΦΦs s = = 22VVTT ln(ln(NNA A /n/ni i )) is surface potentialis surface potential
γγ = (2 = (2qqεεsi si NNAA))½½ttox ox //εεoxox is body effect is body effect coefficient (0.4 to 1.0)coefficient (0.4 to 1.0)
NNAA is doping level = is doping level = 8×108×101717 cm cm-3-3
nnii = = 1.45×101.45×101010 cm cm-3-3
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 27
Threshold Voltage, Threshold Voltage, VVsb sb = 1.1V= 1.1V
Thermal voltage, Thermal voltage, VVTT = = kT/qkT/q = 26 mV = 26 mV
ΦΦss = 0.93 V = 0.93 V
εεoxox = 3.9×8.85×10 = 3.9×8.85×10-14-14 F/cm F/cm
εεsisi = 11.7×8.85×10 = 11.7×8.85×10-14-14 F/cm F/cm
ttoxox = 40 A = 40 Aoo
γγ = 0.6 V = 0.6 V½½
VVthth = = VVt0t0 + + γγ[([(ΦΦss++VVsbsb))½½- - ΦΦss½½] = 0.68 V] = 0.68 V
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 28
A Sample CalculationA Sample Calculation
VVDDDD = 1.2V, 100nm CMOS process = 1.2V, 100nm CMOS process Transistor width, W = 0.5Transistor width, W = 0.5μμmm OFF device (OFF device (VVgsgs = = VVthth) leakage) leakage
II00 = 20nA/ = 20nA/μμm, for low threshold transistorm, for low threshold transistor II00 = 3nA/ = 3nA/μμm, for high threshold transistorm, for high threshold transistor
100M transistor chip100M transistor chip Power = (100×10Power = (100×1066/2)(0.5×20×10/2)(0.5×20×10-9-9A)(1.2V) = A)(1.2V) =
600mW 600mW for all low-threshold transistorsfor all low-threshold transistors Power = (100×10Power = (100×1066/2)(0.5×3×10/2)(0.5×3×10-9-9A)(1.2V) = A)(1.2V) =
90mW 90mW for all high-threshold transistorsfor all high-threshold transistors
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 29
Dual-Threshold ChipDual-Threshold Chip
Low-threshold only for 20% transistors Low-threshold only for 20% transistors on critical path.on critical path.
Leakage power Leakage power = 600×0.2 + = 600×0.2 + 90×0.890×0.8
= 120 + 72= 120 + 72
= 192 mW= 192 mW
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 30
Dual-Threshold CMOS CircuitDual-Threshold CMOS Circuit
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 31
Dual-Threshold DesignDual-Threshold Design To maintain performance, all gates on To maintain performance, all gates on
the critical path are assigned low the critical path are assigned low VVth th .. Most of the other gates are assigned Most of the other gates are assigned
high high VVth th . But,. But, Some gates on non-critical paths may Some gates on non-critical paths may
also be assigned low also be assigned low VVthth to prevent to prevent those paths from becoming critical.those paths from becoming critical.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 32
Integer Linear Programming (ILP) Integer Linear Programming (ILP) to Minimize Leakage Powerto Minimize Leakage Power
Use dual-threshold CMOS processUse dual-threshold CMOS process First, assign all gates low First, assign all gates low VVthth
Use an ILP model to find the delay (Use an ILP model to find the delay (TTcc) of the ) of the critical pathcritical path
Use another ILP model to find the optimal Use another ILP model to find the optimal VVthth assignment as well as the reduced leakage assignment as well as the reduced leakage power for all gates without increasing power for all gates without increasing TTcc
Further reduction of leakage power possible by Further reduction of leakage power possible by letting letting TTcc increase increase
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 33
ILP -ILP -VariablesVariables For each gate For each gate ii define two variables. define two variables. TTi i :: the longest time at which the the longest time at which the
output of gate output of gate ii can produce an event can produce an event after the occurrence of an input event after the occurrence of an input event at a primary input of the circuit. at a primary input of the circuit.
XXi i :: a variable specifyinga variable specifying low or high low or high VVthth for gate for gate i i ;; X Xii is an integer [0, 1], is an integer [0, 1],
1 1 gate gate ii is assigned low is assigned low VVth th ,,
0 0 gate gate ii is assigned high is assigned high VVth th ..
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 34
ILP - ILP - objective functionobjective function
minimize the sum of all gate leakage currents, minimize the sum of all gate leakage currents, given by given by
IILi Li is the leakage current of gate is the leakage current of gate ii with low with low VVthth IIHiHi is the leakage current of gate is the leakage current of gate ii with high with high VVthth Using SPICE simulation results, construct a Using SPICE simulation results, construct a
leakage current look up table, which is indexed leakage current look up table, which is indexed by the gate type and the input vectorby the gate type and the input vector. .
i
leakiddleak IVP
i
HiiLii IXIXMin 1
Leakage power:
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 35
ILP - ILP - ConstraintsConstraints
For each gateFor each gate (1)(1)
output of gate output of gate jj is fanin of gate is fanin of gate ii
(2) (2)
Max delay constraints for primary outputs Max delay constraints for primary outputs (PO)(PO)
(3) (3)
TTmaxmax is the maximum delay of the critical path is the maximum delay of the critical path
HiiLiiji DXDXTT 1
10 iX
maxTTi
Gate j
Gate i
Tj
Ti
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 36
ILP Constraint ExampleILP Constraint Example
Assume all primary input (PI) signals on the left arrive at Assume all primary input (PI) signals on the left arrive at the same time. the same time.
For gate 2, constraints areFor gate 2, constraints are
0
3
1
2
222202 1 HL DXDXTT
22222 10 HL DXDXT
HiiLiiji DXDXTT 1
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 37
ILP – Constraints (cont.)ILP – Constraints (cont.)
DDHi Hi is the delay of gateis the delay of gate i i with highwith high V Vthth
DDLi Li is the delay of gateis the delay of gate i i with lowwith low V Vthth
A second look-up table is constructed A second look-up table is constructed and specifies the delay for given gate and specifies the delay for given gate type and fanout number. type and fanout number.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 38
ILP – Finding Critical DelayILP – Finding Critical Delay
TTmaxmax can be specified or be the delay of longest path can be specified or be the delay of longest path ((TTcc).).
To find To find TTc c , we change constraints (2) to an equation, , we change constraints (2) to an equation, assigning all gates low assigning all gates low VVthth
Maximum Maximum TTii in the ILP solution is in the ILP solution is TTcc..
If we replace If we replace TTmaxmax with with TTc c , the objective function , the objective function minimizes leakage power without sacrificing minimizes leakage power without sacrificing performance.performance.
10 iX
maxTTi
1iX
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 39
Power-Delay TradeoffPower-Delay Tradeoff
1 1.1 1.2 1.3 1.4 1.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalized Critical Path Delay
Nor
mal
ized
Lea
kage
Pow
er
C432
C880
C1908
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 40
Power-Delay TradeoffPower-Delay Tradeoff
If we gradually increase If we gradually increase TTmaxmax from from TTc c , , leakage power is further reduced, because leakage power is further reduced, because more gates can be assigned high more gates can be assigned high VVth th ..
But, the reduction trends to become But, the reduction trends to become slower.slower.
When When TTmax max = = (130%)(130%) T Tcc , the reduction , the reduction about levels off because almost all gates about levels off because almost all gates are assigned high are assigned high VVth th . .
Maximum leakage reduction can be 98%. Maximum leakage reduction can be 98%.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 41
Leakage & Dynamic Power Optimization Leakage & Dynamic Power Optimization 70nm CMOS c7552 Benchmark Circuit @ 70nm CMOS c7552 Benchmark Circuit @
9090ooCC
0
100
200
300
400
500
600
700
800
900
Mic
row
att
s
Original circuit Optimizeddesign
Leakage powerDynamic powerTotal power
Leak
age
exce
eds
dyn
amic
pow
er Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378-387, December 2006.
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 42
SummarySummary
Leakage power is a significant fraction of Leakage power is a significant fraction of the total power in nanometer CMOS the total power in nanometer CMOS devices.devices.
Leakage power increases with temperature; Leakage power increases with temperature; can be as much as dynamic power.can be as much as dynamic power.
Dual threshold design can reduce leakage.Dual threshold design can reduce leakage. Reference: Y. Lu and V. D. Agrawal, “CMOS Reference: Y. Lu and V. D. Agrawal, “CMOS
Leakage and Glitch Minimization for Power-Leakage and Glitch Minimization for Power-Performance Tradeoff,” Performance Tradeoff,” J. Low Power Electronics, J. Low Power Electronics, Vol. 2, No. 3, pp. 378-387, December 2006.Vol. 2, No. 3, pp. 378-387, December 2006.
Access other paper atAccess other paper at http://www.eng.auburn.edu/~vagrawal/TALKS/talks.htmlhttp://www.eng.auburn.edu/~vagrawal/TALKS/talks.html
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 43
Problem: Leakage ReductionProblem: Leakage ReductionFollowing circuit is designed in 65nm CMOS technology using low threshold transistors. Each gate has a delay of 5ps and a leakage current of 10nA. Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally design the circuit with dual-threshold gates to minimize the leakage current without increasing the critical path delay. What is the percentage reduction in leakage power? What will the leakage power reduction be if a 30% increase in the critical path delay is allowed?
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 44
Solution 1: No Delay IncreaseSolution 1: No Delay IncreaseThree critical paths are from the first, second and third inputs to the last output, shown by a dashed line arrow. Each has five gates and a delay of 25ps. None of the five gates on the critical path (red arrow) can be assigned a high threshold. Also, the two inverters that are on four-gate long paths cannot be assigned high threshold because then the delay of those paths will become 27ps. The remaining three inverters and the NOR gate can be assigned high threshold. These gates are shaded grey in the circuit.The reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73%Critical path delay = 25ps
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 45
Solution 2: 30% Delay IncreaseSolution 2: 30% Delay IncreaseSeveral solutions are possible. Notice that any 3-gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow.The reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09%Critical path delay = 29ps