jan 2005 agrawal: low power design 1 minimum dynamic power design using variable input delay cmos...
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Jan 2005 Agrawal: Low Power Design 1
Minimum Dynamic Power Minimum Dynamic Power DesignDesign Using Variable Input Using Variable Input
Delay CMOS LogicDelay CMOS LogicVishwani D. AgrawalVishwani D. Agrawal
Dept. of ECE, Auburn University, AL, USADept. of ECE, Auburn University, AL, USAhttp://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal
Tezaswi RajaTezaswi RajaTransmeta Corp., San Jose, CA, USATransmeta Corp., San Jose, CA, USA
Michael L. BushnellMichael L. BushnellDept. of ECE, Rutgers University, NJ, USADept. of ECE, Rutgers University, NJ, USA
Research Funded by: Research Funded by: National Science FoundationNational Science Foundation
Jan 2005 2Agrawal: Low Power Design
Talk OutlineTalk Outline MotivationMotivation Background on Glitch Elimination Background on Glitch Elimination
TechniquesTechniques Problem StatementProblem Statement New Variable Input Delay LogicNew Variable Input Delay Logic Transistor Level Design of Variable Transistor Level Design of Variable
Input Delay GateInput Delay Gate ResultsResults Physical Level ImplementationPhysical Level Implementation Conclusion and Future WorkConclusion and Future Work
Jan 2005 3Agrawal: Low Power Design
What Are Glitches?What Are Glitches?
Glitches occur due to differential Glitches occur due to differential (unbalanced) path delays.(unbalanced) path delays.
Glitches are transients that are unnecessary Glitches are transients that are unnecessary for the correct functioning of the circuit.for the correct functioning of the circuit.
Glitches waste power in CMOS circuits.Glitches waste power in CMOS circuits.
Delay =12
2
Delay = 2
Jan 2005 4Agrawal: Low Power Design
Prior workPrior work Delay Balancing for Glitch Elimination:Delay Balancing for Glitch Elimination:
Balancing delays by adding buffers on select paths.Balancing delays by adding buffers on select paths. Ref: Chandrakasan and Brodersen and other booksRef: Chandrakasan and Brodersen and other books
Hazard Filtering for Glitch Elimination:Hazard Filtering for Glitch Elimination: Glitch suppression by increasing the inertial delay of Glitch suppression by increasing the inertial delay of
gates.gates. Ref: Agrawal Ref: Agrawal et alet al., ., VLSI DesignVLSI Design `97, `99, `03, `04. `97, `99, `03, `04.
Gate Sizing for Glitch Elimination: Gate Sizing for Glitch Elimination: Every gate is modeled as an equivalent inverter. Every gate is modeled as an equivalent inverter. Model is non-linear Model is non-linear Ref : Berkelaar Ref : Berkelaar et al.,et al., IEEE Trans. on Circuits and SystemsIEEE Trans. on Circuits and Systems
‘96‘96 Transistor Sizing for Area-Speed Oprimization:Transistor Sizing for Area-Speed Oprimization:
Size the width and length of every transistor to get exact Size the width and length of every transistor to get exact delay.delay.
Model is non-linearModel is non-linear Convergence problems due to large search space.Convergence problems due to large search space. Ref: Fishburn Ref: Fishburn et al.,et al., ICCADICCAD ’85. ’85.
Jan 2005 5Agrawal: Low Power Design
Example: Why Buffers Were Example: Why Buffers Were Necessary?Necessary?
Delay unit is the smallest delay possible Delay unit is the smallest delay possible for a gate in a given technology.for a gate in a given technology.
Critical Path is the longest delay path in Critical Path is the longest delay path in the circuit and determines the speed of the circuit and determines the speed of the circuit.the circuit.
1
1
1
Critical path delay = 3
Jan 2005 6Agrawal: Low Power Design
For glitch free operation of first gate:For glitch free operation of first gate: Differential delay at inputs < inertial delayDifferential delay at inputs < inertial delay OKOK
1
1
1
Example (cont.)Example (cont.)0
0
time
Jan 2005 7Agrawal: Low Power Design
1
1
1
Example (cont.)Example (cont.)
For glitch free operation of second gate: Differential delay at inputs < inertial delay OK (Assuming equality does not produce a glitch)
1
0
time
Jan 2005 8Agrawal: Low Power Design
1
1
1
Example (cont.)Example (cont.)
For glitch free operation of third gate: Differential delay at inputs < inertial delay Not true for gate 3
2
0
time
Jan 2005 9Agrawal: Low Power Design
1
1
1
Example (cont.)Example (cont.)
For glitch free operation with no IO delay increase: Must add a delay buffer.
Buffer is necessary for conventional gate design – only gate output delay is controllable.
2
11
time
Jan 2005 10Agrawal: Low Power Design
1
1
Controllable Input Delay GatesControllable Input Delay Gates
Assume gate input delays to be controllable Glitches can be suppressed without buffers
2
0
1
2
time
Jan 2005 11Agrawal: Low Power Design
Problem StatementProblem Statement Find a glitch reduction technique such that:Find a glitch reduction technique such that:
All glitches are eliminated in the circuit.All glitches are eliminated in the circuit. No delay buffers are inserted in the circuit.No delay buffers are inserted in the circuit. Circuit operates at the highest possible speed Circuit operates at the highest possible speed
permitted by the device technology.permitted by the device technology. Technique should be scalable for large circuits.Technique should be scalable for large circuits. Circuits are realizable at the physical level of Circuits are realizable at the physical level of
design.design.
Note: The objective is to minimize switching power. Hence, no attempt is made to reduce short-circuit and leakage power, which is an order of magnitude lower for present CMOS technologies; those components of power may be addressed in the future research.
Jan 2005 12Agrawal: Low Power Design
New Variable Input Delay New Variable Input Delay LogicLogic
Output DelayOutput Delay Propagation delay through a gate from the Propagation delay through a gate from the
inputs to the outputs.inputs to the outputs. Input DelayInput Delay
Extra delay that can be added on a single I/O Extra delay that can be added on a single I/O path through the gate, which can be controlled path through the gate, which can be controlled independentlyindependently of the other input delays. of the other input delays.
Variable Input Delay LogicVariable Input Delay Logic Logic level design of circuits using components Logic level design of circuits using components
with variable input and output delays along with variable input and output delays along different I/O paths through the gate.different I/O paths through the gate.
I/O path delay through a gate = Input Delay + Output Delay
Jan 2005 13Agrawal: Low Power Design
Delay Model for a New Delay Model for a New GateGate
Separate the output (inertial) and input delay variables.Separate the output (inertial) and input delay variables. dd3 3 - output delay of the gate.- output delay of the gate. dd3,13,1 - input delay of the gate along path from 1 to 3.- input delay of the gate along path from 1 to 3.
Technology constraint: Technology constraint: 0 0 d d3,1 3,1 ,d,d3,2 3,2 u ubb
Input delay difference has an upper bound, which we define as Input delay difference has an upper bound, which we define as
Gate Input Differential Delay Upper Bound ( uGate Input Differential Delay Upper Bound ( ub b ).).
d3,1 + d33
1
2 d3,2 + d3
Jan 2005 14Agrawal: Low Power Design
Gate Input Differential Delay Gate Input Differential Delay Upper Bound (Upper Bound (uubb))
It is a measure of the maximum difference in It is a measure of the maximum difference in delay of any two I/O paths through the gate, that delay of any two I/O paths through the gate, that can be designed in a given CMOS technology.can be designed in a given CMOS technology.
Arbitrary input delays cannot be realized in practice Arbitrary input delays cannot be realized in practice due to the technology limitation at the transistor and due to the technology limitation at the transistor and layout levels.layout levels.
The bound The bound uubb is the limit of flexibility allowed by the is the limit of flexibility allowed by the technology to the designer at the transistor and layout technology to the designer at the transistor and layout levels.levels.
The following The following feasibility conditionfeasibility condition must be imposed must be imposed while determining delays for glitch suppression:while determining delays for glitch suppression:
0 0 d di, j i, j uubb
Jan 2005 15Agrawal: Low Power Design
New Linear ProgramsNew Linear Programs We propose two new LPs for designing We propose two new LPs for designing
circuits based on the specifications of circuits based on the specifications of the design.the design.
Minimum dynamic power (MDP) LPMinimum dynamic power (MDP) LP Where the circuit consumes least power Where the circuit consumes least power
possible and operates at the highest possible and operates at the highest possible speed for that power.possible speed for that power.
Delay specification (DS) LPDelay specification (DS) LP Where the circuit meets a given delay Where the circuit meets a given delay
requirement but does it by adding the requirement but does it by adding the smallest number of buffers.smallest number of buffers.
Jan 2005 16Agrawal: Low Power Design
6
New MDP LP ExampleNew MDP LP Example51
72
3
4 Gate inertial delay variables Gate inertial delay variables dd5 5 ....dd77 Gate input delay variables Gate input delay variables ddi, ji, j for every path through for every path through
gate i from input jgate i from input j Corresponding window variables Corresponding window variables tt5 5 ....tt77 and and TT5 5 ....TT77. .
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Jan 2005 17Agrawal: Low Power Design
6
New MDP LP Example New MDP LP Example (cont.)(cont.)
51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Inertial delay constraint for gate 5: Inertial delay constraint for gate 5: dd55 1 1 Input delay (feasibility) constraints for gate 5:Input delay (feasibility) constraints for gate 5:
0 0 d d5,1 5,1 u ubb 0 0 d d5,2 5,2 u ubb
Jan 2005 18Agrawal: Low Power Design
Differential delay constraints for gate 5:Differential delay constraints for gate 5:TT55 >> T T1 1 + d+ d5,15,1 + d + d55; ; tt55 << t t11+ d+ d5,15,1 + d + d55; ;
dd55 > T > T55 – t – t55;;
TT55 >> T T2 2 + d+ d5,25,2 + d + d55;; tt55 << t t22+ d+ d5,25,2 + d + d55;;
6
New MDP LP Example New MDP LP Example (cont.)(cont.)
51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Jan 2005 19Agrawal: Low Power Design
6
New MDP LP Example New MDP LP Example (cont.)(cont.)
51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
IO delay constraint for each PO in the circuit:IO delay constraint for each PO in the circuit:
TT77 maxdelaymaxdelay;;maxdelay maxdelay is the parameter which gives the delay of the is the parameter which gives the delay of the
critical path.critical path.This determines the speed of operation of the circuit.This determines the speed of operation of the circuit.
Jan 2005 20Agrawal: Low Power Design
6
New MDP LP Example New MDP LP Example (cont.)(cont.)
51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Objective FunctionObjective Function: : minimizeminimize maxdelaymaxdelay;; This gives This gives the fastest possible, minimum dynamic power the fastest possible, minimum dynamic power
consuming circuit, consuming circuit, given the feasibility condition for the given the feasibility condition for the technology.technology.
Jan 2005 21Agrawal: Low Power Design
Solution CurvesSolution Curves
ub=0ub=5ub=10ub=15ub= ∞
Fastest Possible Design in any
technology
Minimum Dynamic
power
Maxdelay
Power
Power consumed by buffers
Previous solutions
New MDP LP solutions
Jan 2005 22Agrawal: Low Power Design
Delay Specification LPDelay Specification LP
If the design needs to meet a given delay If the design needs to meet a given delay specification and the designer is willing to specification and the designer is willing to sacrifice some dynamic power by inserting sacrifice some dynamic power by inserting buffers.buffers.
Modifications to MDP LPModifications to MDP LP Insert buffer variables at every fanout stem and Insert buffer variables at every fanout stem and
branches and at PIs (similar to Linear constraint branches and at PIs (similar to Linear constraint set method by Raja set method by Raja et al.et al.))
maxdelaymaxdelay is a given parameter, which is the is a given parameter, which is the maximum delay of the critical path according to maximum delay of the critical path according to specification.specification.
Jan 2005 23Agrawal: Low Power Design
Delay Specification LPDelay Specification LP
Components of the LPComponents of the LP Gate constraints – unchangedGate constraints – unchanged Input delay (feasibility) constraints – Input delay (feasibility) constraints –
unchanged for same unchanged for same uubb
Differential delay constraints – unchangedDifferential delay constraints – unchanged Maxdelay constraints – unchanged but Maxdelay constraints – unchanged but
maxdelaymaxdelay is a given parameter. is a given parameter. Objective function:Objective function:
Minimize sum ( dMinimize sum ( djj) where j ) where j єє buffers buffers
Jan 2005 24Agrawal: Low Power Design
Solution CurvesSolution Curves
ub=0ub=5ub=10ub=15ub= ∞
Fastest Possible Design in any
technology
Minimum Dynamic
power
Maxdelay
Power
Power consumed by buffers
Previous solutions
New MDP LP solutions
New DS LP solutions
Jan 2005 25Agrawal: Low Power Design
Transistor Level Transistor Level ImplementationImplementation
Conventional CMOS gate design:Conventional CMOS gate design: Delay = Ron ( Crouting + Cinput )
Energy = 0.5 (Cr + Cin ) V2
Delay can be changed by changing the resistance or the capacitance.
Resistance does not affect energy per transition.
Ron
Cr CinCp
Cr
Ron
d3,1
d3,2
Cr
Ron
Cin
Cin
Jan 2005 26Agrawal: Low Power Design
Transistor Level Transistor Level ImplementationImplementation
Possible implementations of the variable Possible implementations of the variable input delay gate:input delay gate: Capacitance manipulationCapacitance manipulation method where the method where the
input capacitance offered by the respective input capacitance offered by the respective transistor pair is varied.transistor pair is varied.
Pass transistor added designPass transistor added design where an extra where an extra transistor is added to increase the resistance and transistor is added to increase the resistance and thereby the input delay. We propose the addition thereby the input delay. We propose the addition of:of:
Single nMOS transistorSingle nMOS transistor CMOS pass transistorCMOS pass transistor
We describe the single We describe the single nnMOS transistor added MOS transistor added design in detail here. The other two are design in detail here. The other two are documented in the thesis.documented in the thesis.
Jan 2005 27Agrawal: Low Power Design
Single Single nnMOSFET Added MOSFET Added DesignDesign
The input delay can be added by an The input delay can be added by an nnMOS MOS transistor in series to the path desired.transistor in series to the path desired.
The addition of resistance does not increase the The addition of resistance does not increase the energy per transition.energy per transition.
d3,2 = Ron (Cr + Cin )
Energy = 0.5 (Cr + Cin ) V2
d3,1 = Ron (Cr + Cin ) + Rs Cin
d3,1 = Output + Input delayCr
Ron
d3,1
d3,2
Rs
Cr
Ron
Cin
Cin
Jan 2005 28Agrawal: Low Power Design
Rs
Effect of Input SlopeEffect of Input Slope
Too large Too large uubb cannot be realized in practice due to noise cannot be realized in practice due to noise issues.issues.
Increased resistance degrades the slope of a signal and we Increased resistance degrades the slope of a signal and we use the CMOS gate following it to regenerate the slope.use the CMOS gate following it to regenerate the slope.
The regenerative capability of a gate is limited and this The regenerative capability of a gate is limited and this determines practical determines practical uubb value. value.
The slope allowed in a design depends on the noise The slope allowed in a design depends on the noise specifications of the circuit.specifications of the circuit.
Jan 2005 29Agrawal: Low Power Design
Single nMOSFET Added Single nMOSFET Added DesignDesign
Advantages:Advantages: Almost completely independent control of input delays.Almost completely independent control of input delays. uubb is very high compared to capacitance manipulation is very high compared to capacitance manipulation
method.method. Very less overhead compared to a conventional buffer.Very less overhead compared to a conventional buffer. Can be integrated to full-custom as well as standard cell Can be integrated to full-custom as well as standard cell
place and route design flows.place and route design flows. Design Issues:Design Issues:
nMOSFET degrades the signal when passing logic 1. nMOSFET degrades the signal when passing logic 1. Hence, it increases the leakage of the transistors in the Hence, it increases the leakage of the transistors in the fanout stages. However, this is for certain input fanout stages. However, this is for certain input combinations only.combinations only.
Short circuit current is a function of the ratio of Short circuit current is a function of the ratio of input/output slopes. Since we increase the input slope by input/output slopes. Since we increase the input slope by inserting resistance, it might increase short circuit power inserting resistance, it might increase short circuit power by a minor amount.by a minor amount.
Jan 2005 30Agrawal: Low Power Design
CMOS Pass Transistor Added CMOS Pass Transistor Added DesignDesign
The input delay can be added by the input CMOS The input delay can be added by the input CMOS pass transistor in series to the path desired.pass transistor in series to the path desired.
This does not degrade the signal as both transistors This does not degrade the signal as both transistors together conduct both logic values well.together conduct both logic values well.
d3,2 = Ron (Cr + Cin)
Energy = 0.5 (Cr + Cin) V2
d3,1 = Ron (Cr + Cin) + Rs Cin
d3,1 = Output + Input delayCr
Ron
d3,1
d3,2
Rs
Cr
Ron
Cin
Cin
Jan 2005 31Agrawal: Low Power Design
Technology MappingTechnology Mapping
Determine sizes of transistors in a gate for the Determine sizes of transistors in a gate for the given delay and given load capacitance.given delay and given load capacitance.
First guess is given by the look-up table.First guess is given by the look-up table. Second stage is sensitivity driven. Second stage is sensitivity driven. Reduces the complexity of transistor search.Reduces the complexity of transistor search.
Look Up Table for sizes
Delay required
Error acceptab
le?
Sensitivity of each
transistor size to delay
Increment that
transistor dimension
Transistor Sizes
yes no
Jan 2005 32Agrawal: Low Power Design
Results for Speed of Circuit Results for Speed of Circuit Using MDP LPUsing MDP LP
MaxdelayMaxdelay is normalized to the length of the critical path when all gates are of is normalized to the length of the critical path when all gates are of unit delay.unit delay.
Each curve is a different benchmark circuit.Each curve is a different benchmark circuit. As we increase As we increase uubb the circuit becomes faster. the circuit becomes faster. Flexibility required for fastest operation of circuit is proportional to the size of Flexibility required for fastest operation of circuit is proportional to the size of
the circuit.the circuit.
Jan 2005 33Agrawal: Low Power Design
Power Opt. Using MDP LP (for Power Opt. Using MDP LP (for uubb=10)=10)
CircuitCircuit No. No. of of
vectovectorsrs
maxdelmaxdelayay
NorNorm. m.
delaydelay
Original Original powerpower
Optimized Optimized powerpower
Avg.Avg. PeakPeak Avg.Avg. PeakPeak
c432c432 5656 7171 4.174.17 1.01.0 1.01.0 0.650.65 0.550.55
c499c499 5454 3434 2.262.26 1.01.0 1.01.0 0.700.70 0.650.65
c880c880 7878 4545 1.501.50 1.01.0 1.01.0 0.480.48 0.450.45
c1355c1355 8787 6767 2.052.05 1.01.0 1.01.0 0.470.47 0.360.36
c1908c1908 144144 173173 4.324.32 1.01.0 1.01.0 0.540.54 0.440.44
c2670c2670 8282 3535 1.091.09 1.01.0 1.01.0 0.680.68 0.560.56
c3540c3540 200200 347347 7.387.38 1.01.0 1.01.0 0.530.53 0.430.43
c5315c5315 157157 542542 11.011.066
1.01.0 1.01.0 0.530.53 0.440.44
c6288c6288 141141 124124 1.871.87 1.01.0 1.01.0 0.220.22 0.180.18
c7552c7552 158158 5050 1.161.16 1.01.0 1.01.0 0.280.28 0.260.26
Jan 2005 34Agrawal: Low Power Design
Power Opt. Using DS LP (for Power Opt. Using DS LP (for uubb=10)=10)
CircuiCircuitt
Norm.Norm.
MaxdelMaxdelayay
Conventional gatesConventional gates
(Raja (Raja et alet al., ., VLSI VLSI DesignDesign `03) `03)
Variable input Variable input delay gatesdelay gates
Avg.Avg. PeakPeak BuffeBuffersrs
Avg.Avg. PeakPeak BuffeBuffersrs
c432c432 1.01.0 0.720.72 0.670.67 9595 0.690.69 0.660.66 6161
2.02.0 0.620.62 0.600.60 6666 0.650.65 0.550.55 00
c499c499 1.01.0 0.910.91 0.870.87 4848 0.860.86 0.840.84 00
2.02.0 0.700.70 0.660.66 00 0.710.71 0.650.65 00
c880c880 1.01.0 0.680.68 0.540.54 6262 0.580.58 0.450.45 11
2.02.0 0.680.68 0.520.52 3434 0.560.56 0.450.45 00
c1355c1355 1.01.0 0.580.58 0.480.48 224224 0.480.48 0.420.42 6464
2.02.0 0.570.57 0.480.48 192192 0.440.44 0.390.39 3232
c1908c1908 1.01.0 0.690.69 0.590.59 219219 0.560.56 0.460.46 55
2.02.0 0.590.59 0.440.44 7070 0.550.55 0.450.45 44
Jan 2005 35Agrawal: Low Power Design
Power Opt. Using DS LP (for Power Opt. Using DS LP (for uubb=10)=10)
CircuiCircuitt
Norm.Norm.
MaxdelMaxdelayay
Power (conventional Power (conventional gates)gates)
(Raja (Raja et alet al., ., VLSI VLSI DesignDesign `03) `03)
Power (variable Power (variable input delay gates)input delay gates)
Avg.Avg. PeakPeak BuffeBuffersrs
Avg.Avg. PeakPeak BuffeBuffersrs
c2670c2670 1.01.0 0.790.79 0.650.65 157157 0.700.70 0.560.56 22
2.02.0 0.710.71 0.580.58 3535 0.690.69 0.570.57 00
c3540c3540 1.01.0 0.640.64 0.440.44 239239 0.570.57 0.460.46 33
2.02.0 0.580.58 0.460.46 140140 0.540.54 0.430.43 11
c5315c5315 1.01.0 0.630.63 0.520.52 280280 0.570.57 0.480.48 2626
2.02.0 0.600.60 0.450.45 171171 0.550.55 0.460.46 44
c6288c6288 1.01.0 0.400.40 0.360.36 294294 0.910.91 0.870.87 584584
2.02.0 0.360.36 0.340.34 120120 0.210.21 0.160.16 00
c7552c7552 1.01.0 0.380.38 0.340.34 366366 0.280.28 0.240.24 11
2.02.0 0.360.36 0.320.32 111111 0.270.27 0.240.24 00
Jan 2005 36Agrawal: Low Power Design
Example CircuitExample Circuit
Buffer optimized Buffer optimized CircuitCircuit
4 5
7
6123
d=2
d=1
d=1
d=1
4 5
7
6123
d=1
d=2
d=1
d=1
d=1
4 5
7
6123
d=2
d=1
d=1
d=2
d=1
d=1
Unoptimized CircuitUnoptimized Circuit
nMOS optimized nMOS optimized CircuitCircuit
Jan 2005 37Agrawal: Low Power Design
Example Circuit – Spectre Example Circuit – Spectre ResultsResults
time time timeUnoptimized CircuitUnoptimized Circuit Buffer optimized Buffer optimized
CircuitCircuit nMOS optimized nMOS optimized
CircuitCircuit
Jan 2005 38Agrawal: Low Power Design
Physical Level VerificationPhysical Level VerificationAMPL
Technology Mapping
Create Cells using Prolific
Standard Cell Place and Route
Extract Routing Capacitance
Analog Power simulations
Delays
Transistor Sizes
Standard Cell Library
Layout
Routing load
Energy Consumption
Routing acceptable?
No
Yes
Optimized Layout
Jan 2005 39Agrawal: Low Power Design
Layouts of C7552 (0.25Layouts of C7552 (0.25 CMOS)CMOS)
c7552 Un-optimizedGate Count = 3827
Transistor Count ≈ 40,000
Critical Delay = 2.15 ns
Area = 710 x 710 um2
c7552 optimized (ub = 10)Gate Count = 3828
Transistor Count ≈ 45,000
Critical Delay = 2.15 ns
Area = 760 x 760 um2(1.14)
Jan 2005 40Agrawal: Low Power Design
Instantaneous Power Instantaneous Power SavingsSavings
Peak Power Savings = 68%Peak Power Savings = 68%
Jan 2005 41Agrawal: Low Power Design
Patents and Patents and DissertationsDissertations PatentsPatents
V. D. Agrawal, “Low Power Circuits Through Hazard V. D. Agrawal, “Low Power Circuits Through Hazard Pulse Suppression,” U.S. Patent 5,983,007, November Pulse Suppression,” U.S. Patent 5,983,007, November 1999.1999.
T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic and Its Application to Low Power Delay CMOS Logic and Its Application to Low Power Design,” to be submitted to USPTO through Rutgers Design,” to be submitted to USPTO through Rutgers Univ., May 2004.Univ., May 2004.
DissertationsDissertations T. Raja, T. Raja, Minimum Dynamic Power Design of CMOS Minimum Dynamic Power Design of CMOS
Circuits using a Reduced Constraint Set Linear Program,Circuits using a Reduced Constraint Set Linear Program, MS Thesis, Dept. of ECE, Rutgers University,MS Thesis, Dept. of ECE, Rutgers University, May 2002.May 2002.
T. Raja, T. Raja, Minimum Dynamic Power CMOS Design with Minimum Dynamic Power CMOS Design with Variable Input Delay LogicVariable Input Delay Logic , , PhD Thesis, Dept. of ECE, PhD Thesis, Dept. of ECE, Rutgers University,Rutgers University, May 2004.May 2004.
S. Uppalapati, S. Uppalapati, Low Power Design of Standard Cell Digital Low Power Design of Standard Cell Digital VLSI Circuits, VLSI Circuits, MS. Thesis, Dept. of ECE, Rutgers MS. Thesis, Dept. of ECE, Rutgers University,University, October 2004.October 2004.
Jan 2005 42Agrawal: Low Power Design
PapersPapers V. D. Agrawal, “Low-Power Design by Hazard Filtering,” V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. Proc.
10th Int. Conf. VLSI Design10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197., Jan. 1997, pp. 193-197. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R.
Ramadoss, “Digital Circuit Design for Minimum Transient Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Energy and a Linear Programming Method,” Proc. 12th Int. Proc. 12th Int. Conf. VLSI DesignConf. VLSI Design, Jan. 1999, pp. 434-439., Jan. 1999, pp. 434-439.
T. Raja, V. D. Agrawal, and M. L. Bushnell, “Minimum Dynamic T. Raja, V. D. Agrawal, and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Linear Program,” Proc. 16th Int. Conf. VLSI DesignProc. 16th Int. Conf. VLSI Design, Jan. 2003, , Jan. 2003, pp. 527-532.pp. 527-532.
T. Raja, V. D. Agrawal, and M. L. Bushnell, “CMOS Circuit T. Raja, V. D. Agrawal, and M. L. Bushnell, “CMOS Circuit Design for Minimum Dynamic Power and Highest Speed,” Design for Minimum Dynamic Power and Highest Speed,” Proc. 17th Int. Conf. VLSI DesignProc. 17th Int. Conf. VLSI Design, Jan. 2004, pp. 1035-1040., Jan. 2004, pp. 1035-1040.
T. Raja, V. D. Agrawal, and M. L. Bushnell, “Variable Input T. Raja, V. D. Agrawal, and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Delay CMOS Logic for Low Power Design,” Proc. 18th Int. Proc. 18th Int. Conf. VLSI DesignConf. VLSI Design, Jan. 2005, pp. 368-374., Jan. 2005, pp. 368-374.
Jan 2005 43Agrawal: Low Power Design
ConclusionConclusion Main idea: Minimum dynamic power high speed circuits can be Main idea: Minimum dynamic power high speed circuits can be
designed if gates with variable input delays are used.designed if gates with variable input delays are used.
The new design suppresses all glitches without any delay The new design suppresses all glitches without any delay
buffers.buffers.
Decreases power without loss in speed and very little increase Decreases power without loss in speed and very little increase
in area.in area.
Developed a linear program solution to demonstrate the idea.Developed a linear program solution to demonstrate the idea.
Developed new gate design for transistor level implementation.Developed new gate design for transistor level implementation.
Results have been verified by physical layout design of large Results have been verified by physical layout design of large
circuits.circuits.
Results show average power savings up to 58%.Results show average power savings up to 58%.
Technique easily scalable for large circuits.Technique easily scalable for large circuits.
Leakage power remains a concern – ongoing research.Leakage power remains a concern – ongoing research.