critical aspects of · scaling, in which the space transformation from fine-featured silicon...

IntroductionA brief look at the evolution of micro-

processor packaging1 shows that packaginghas evolved from being a simple protectiveenclosure to a sophisticated performance-enabler. Packaging has a few key functionsand associated challenges that include thefollowing considerations:� Packaging provides a physical geometricscaling capability of approximately 5–10�,from small-dimension die-level inter-

connects to the more global motherboard-level interconnects. As silicon featurescontinue to shrink to increase functionality,there are increasing challenges for packagearchitecture to provide manufacturableoptions that continue to enable physicalscaling.� Packaging protects the fairly delicatesilicon from the external environment. Thethermomechanical integrity of the silicon

package assembly must be ensured throughcareful selection of materials and geome-tries as well as through a thorough under-standing of the environmental conditionsthat the assembly is expected to survive.2The focus of this article is on the thermo-mechanical integrity of packages. The readeris directed to an additional reference fordiscussions on environmental conditions.2� Packaging facilitates delivery of powerto silicon. The traditional approach to powerdelivery has been to incrementally optimizethe electrical pathway from the powersource on the motherboard to the silicon.However, there is a growing realizationthat in addition to these incremental im-provement challenges, a restructuring ofthe delivery path may be required. Resis-tive power losses and the ensuing heat dis-sipation are also of concern to package andsystem architects. The package inherentlyproduces electrical parasitics (unwantedresistance, capacitance, and conductance)that must be managed and minimized.� Packaging facilitates thermal manage-ment. Increasing device power is concomi-tant with increasing performance. The goalof thermal management for microproc-essors, as with other devices, is to ensurethat the on-die temperature is maintainedat or below certain limits imposed for per-formance or reliability reasons. The needto maintain device temperatures whilemanaging the increasing power has led tosome interesting technical challenges incooling-technology development.

A combination of decreasing pitch,environmental concerns (e.g., Pb- andhalogen-free materials), mechanical-stressconcerns (e.g., for the mechanical integrityof fragile low-dielectric-constant materials),electrical requirements (e.g., current den-sity), and cost constraints is driving thedevelopment of solder bump and under-fill materials technology in an entirely newdirection. Furthermore, there is a need todevelop integrable thermal-interface ma-terials (TIMs) that will facilitate properthermal management by reducing ther-mal resistance.

Power DeliveryThe ever-increasing microprocessor per-

formance levels have been accompaniedby higher transistor counts and the fasterswitching frequencies of these transistors.While process improvements and feature-size reductions result in reduced transistor-related capacitive and resistive parasiticelements, the overall power demand ofthe microprocessor has continued to in-crease from one technology generation tothe next. The higher current levels requiresignificant reductions in the parasitic re-sistive and inductive elements of the de-

MRS BULLETIN/JANUARY 2003 21

Critical Aspects ofHigh-PerformanceMicroprocessorPackaging

Vasudeva P. Atluri, Ravi V. Mahajan,Priyavadan R. Patel, Debendra Mallik,

John Tang, Vijay S.Wakharkar,Gregory M. Chrysler, Chia-Pin Chiu,

Gaurang N. Choksi, and Ram S.Viswanath

AbstractHistorically, the primary function of microprocessor packaging has been to facilitate

electrical connectivity of the complex and intricate silicon microprocessor chips to theprinted circuit board while providing protection to the chips from the external environment.However, as microprocessor performance continues to follow Moore’s law, the packagehas evolved from a simple protective enclosure to a key enabler of performance.Theart and science of semiconductor packaging has advanced radically over the past fewdecades as faster and more powerful microprocessors with tens of millions of transistorscontinue to be available, which require more signal and power input/output connectionsas well as greater power-dissipation capabilities. Key drivers for the development ofpackaging technologies include power delivery, thermal management, and interconnectscaling, in which the space transformation from fine-featured silicon interconnects to therelatively coarse features seen on motherboards has to be enabled by the package.These drivers, under constant market-driven cost pressure, have led to increaseddemands on new materials and new package architectures to enable siliconperformance. Significant advances have already been made in the areas of heatdissipation, power delivery, high-speed signaling, and high-density interconnects. It isexpected that the future evolution of microprocessors will be increasingly challenging inthese areas.This article focuses on providing a broad perspective view of the evolutionof microprocessor packaging and discusses future challenges.

Keywords: assembly, microelectronics packaging and integration, interconnects,International Technology Roadmap for Semiconductors (ITRS).

www.mrs.org/publications/bulletin

livery system in order to reduce the lossin voltage level across the logic circuits.Without an adequate voltage supply, thetransistors are not able to switch quickly athigher frequencies, which is one of thecritical means of achieving the high com-puting performance of the microprocessor.At high voltage levels, transistor gate reli-ability and high power dissipation areconcerns.

Power-Delivery TrendsMoore’s law predicts the doubling of

transistor count on microprocessors every18 months or so, as shown in Figure 1.3 Itis expected that by the end of the decade,manufacturing processes will allow thefabrication of about 1 billion transistors ona single microprocessor die. This doublingof on-die integrated transistors with eachnew process generation is a direct result ofimproved fabrication capabilities. Power-demand trends for Intel microprocessors,shown in Figure 2, indicate that power de-mand doubles every �36 months, if left togrow in an unconstrained manner.4 Thus,there is a need to examine power-deliveryissues associated with these trends.

Power-Delivery System Stackand Building Blocks

The challenge of delivering power effi-ciently and cost-effectively to the micro-processor chip through the currentpower-delivery stack is being pushed toits limits. The biggest challenge is meetingthe dc average steady-state current demandwith minimal power losses in the deliverypath. The power-loss minimization ismainly achieved through improved voltageregulator module (VRM) dc–dc power-conversion efficiency and through mini-mizing the undesired electrical-resistanceparasitics. Figure 3a shows a typical micro-processor power-delivery system, fromthe motherboard to the central processingunit die (load),5 and the related compo-nents and resistances (Figure 3b). Thesecomponents are collectively referred to asthe power-delivery building blocks. Themajor building blocks consist of the power-supply converter (110-V ac to 12-V or otherdc voltage), the VRM, the motherboard,the socket, the package, and the die. Thehierarchical nature and topological place-ment of these building blocks are criticalto the performance and efficiency of thetotal power-delivery system.

Typical Power DeliveryThe power-delivery system first con-

verts the standard 110-V ac voltage to adc voltage of 48 V or 12 V. This dc voltageis further converted and regulated to even

lower voltages by the VRM (between 1 Vand 2 V) and distributed to the CPU. Thedistribution of this lower dc voltage to theCPU can be accomplished through one oftwo ways:1. VRM–motherboard–socket–packagepath: This distribution delivery path in-volves routing through the motherboardpower layers, the socket power pins (cop-per or an alloy), the package power layers(copper) and C4 (controlled collapse chipconnection) tin–lead or lead-free solderbumps, and finally to the load (CPU die).2. VRM–package path: This distributiondelivery path involves routing the dc powerthrough a power-pod module that thenroutes the power through a special con-nector onto the package power layers andthrough the same package distribution

layers up to the CPU die as described inPath 1.

Figure 4 shows the two alternate power-delivery paths for the converted dc volt-ages to the CPU die. Typical desktopcomputer systems route power throughthe motherboard–socket–package system.Other key components of the power-delivery network are discrete power-decoupling capacitors and the VRM.Figure 5 shows the overall hierarchicalpower-delivery path from the VRM all theway to the CPU die through the mother-board route.

Power-Delivery ChallengesThe power-delivery performance of the

system is measured in ways such as thedc voltage drop, the power-conversion

22 MRS BULLETIN/JANUARY 2003

Critical Aspects of High-Performance Microprocessor Packaging

Figure 1. Illustration of Moore’s law.3 Pentium is a registered trademark of Intel Corporation.

Figure 2. Historical and projected power-demand trends for Intel microprocessors.4

efficiency, the heat dissipation, and thetransient response to changing dynamicpower loads. One of the most challengingof these is to meet the dc delivery require-

ments of minimizing the voltage dropthrough the package-level interconnectresistance and maximizing the current-carrying capability of the delivery path.

There are numerous constraints andchallenges that need to be overcome in orderto improve the dc power delivery. Some ofthe ways to address this challenge areimproving VRM component technology,optimizing the physical placement of theVRM, reducing the electrical parasitics inthe interconnect delivery path, improvingmaterials properties to handle the higherheat-dissipation levels, reducing the formfactor (physical size), meeting the printedcircuit board (PCB) space constraints, anddeveloping better passives such as de-coupling capacitors.

Lower Parasitic ResistanceAs the transistor count has continued to

increase from one generation to another,so has the demand for power-supply cur-rents. One way that the overall power-consumption demand was managed inthe past was to lower the microprocessorvoltages, from �3.3 V to �1 V. While thisapproach has kept the overall power levelsreasonable, it has significantly increasedthe current levels. Today’s microprocessorsupply-current demands are approachingbetween 100 A and 150 A. At today’s resis-tance levels of several milliohms, the powerlost in the delivery system due to resis-tance is fast approaching 5–15 W. This lossof power is converted to thermal energythat results in an increase in the operating-temperature conditions of the various com-ponents and affects the materials propertiesof components such as plastics, passives,and PCBs (including package substrates).In addition, the reliability of these compo-nents is also being affected as the maximumoperating temperatures are exceeded.Therefore, every effort must be made toreduce the electrical parasitic resistance ofeach of the power-delivery building-blockelements.

The electrical resistance is a functionof the materials properties and physicalgeometry of the various power layers inthe motherboard and package substratesas well as the number of socket pins.Copper and its alloys are widely used intoday’s microprocessor power-deliverybuilding blocks. Figure 6 shows the drasticreduction in resistance required for thenext generation of high-performance micro-processors. As can be seen in the graph,future power-delivery demands will requirea greater than 5� reduction in impedance.Significant reductions in VRM-related im-pedance would require the developmentof MOSFETs (metal oxide semiconductorfield-effect transistors) with lower turn-onresistances. Motherboard resistance reduc-tion requires the use of very thick copperpower layers, adding to the cost andmanufacturing challenges. Reductions in



Figure 3. (a) Motherboard-to-CPU (central processing unit) power-delivery system.5

Tx � transistor. (b) Power-delivery system building blocks and resistance.

Figure 4. Illustration of alternate power-delivery paths. PSU is power-supply unit; VRM isvoltage regulator module.

Figure 5. Illustration of the overall hierarchical power-delivery system path.

package resistance are achieved by in-creasing the thickness of the power layers(typically made of copper), leading tomanufacturing constraints and highercosts. Using pin materials with low resis-tivity or increasing the number of power-delivery pins helps reduce the socketresistance. However, given that the socketpin material is already optimized for boththe electrical resistance as well as pin stiff-ness, the only viable way to further reducethe socket resistance is to increase thenumber of pins. Today’s microprocessorsockets are fast approaching the practicalmanufacturing limitations of high-pin-count sockets. While these incrementaloptions are being pursued, they offer di-minishing gains going forward.

An alternate approach is to redesign thepower-delivery system. For example, onecould bring in additional power-deliverypathways, move the VRM closer to the CPU(bypassing the motherboard and socketblocks completely), or split the VRM mod-ule (move some VRM functions to thepackage). These options help reduce theresistance stack by eliminating componentsfrom the critical power-delivery pathway.The optimum solution would be to inte-grate the VRM components directly intothe CPU itself or within the package toeliminate most of the resistive elements.

Improved ComponentsAnother way to reduce the parasitics is

to improve the various components usedin the conversion and delivery paths. Bet-ter power MOSFETs with lower turn-onresistances are critical for the VRM tech-nology. Moving to higher and higher VRMswitching frequencies helps significantlyreduce the inductance and capacitance re-quired. As shown in the photograph labeled“multiphase” in Figure 7, the smallerphysical size of the VRM components re-sults in a compact design. This enables thepotential for integrating the VRM modulewith the package substrate itself, therebyeliminating the motherboard and socketparasitics. Almost half of today’s CPU

power-delivery BOM (bill of materials) ismade up of motherboard and package-level decoupling capacitors. It is importantto develop new capacitor materials andprocesses that lead to the development ofhigh-density, high-capacitance capacitorsoptimized for power-delivery decoupling.

Thermal ManagementAs mentioned earlier, microprocessor

development over the past few decadeshas faithfully tracked Moore’s law, result-ing in continually increasing performance.One consequence of increasing perform-ance is that microprocessors tend to dissi-pate higher amounts of power, as shownin Figure 8, posing greater challenges forthermal management. In this section, thespecifics of thermal-management chal-lenges are discussed.

The Thermal-Management ProblemThe goal of thermal management is to

develop solutions that maintain silicon ator below certain temperatures dictated by

reliability and performance considerations.Thermal-management solutions essentiallytransfer heat from the silicon to the externalenvironment. The concept of thermal resis-tance has been commonly used to describethermal requirements and define solutioncapabilities. Equation 1 describes the re-quirement that a thermal-managementsolution must satisfy:

Rreq � (Tj � Ta)/TDP, (1)

where Rreq is the required thermal resis-tance of the solution, Tj is the silicon tem-perature (i.e., junction temperature, typicallymeasured using an on-die temperature sen-sor), Ta is the ambient temperature, and TDP(thermal-design power) is the target power-dissipation requirement of the coolingsolution. In most applications, the TDP isassumed to be a steady-state entity. Thisis a fairly good assumption for most end-user conditions where a thermal solutiontypically enables continual operation. Theonly situation where transient effects areconsidered (i.e., in the design of thermalsolutions during the test process) is be-yond the scope of this article.

Let us examine each term in Equation 1in some detail. Tj is typically determinedfrom reliability and performance consid-erations. In a very general sense, decreas-ing Tj will result in increased performanceand improved silicon reliability due toreduced leakage and electromigration ef-fects. In general, Tj can be reasonably ex-pected to trend lower over time. Otherfactors such as microprocessor architectureand process and design maturity also in-fluence Tj trends.



Figure 6. Power-impedance reductiontrends from 2002 to 2010, showingthe drastic reduction in resistancerequired for the next generation ofhigh-performance microprocessors. Figure 7. Reducing the VRM size.

Figure 8. Microprocessor power trends (TDP is thermal-design power) as a function offrequency for desktop applications.The blue symbols represent Pentium and Pentium II, thered triangles Pentium III, and the solid red diamonds Pentium 4 processors.

Ta in Equation 1 is the ambient temper-ature at the point of heat dissipation. Inmost thermal-management solutions indesktop and server applications (see Fig-ure 9 for a typical example), a heatsinkis attached to the package, and the entirecooling solution is local to the micro-processor. The heat from the micro-processor is channeled through the packageand heatsink and is dissipated to theheatsink inside the computer chassis.Hence, the temperature inside the box,local to the heatsink, must be consideredin assessing the magnitude of the thermal-management task. In general, the air localto the heatsink will be preheated, due tothe presence of other hot components inthe box. Thus, the local ambient is higherthan the external ambient. The amountof heating—and hence the temperaturedifference—between the internal and ex-ternal ambient temperatures critically de-pends on the design of the box and themanner in which air is made accessible tothe heatsink. This temperature differencecan be as much as 10–15�C in some systemdesigns. In mobile systems such as lap-tops, a heat pipe is often used to transportheat efficiently away from the micro-processor to remote locations where theheat exchange occurs, as shown in Fig-ure 10. In this case, the influence of heat-ing inside the laptop on heat-pipe andremote heat-exchanger performance mustbe understood during the thermal design.Based on this discussion, it can be con-cluded that the term Tj � Ta will, in gen-eral, decrease over time.

The evolution of TDP as a function ofmicroprocessor frequency (Figure 8) showsthat despite the power savings typicallyobtained as a result of silicon technology-generation transitions, the general trend is

toward increasing power. A similar trendis predicted in the International Technol-ogy Roadmap for Semiconductors (ITRS).6Given the trends in Tj � Ta and TDP, it isreasonable to expect that Rreq will continueto decrease with time, and the thermal-management challenge will be to producesolutions of lower resistance.

Another factor that exacerbates thethermal-management challenge is thepresence of local die regions of increasedpower density on the microprocessor, asshown in Figure 11. These regions are oftenreferred to as hot spots and representareas on the die that have higher levels ofactivity. Hot spots are problematic becausethe design demand on the thermal solu-tion is to sufficiently cool them and thusensure reliability and performance. Theneed to cool hot spots often drives athermal-solution over-design as far as other

regions of the die are concerned. The im-pact on the cooling capability of differentsolutions is discussed in the next section.

Thermal-Solution StrategiesIn general, two thermal-solution archi-

tectures, shown in Figure 12, can be definedfor a microprocessor package that usesflip-chip (C4) interconnects between thedie and package.4 In packages that use C4interconnects, heat transfer from the activeside of the die is impeded by the highthermal resistance from the underfill ma-terials. The primary heat-transfer path insuch a package is through the silicon bulkand then the inactive side of the die. In Ar-chitecture I, a heatsink directly interfaceswith the inactive (back) side of the die;in Architecture II, the heatsink interfaceswith an integrated heat spreader (IHS).From the perspective of a thermal engi-neering purist, there is no difference be-tween the two architectures, except thatthe heat-spreading function is implicit, orbuilt-in, in Architecture I and explicit, or aseparate part, in Architecture II. Given this,we will use Architecture II, for the mostpart, to explain thermal-management de-sign considerations.

The general strategy for thermal man-agement should focus on minimizing thetemperatures of local hot spots caused bydie-level power non-uniformity, increas-ing the power-dissipation capability ofthe thermal solutions, and expanding thethermal envelopes of systems. In general,there is an increasing realization thatmicroprocessor architectures should bedesigned to produce as uniform a powerdistribution as possible. In parallel, thethermal engineering community mustfocus on increasing the power-handlingenvelope by developing cost-effective,high-performance thermal solutions.



Figure 9. Example of a thermal-management solution for a typicaldesktop or server application.

Figure 10. Schematic illustration of the remote heat-exchanger concept in typical laptopapplications.TIM � thermal interface material.

Figure 11. On-die power distributionfor a typical microprocessor. Areas inyellow to red are regions with increasedpower density (hot spots).

The heat-transfer issues are schemati-cally illustrated in Figure 13. Heat gener-ated at the device is mostly conductedthrough the thickness in the first TIM(TIM1) located between the die and theheat spreader with a minimal amount ofspreading. The focus in optimizing TIM1thermal performance is to minimize ther-mal resistance, resulting in a lower tem-perature drop across the thermal interface.A lower temperature drop here allows forhigher temperature drops across othercomponents without affecting the overallthermal budget. This is accomplished bymanaging three parameters: (a) the in-trinsic thermal conductivity of the TIM;(b) the thermal contact resistance of thedie/TIM1 and TIM1/IHS interfaces; and(c) the thermal-interface thickness, also re-ferred to as the bond-line thickness.

At the IHS level, the heat spreads andsome of the peaks in the power profile aresmoothed out. The considerations in de-signing the IHS, then, are to optimize twofactors: the thermal conductivity of theIHS material and the thickness of the IHS.

It is common knowledge that thermal-management solutions will perform betterif the source of heat being cooled is uni-formly spread. To help quantify this per-formance, a density factor (DF) that isindependent of the power profile on the diehas been proposed.7 The DF is simply theratio of the actual thermal resistance at thehottest spot to the die-area-normalizeduniform power resistance or thermalimpedance, and has the units of inversearea A�1. Two very different power pro-files could actually result in the same DF,and would therefore result in equal thermal-management challenges. On the otherhand, slight changes in power profilescould result in very different DFs , includ-ing very different challenges in thermalmanagement. This factor can help in as-sessing different cooling schemes withoutthe need to understand specifically theon-die power distribution. An example ofthe use of this factor is shown in Figure 14.

Heat is next transported between theIHS and the heatsink through anotherTIM (TIM2). TIM2 is designed with con-siderations similar to TIM1. Due to theexcellent heat-spreading on the heatsinkbase, the heat fins see a more uniform gra-dient as compared with the IHS, and theheatsink has the primary function ofducting heat to the environment. In typi-cal desktop computer applications, natu-ral or forced convection of air through finson the heatsink is used to transfer heat tothe local ambient. Heatsink design consid-erations include (a) thermal performancethat is optimized given the airflow andpressure drop available, and (b) ensuringthe “fit” within the computer system interms of volume and weight.

Finally, there is a need to ensure thatsystem layouts are optimized for thermal

performance. This factor has become es-pecially important because of the growingdemand for smaller and quieter computersystems. If system layouts are optimizedfor thermal performance so that the airflowing through the computer does notpass over a hot component before reach-ing the microprocessor, the preheating ofair can be minimized. Also, better ventila-tion and exhaust will lead to better utiliza-tion of fans and heatsink capability.

In addition to the general technical chal-lenges, the thermal engineer must alsobe aware of business considerations andconstraints such as cost, time-to-market,and extendibility of thermal solutions formultiple process generations and marketsegments.

Interconnect TechnologyPackage design integrates all of the

elements in a manner that enables thepackage to be a cost-effective platform formanaging the physical, thermal, electrical,and mechanical demands of high-performance microprocessors. This is inaddition to providing the basic functionsof a space transformer and protectiveenclosure for the silicon die. The packagearchitecture is expected to continue toundergo major changes in order to enablehigh-performance and low-cost system-level solutions in a given business model.In the following sections, we discuss thehistory, current status, and challenges inthe physical design of high-performancemicroprocessor packages.

Die-to-Package InterconnectionWire bonding had been the technology

of choice for die-to-package interconnec-tion over a long period of time because ofits low cost. This method forces all of theterminals on the die to the periphery sothat very fine wires can connect these ter-minals to corresponding ones on the pack-age. In recent years, wire bonding has faced



Figure 12. Schematic illustration of the two thermal-solution architectures: (a) Architecture I,typically used in laptop applications; and (b) Architecture II, typically used in desktop andserver applications. (1) heatsink, (2) TIM2 (thermal-interface material over the integratedheat spreader), (3) integrated heat spreader (IHS), (4) TIM1 (thermal-interface materialover the die), (5) die, (6) underfill, and (7) substrate.

Figure 13. Schematic illustration of theneed to spread hot spots. Red arrowsshow the direction of heat flow; thelight-blue arrow indicates a hot spot.The heat spreader significantly reducesthe heat flux near the hot spot.

Figure 14. Cooling capability versusdensity factor (DF) for a typical desktopapplication. Increasing DF reducescooling capability.

many roadblocks for microprocessor ap-plications. The large increase in terminalcount and the need for low resistance aswell as a low inductance path to the cir-cuits on the silicon have made this periph-eral placement of terminals difficult fromboth cost and performance standpoints.This has led to the re-emergence of an oldconcept, flip-chip bonding, as shown inFigure 15, as the de facto interconnectstandard for high-performance micro-processor packaging in the last few years.Compared to wire bonding, flip-chipbonding provides a higher density of inter-connects, due to area-array placement ofthe die terminals, and superior electricalcharacteristics, due to the short inter-connect length, as well as the ability todeliver operating voltage much closer towhere it is needed by the circuits. The flip-chip interconnect is also more suitable inaccommodating the interconnect densityscaling required by performance demands.Unlike wire bonding, which is typicallydone one bond at a time, the number ofconnections between die and packagelargely does not impact the cost of flip-chip bonding, which is typically a massbump-formation and joining process. How-ever, the continued need for a reductionin the terminal pitch (distance betweenterminals) and for the individual inter-connects to carry a higher and higheramount of current demands innovation inmaterials and process development. Ex-amples include the ability to bump thepackage substrate at and significantlybelow a pitch of 120 �m, the ability tomaintain coplanarity or flatness of thebump topology, and the use of environ-mentally friendly materials compatiblewith process-temperature needs.6 One ex-ample of a potential package-architecture-level solution is bumpless build-up layer(BBUL) processing, which replaces tradi-tional bumping by microvia connectionsbetween silicon and package.8 BBUL proc-essing can approach silicon-level terminaldensities.

Package-to-MotherboardInterconnection

A microprocessor package, like any otherintegrated-circuit (IC) package, serves oneof the most basic functions of enabling acost-effective space transformation of thefine-pitch terminals on the die to a looserpitch of receiving terminals on electronicsystem boards. The system board (i.e., themotherboard or PCB) is generally at leastone order of magnitude larger than thesize of a current microprocessor packagein linear dimensions (i.e., two orders ofmagnitude larger in area). Without thepackage, the motherboard would need tocontain the fine features (linewidths, spac-ing, via pads, etc.) required by a smallmicroprocessor chip with thousands of in-terconnections. This would drive the costof the system significantly higher, raisingconcern about the cost related to yieldissues of individual components on theboard. The package typically provides aone order of magnitude increase in theinterconnect pitch, lowering the systemcost. There are two types of interconnectionbetween a packaged component and themotherboard: (1) direct mounting, typi-cally by solder-attachment of the packageterminals to the surface of the PCB; and(2) socket mounting, where the packagedcomponent is inserted into a socket, whichin turn is directly mounted onto the PCB.Direct-mounted components are typicallysolder-attached to the motherboard simul-taneously and are difficult to remove andreplace. Socket-mounted components areeasily attached at any time and are easilyreplaceable. Unlike almost all other typesof IC components, a significant majority ofhigh-performance microprocessors con-tinue to be socket-mounted, driven bymultiple business considerations relatedto the cost of the system. This trend isexpected to continue. A smaller portionof microprocessors are directly surface-mounted onto the PCB, generally wherethe physical size of the system is verysmall (as in highly mobile systems likecellular telephones and PDAs).

From the 1980s through the mid-1990s,direct-mounted microprocessor packagescame in the form of quad flat packs (QFPs)and later in tape-carrier packages (TCPs)with leads on all four sides of the package.These leads were surface-mounted to themotherboard by tin–lead solder. Then thepackages migrated to the ball grid array(BGA) format, where tin–lead solderspheres were placed on a grid pattern onthe underside of the package surface. Thearea-array placement achieved a higherdensity of terminals, even with a looserterminal pitch, when compared with theperipheral placement of QFPs and TCPs.

The future trend for surface-mountedmicroprocessors primarily lies in scalingthe ball pitch down. A shrinking ball pitchin turn will require thinner solder pastesapplied to the motherboard, reducing theability of the surface-mounting process toaccommodate the lack of coplanarity ofthe ball field. So, it is critical to find mate-rials and process means to improve theflatness of the packages. The future needfor lead-free solder-ball material and asso-ciated process changes must also be takeninto account. The selection of finish ma-terials for the package terminals is im-portant in order to provide mechanicalstrength at the solder-ball and package-pad interface; this is especially importantfor small-diameter, lower-joint-height,lead-free materials.

Socket-mounted microprocessors gen-erally came in the form of pin grid arrays.The pin pitch has decreased over timefrom 2.540 mm to 1.796 mm and most re-cently to 1.270 mm. With the decrease inpin pitch, pin diameter has also shrunk to300 �m. In addition, the traditional Kovarmaterial has been replaced by copper tosatisfy the demand for low resistance, asdiscussed earlier. These small dimensionsmake the pins fragile, thus requiring spe-cial care in manufacturing. Also, the physi-cal socket space to hold each pin for goodelectrical contact would make further de-creases in pin pitch cost-prohibitive. Thiswould likely lead to the land grid array(LGA) type of package, which is morepitch-scalable and can eliminate the needfor the fragile pins. Very-fine-pitch lands(metal pads on the bottom of the package)enable a large number of contacts for thepackage. In order to keep the total force toa reasonable value and still provide lowcontact resistance, developments in thefinish materials for both the package landsand socket contacts are needed.

Substrate TechnologyCeramic substrates dominated micro-

processor packaging from the birth ofmicroprocessors in the early 1970s untilthe last few years. Some of the key driversfor ceramics were the need for hermeticpackaging reliability, then effective power-delivery metal layers, and later flip-chipdemands for matching coefficients of ther-mal expansion (CTEs) between the die andsubstrate. However, ceramic substrates suf-fered from many disadvantages, includ-ing (a) low conductivity of the conductormaterial (W or Mo) affecting the powerdelivery—that is, voltage loss (current–resistance, IR, drop) and power loss (I2Rloss) with ever-increasing supply-currentvalues; (b) high dielectric constants affectingthe high-speed signal-transfer performance;



Figure 15. Schematic illustration ofsilicon flip-chip bonding on an organicsubstrate.

(c) feature-size limitation to accommodatethe finer line/space/via sizes demandedby high bump densities as well as large,thin packages needed for space-constrainedapplications; and (d) CTE mismatches withthe motherboard for surface-mounted ap-plications. In the mid-1990s, Intel pioneeredthe transition from ceramic to organic sub-strates for high-volume, high-performancemicroprocessors. Figure 16 illustrates theevolution of organic substrates for variousIntel microprocessor generations.

Organic substrates provide better per-formance at a lower cost and have evolvedto be the substrate of choice for micro-processor packaging. They leverage thewell-established fiberglass-based PCB in-dustry infrastructure. Copper conductorsin much thicker dimensions and finerpatterns are easily incorporated into thesesubstrates. This enables package designsthat provide both low-inductance andlow-resistance paths through the package.Higher-density signal routing is alsomade feasible by the beneficial combina-tions of a low-dielectric-constant material,a thin dielectric, and the finer linewidthand spacing capabilities provided by theorganic substrates. However, the advan-tages of dimensional stability and lowerCTEs of the ceramic packages are lost andhave to be managed through other means.One method to improve dimensional andmechanical stability is the addition of athick organic core. While the higher CTEsof organic substrates help the package-to-motherboard interconnect, the die–packageinterface is managed through the properchoice of underfill material as well as goodcoordination between the silicon andpackage development. Looking forward,there are significant challenges to be con-sidered in substrate materials and proc-esses as well as in the package architectureitself. As future microprocessors continuescaling in feature and performance, sig-

nificant challenges are imposed on theperformance and cost of the substratetechnology. Some of the key requirementsfor the development of a new class ofnext-generation substrate materials aredescribed in the following sections.4

Reduced Stress on the DieIt is expected that materials with lower

and lower dielectric constants will be im-plemented for the interlayer dielectrics(ILDs) on silicon. These materials tend tobecome increasingly fragile with the re-duction in dielectric constants. Also, thesize of the die is expected to increase sig-nificantly over time. Other considerationsinclude the eventual implementation ofPb- and halogen-free materials on the dieand in the package. This in turn could po-tentially reduce the stress on the die sincePb and halogen compositions generallyhave higher melting temperatures, result-ing in higher thermomechanical stress. Itis critical, therefore, to have a substratematerial that mitigates the stress impacton silicon while maintaining the thermo-mechanical reliability of the total system.

Feature-Size ReductionThe reductions in interconnect linewidth,

line spacing, microvia diameter, capture-pad diameter, plated through-hole diame-ter, flip-chip bump pad pitch, and flip-chippad solder-mask-opening diameter de-mand new processes and process materials.These include better photoresists andsolder-mask materials for higher resolution,better layer-to-layer-alignment lithographytooling and processes to reduce capture-pad size, better mechanical drillbits to drillsmaller plated through-holes, better andhigher throughput laser-drill equipmentfor smaller microvias, and better dielectricmaterials for improved metal adhesion. Fortoday’s state-of-the-art build-up processes,the linewidth and spacing are �25 �m

and the bump pitch is �200 �m. In aboutfive years, the requirement will be sub-stantially smaller. Figure 17 illustrates across section of state-of-the-art microviatechnology (65-�m diameter).

Increased Electrical PerformanceIn order to meet the requirements of

future high-speed signal transmissionfrom the microprocessors to the periph-eral components, new substrate dielectricmaterials and process controls are needed.The new materials are expected to havelow dielectric constants and low loss tan-gents (low energy loss in the dielectricmaterial when a high-frequency signalis transmitted through a conductor incontact with the dielectric). In addition,impedance-matching and impedance con-trol are critical for high-speed signals.Impedance control is a direct effect of di-electric thickness and linewidth tolerance;therefore, the control of linewidth and thetightening of tolerance are important pa-rameters for future manufacturing proc-esses. Improved processes and materialsare also needed to reduce dielectric rough-ness while maintaining adhesion betweenthe dielectric and copper lines in the sub-strate. The next-generation substrateswould also require lower electrical resis-tance to enable higher amounts of currentthrough them.

Increased Mechanical LoadingDue to the increase in performance re-

quirements, the power dissipation offuture-generation microprocessors is rap-idly increasing. As a result, larger andheavier heatsinks are employed to cool themicroprocessor. In order to maintain inti-mate contact between the heatsink andpackage, a TIM is introduced betweenthem. The two are then clamped so that



Figure 16. Evolution of organic substrate technology for various Intel microprocessors. In theplastic pin grid array and the flip-chip pin grid array, the substrate is 49.5 mm across and thesilicon is 10 mm. In the second-generation pin grid array, the substrate is 35 mm across andthe silicon is 10 mm.

Figure 17. Cross-sectional view ofstate-of-the-art microvia technologyused in organic packaging (microviadiameter: 65 �m).

the TIM is as thin as possible. This leads tofairly large static and dynamic loads onthe package. In addition, the predicted mi-gration to LGA sockets implies thatpotentially higher static loading will beapplied to the substrate. The substrate hasto withstand all of these mechanical loadsthroughout the life of the device.

Lower CostIf price was of no concern, then it would

not be difficult to custom-tailor a substratetechnology to meet all the needs statedhere. However, the reality of market pres-sures requires that substrate costs must below enough to ensure competitiveness inthe marketplace. This puts limits on theextent of technology features that can beutilized.

Packaging MaterialsFuture microprocessor marketing needs

demand cost-effective packaging solu-tions and are challenging the develop-ment of breakthrough materials. In thissection, the discussion will focus on thechallenges related to TIMs and underfillmaterials.

Thermal Materials TechnologyIn the context of heat removal for

microprocessor packaging, the followingtwo generic architectures have already beendefined (see the previous section on“Thermal Solution Strategies”):� Architecture I: Typically dealing withlow-power (�30 W) microprocessors ormicroprocessors used in height-constrainedapplications where the die is directly at-tached to the heatsink or a heat pipe; and� Architecture II: Typically dealing withmedium- to high-power processors (�30 W)where an IHS is used to spread the heat.

The basic implementation of Architec-tures I and II were shown in Figure 12. Ineither case, successful thermal manage-ment requires the development of a TIMthat comes in contact with the die andheatsink, as shown in Figure 12a, or thedie and the heat spreader, as shown in Fig-ure 12b. Typically, the TIMs are made upof a polymer matrix in combination withhighly thermally conductive fillers of metalor ceramic, and they can be classified asphase-change materials (PCMs), thermalgreases, gels, and so on. Performance con-siderations, as well as cost and manufac-turability concerns, inevitably result intradeoffs made during the selection of aninterface material for a given application.The attributes that are considered includechoice of polymer matrix, choice of fillers,design, manufacturability, and the reliabil-ity and cost of the total thermal solution.

Thermal Materials Technologiesfor Architecture I

Architecture I encompasses packagingsolutions for low- and medium-powermicroprocessors, which are predominantlyencountered in the mobile and low-priced(under $600) PC processor market seg-ments. As discussed earlier, the technologyinvolves interfacing the heatsink to the diethrough a compliant interface material. Thedevelopment of thermal materials tech-nologies for this application has evolvedover time and includes elastomeric thermalpads, thermal greases, and phase-changefilms (PCFs).9

Thermal Materials Technologiesfor Architecture II

Architecture II is designed to be scalableto meet the demands of medium- to high-performance (power) processors. The inte-gration of the heat spreader on the dierequired the development of a thermallyconductive polymer, a heat spreader, andan adhesive sealant. The heat spreaderhelps in improving the diffusion of heatflux from the smaller die area to a muchlarger surface area. This in turn translatesto improved thermal performance of theheatsink. This architecture precludes theuse of thermal greases due to their associ-ated thermomechanical failure mecha-nisms.9 PCMs are precluded, since they donot meet the stringent thermal-performancerequirements. In addition, the need for apositive compressive load at the interfaceimposes limitations on the design of thispackaging architecture. In order to over-come these technological issues, novelchemistries have been aggressively inves-

tigated. As a result, a new thermally con-ductive gel TIM was developed. The gelis typically a metal-filled or ceramic-particle-filled silicone polymer, and itcombines the properties of both a greaseand a cross-linked polymer.

It is expected that in order to continueon the path illustrated in Figure 18 to keepup with power requirements, it will benecessary to make significant break-throughs in thermal materials technologies.Heat dissipation through polymer TIMsoccurs through the phenomenon of perco-lation. One can also consider providingthermal solutions for heat dissipation en-tirely through conduction by utilizing TIMsmade up of metals. However, to integratethese metallic TIM technologies with thesilicon and packaging technology of choiceposes an entirely new set of challengesfrom a stress, cost, and infrastructure per-spective. An ideal case would be to de-velop a composite TIM that providesenhanced heat dissipation while balancingthe mechanical properties to minimizepackage stress. Developing these compositeTIMs can be achieved in a variety of ways,including utilizing recent developmentsin nanomaterials technologies. It is expectedthat one can develop materials with bulkthermal conductivities that are 5–10� thatof those obtained using conventionalapproaches.

Chip-to-Package-LevelInterconnect Materials

Organic flip-chip technology is becomingthe cost-effective technology for meetinghigh-pin-count/high-performance require-ments. The ITRS predicts that the input/



Figure 18. Illustration of required improvements in the thermal resistance (RTIM) of thermal-interfacematerials.These are expected to continue to pose significant challenges in the years to come.

output pitch will approach 120 �m inthe next five years and 80 �m in the next10 years.

As mentioned in the introduction, acombination of decreasing pitch, environ-mental concerns, mechanical-stress con-cerns (e.g., for low-� dielectric integrity),electrical requirements (e.g., current den-sity), manufacturability, and cost constraintsis driving the development of bump andunderfill materials technology in an en-tirely new direction. The packaging archi-tectures of relevance to underfill materialstechnology include (a) a flip-chip packagewith underfill (capillary underfill, no-flowunderfill, etc.) and (b) a mixed-stack pack-age with overmolded underfill (OMUF).These are illustrated in Figure 19.

The key function of the underfill is toredistribute the stresses and strains overthe entire die so as to maximize the inter-connect joint reliability in addition to pro-tecting the active die surface from a hostileenvironment. Typically, the underfills aremade up of a polymer matrix in combina-tion with various fillers (e.g., silica). Theattributes that are considered while devel-oping an integrated underfill solution in-clude materials properties, package designand architecture considerations (bumppitch, spacing, die size, etc.), integration(low-� dielectric, organic substrate, bumpmetallurgy, etc.), manufacturability, relia-bility, and total cost.

In the arena of mixed-stack packaging,OMUF is being investigated as a noveland alternate materials solution that willboth underfill and encapsulate the mixed-stack package in a single step, as illustratedin Figure 19b. This approach provides alow-cost path with the additional benefitof process simplification. However, thechallenges related to the development of

an OMUF material are significant. Thetechnical challenges involve (1) tailoringthe material to be 260�C-compatible for lead-free package applications; (2) improvingmaterial flow/viscosity/wettability char-acteristics to enable good underfilling;and (3) optimizing adhesion/moisture-absorption/mechanical properties suchas toughness, modulus, CTE, and glass-transition temperature in order to preventdelamination and cracking. The small, thinform factors of the package could lead tomechanical-integrity issues such as thin-die cracking due to high molding pres-sures as well as excessive warpage of theoverall thin package.10

Decreasing bump pitch and chip heightas well as increasing bump density con-tinue to push the limits of capillary-flowunderfill materials.6 To ensure the abilityto meet this demand, managing the mate-rial flow and filleting is crucial. Filleting isthe ability of the underfill materials to wetthe silicon die and form around it. Key at-tributes of the material that contribute tothe flow of the underfill on the substrateinclude the viscosity, gel time, and rheo-logical characteristics of the underfill.Typically, empirical data are collected todetermine the flow characteristics of theunderfill on various substrates. However,the availability of predictive flow-modelingtools to understand the flow behavior ofmaterials on different substrates can pro-vide a distinct advantage for materialsdevelopment.11 The typical steps involvedin an underfill process are illustrated inFigure 20.

Upon completion of the capillary flowunder the die, the underfill needs to forma fillet against the sides of the silicondie. This is crucial to eliminate the use ofan extra dispense-process step to createa fillet and helps in maximizing thethroughput and minimizing assembly

cost. An underfill fillet height of approxi-mately half or more of the die thicknessensures good performance. The fillet issimilar to a meniscus against a plane wall,as shown in Figure 21.

The capillary rising has the followingrelationship with the contact angle andsurface tension:

, (2)

where � is the contact angle, is the surfacetension, is density, g is acceleration due togravity, and H is the capillary height. Equa-tion 2 shows that the capillary height isproportional to the square root of the sur-face tension and (1 � sin�). Hence, devel-oping an underfill-material chemistrythat maximizes wetting and adhesion tothe critical interfaces—which include thesubstrate solder mask, polyimide on thesilicon, and bump metallurgy—is crucial.

Another key performance metric relatesto the ability of the underfill to withstanda variety of mechanical stresses (e.g., tem-perature cycling, shock, and vibration). Thefailure mechanisms during these stressesmanifest in the form of cracking of theunderfill, thus making bulk fracturetoughness and fatigue-resistance of theunderfill important parameters to consider.Fracture-toughness measurements predictthe ease of crack initiation, while the fatigue-crack-resistance measurements can helppredict the ease of crack propagation fol-lowing initiation. Figure 22 is an illustrationof the kind of data that can be collectedusing such measurement techniques.12

From a materials-development perspec-tive, a variety of techniques are used to en-hance the mechanical performance of theunderfill, including filler loading, tough-eners, and so on. The CTE of the underfillis critical in ensuring adequate fatigue life

H � �2�1 � sin ��g



Figure 19. Schematic illustration of(a) a flip-chip package with underfilland (b) a mixed-stack package withovermolded underfill (OMUF). Figure 20. Illustration of the typical steps involved in an underfill (UF) process.

of the underfill. Selection of the requiredmechanical properties such as modulusand CTE for an underfill material is alsoheavily dependent on the type of bump-ing material chosen. Figure 23 shows theinterdependency of the underfill viscosityand CTE as a function of the silica fillercontent in the underfill.13

A combination of factors, including thepolymer resin CTE, choice of bump metal-lurgy (Pb, Cu, Sn-Ag, etc.), filler size dis-tribution, and material viscosity rangethat can be accommodated within themanufacturing process window, will helpdetermine the optimum filler content. This

determines the base fracture toughnessand fatigue resistance of the underfill-material system. Any further improvementsto this will have to be managed throughalternative formulation approaches, in-cluding rubber-toughened systems.

However, in order to achieve a break-through, one has to look for new directionsin both polymer and filler technologiesthat can break the interdependencies shownin Figure 23. Polymer resin technologiesthat can provide fundamentally low CTEs(�35 � 10�6/�C) and low viscosity andthat can be “integrated” with the bumpingmaterials of the future will emerge as theresins of choice. Filler technologies thatcan be combined with this resin of choiceto manage the underfill CTE without af-fecting flow or bump-to-substrate inter-connect would be ideal—for example,reactive nanofiller technologies. Underfillmaterials using such technologies can pro-vide further opportunities to develop newcost-effective materials and process tech-nologies. The ideal underfill material andprocess technology of choice would be suchthat they can be scaled independently ofbump pitch and die size while being cost-effective. This would point toward usingwafer-level underfills, which involves in-tegration of the underfill process with back-end silicon processing technology. Hence,the continuing development of underfill-

materials technology in conjunction withsilicon processing technology can providehigh-performance, cost-effective solutions.The significance of the close interdepend-ency of these technologies is highlightedin the next section in the context of low-�ILD materials.

Mechanical IntegrityOne of the primary functions of the

package continues to be to provide protec-tion for the silicon against thermal andmechanical loads imposed during manu-facturing, motherboard assembly, shipping,handling, and in end-user conditions. Aconsiderable amount of literature has ac-cumulated over the years on the variousfailures that can occur within the differentelements of the package when it is sub-jected to thermal and mechanical loads.The intent of this section is not to reiterateor summarize the knowledge alreadyavailable in the literature but to focus onthe primary issues that are expected todominate in the next few years and reviewsome of the demands on the analyticaland experimental tools needed to assessthese issues.

A package is a combination of a numberof disparate materials included to satisfyspecific elements of the performance de-mand. As a result, when the package issubjected to different thermal and me-chanical loads, the intrinsic strengths ofthe materials and their properties such asCTE and Young’s modulus play a signifi-cant role in determining the robustness ofthe package. A number of trends in pack-age evolution require an increased focuson assessing package robustness:� Advanced microprocessors dependupon transistor scaling to meet densityand performance targets. The accompany-ing interconnect scaling causes the inter-connect propagation delays to be asignificant portion of the clock cycle time,affecting chip performance.14 The use ofcopper interconnects instead of conven-tional aluminum interconnects is the firststep toward reducing this interconnectdelay by reducing the electrical resistance.Further reduction in interconnect delay isachieved by reducing the capacitance inthe ILD material used between the metalinterconnects. An unintended consequenceof driving for lower � is that ILD materialsbecome increasingly fragile, especially asmore and more porosity is introduced toreduce the dielectric constant.15,16

� As die-level features shrink, the die–package interconnects and package-levelfeatures also shrink. Furthermore, there isan increase in feature density. The impactof this is increased fragility of the entiredie–package system.



Figure 21. Illustration of the capillary-rise phenomena against a vertical wall;� is the contact angle, H is the capillaryheight, and p(x,z) is fillet profile.

Figure 22. Illustration of the kind of data that can be collected using measurements such asfracture toughness and fatigue-crack resistance to help predict the ability of (here, unspecified)underfill materials to withstand a variety of mechanical stresses.12

� With increasing power-delivery de-mands, there is an increase in the amountof current flowing through the intercon-nects. Joule heating of the interconnectsand the associated stress issues become amatter of concern.� As heatsinks become heavier and heat-sink retention mechanisms impose higherloads, the effect of mechanical loads intro-duced to improve socket performance isalso a matter of concern. Attention mustbe paid to ensuring mechanical reliability,especially when designing systems withheavily loaded packages that use LGAsockets. In these cases, additional load isplaced to ensure LGA performance.� Increasing power-dissipation demandsimply that the die–package and package–heatsink interfaces along with their thick-ness and thermal characteristics must becarefully optimized. Ensuring the mechani-cal integrity of the interfaces is also critical.

A key aspect of ensuring package ro-bustness is being able to make the rightmaterial and design choices through theuse of accurate and reliable thermo-mechanical modeling of the package.Thermomechanical models will be accu-rate and reliable if� They correctly capture the right level ofdetail, in terms of geometry, of the pack-age. The challenge here is to ensure the di-mensional scales and effects at the silicon,package, and system level are appropri-ately captured. Commercially available fi-nite element codes that include powerful

features such as submodeling capability toaddress the dimensional scaling chal-lenge, combined with powerful comput-ing capabilities, have come a long way inhelping system engineers quickly modeldifferent conditions and assess design andmaterials options.� Materials properties of the different ele-ments of the package are collected andused. A considerable amount of work hasbeen done over the past few decades tocharacterize materials, and powerful data-bases of material properties are now avail-able for use.17

� Appropriate validation methods existthat help calibrate models and validatetheir predictions. A considerable amountof effort has been spent in developing op-tical techniques such as moiré and digitalimage correlation for both a qualitativeand quantitative understanding of the strainand displacement states. Examples of moirétechniques used to assess BGA joint ro-bustness and in die-attach selection areshown in Figures 24 and 25.� Measurement methods that help assessthe strength of interfaces and materials arealso important for enabling appropriatematerials and geometry choices.17

ConclusionThe evolution of microprocessor pack-

aging and future challenges have beensummarized in this article. In brief, micro-processor packaging has evolved froma simple protective enclosure providing

protection to microprocessor chips fromthe external environment to a key enablerof performance. This trend is primarilydue to the increase in microprocessor per-formance, tracking Moore’s law. Key driversfor the development of packaging tech-nologies are power delivery, thermalmanagement, and interconnect scaling,complemented with demands on new ma-terials and package architecture to meetcost pressures driven by competing mar-kets. Although quite a few advances weremade over the last decade, microprocessorpackaging is expected to face increasingchallenges in the future.

Microprocessor power demands willcontinue to increase going forward. Re-designing the power-delivery system stackis critical to achieving cost-effective per-formance solutions. In addition, the devel-opment of new materials and componentsthat have better characteristics and prop-erties such as high-value capacitors andinductors; smaller form-factor components;improved manufacturing capability allow-ing thicker, heavier material layers forhandling the high power levels; and, ofcourse, lower-resistance materials is alsorequired. These developments will furtherenable the integration and miniaturizationof the voltage regulator module and its re-lated passive components and help locateit closer to the microprocessor.

With higher performance, there is an in-crease in microprocessor power dissipation,posing increasing challenges for thermalmanagement. The issue is further exacer-bated by the fact that there are localizedregions of high power density on themicroprocessor die that need to be cooledto ensure performance and reliability.Both of these factors require greater atten-tion to be focused on cost-effective thermal-management strategies. The problem mustbe addressed in its entirety, that is, ap-proached with an intent to optimize allcomponents of the thermal-managementsystem (architecture, package, heatsink, andsystem). Strategies for doing this have beendiscussed in the article.

Package-to-motherboard and die-to-package interconnection technologies haveundergone significant changes. These haveevolved from peripheral connections toarea-array connections and then to reducedcontact pitch. Further reductions in con-tact pitch are expected with future silicongenerations to deliver the large amountof current required for chip switching atincreased frequencies. Package architecturalchanges are also needed to provide in-creased package decoupling capacitance aswell as low package resistance and induc-tance in a cost-effective manner. Thermal-management integration and significant



Figure 23. Interdependency of the underfill properties (viscosity and coefficient of thermalexpansion, CTE) as a function of the formulation variables in the underfill (resin CTE, fillercontent, and filler particle size).13

mechanical loading on the package sub-strate need to be understood in additionto the electrical requirements. These de-mands and the need for environmentallyfriendly products will require significantdevelopment in microprocessor packag-ing materials and processes to provide acontinued rich end-user experience at acompetitive price.

Advanced packaging needs presentcomplex challenges for materials. On thethermal-materials front, the practical limitsof providing a solution using “conven-tional” methods are fast approaching. Newways of integrating advanced materials

technologies already in use in other fields,such as nanocomposites, will be required.Underfill-materials development will bene-fit significantly by moving underfill inte-gration more upstream from assemblyand integrating it with silicon processing.Although this approach is faced with anew set of challenges, it has the advantageof providing a more integrated and cost-effective total solution. In either case, theexisting paradigms and conventional ap-proaches need to be reexamined to comeup with high-performance and cost-effectivematerials solutions for microprocessorpackaging.

With dimensional reductions in siliconand package features, there is an increasein the fragility of the entire silicon, pack-age, and heatsink system. The increasedfragility of the dielectric layers requiresthat attention must be focused on under-standing and optimizing the materialsand geometry choices so that the robustnessof the system is ensured. This requiresdeveloping a good understanding of thestresses in the system under various loadsand developing solutions that are able tosustain these loads. Over the past fewdecades, sophisticated modeling and vali-dation tools that help quantify the stresshave been developed. There is a need tocontinue efforts in this area to be able todesign robust packages.

AcknowledgmentsThe authors would like to take this

opportunity to thank Dr. Nasser Grayeli,Mr. Bala Natarajan, Mr. Robert Sankman,Mr. Mostafa Aghazadeh, and Dr. MikeGarner for providing timely managementsupport. This article would not be pos-sible without the contributions of manyengineers and technicians from Intel Corp.The authors especially acknowledge thecontributions received from the DesignProcess Development, Pathfinding, andMaterials groups from the Assembly Tech-nology Development Division of Intel.

References1. R. Mahajan, K. Brown, and V. Atluri, Intel.Technol. J. Q3 (August 22, 2000), available fromhttp://developer.intel.com/technology/itj/q32000.htm (accessed October 2002).2. N.P. Mencinger, Intel. Technol. J. Q3 (August 22,2000), available from http://developer.intel.com/technology/itj/q32000.htm (accessed October2002).3. G.E. Moore, Electronics 38 (8) (1965) p. 114.4. R. Mahajan, R. Nair, V. Wakharkar, J. Swan,J. Tang, and G. Vandentop, Intel. Technol. J. 6 (2)(2002), available from http://developer.intel.com/technology/itj/2002/volume06issue02/index.htm (accessed October 2002).5. G. Choksi, Intel University Course on Packaging(Intel Corp. Internal Document, January 2002).6. 2001 International Technology Roadmap for Semi-conductors: Executive Summary (SemiconductorIndustry Association, San Jose, 2001).7. J. Torresola, C.-P. Chiu, G. Chrysler, D.Grannes, R. Mahajan, R. Prasher, and A. Watwe,“Density Factor Approach to RepresentingImpact of Die Power Maps on Thermal Man-agement.” Submitted to IEEE Transactions onAdvanced Packaging.8. S.N. Towle, H. Braunisch, C. Hu, R.D. Emery,and G.J. Vandentop, ”Bumpless Build-Up LayerPackaging,” presented at the ASME Int. Me-chanical Engineering Congress and Exposition(IMECE), New York, November 12, 2001.9. R. Viswanath, V. Wakharkar, A. Watwe, andV. LeBonheur, Intel. Technol. J. Q3 (August 22,2000), available from http://developer.intel.com/



Figure 24. Example of moiré (417 nm/fringe) pattern used to study ball grid array (BGA)reliability. U and V represent orthogonal displacements on the cross-sectioned surface ofthe package. (Courtesy of M. Mello and G. Raiser, Intel Corp.)

Figure 25. (a) Finite element analysis (FEA) model and (b) moiré (417 nm/fringe) imageused for die-attach materials selection in organic packages (Courtesy of M. Mello andG. Raiser, Intel Corp.)

technology/itj/q32000.htm (accessed October2002).10. C.K. Chee, T. Sterrett, V. LeBonheur, L. DeCesare, and Y. He; in Proc. GlobalTronics TechnologyConf. (Singapore) (in press).11. S. Skokov, L. Jiang, D. Pantuso, and S.Shankar, Intel Assembly Test Technol. J. 4 (IntelCorp. Internal Technical Journal, 2001) p. 254.12. J. Zhang, Intel Corp. internal technical com-munication (2000).13. S. Jayaraman, P. Koning, F. Hua, T. Chen,

C. Gettinger, and G. Clemmons, Intel AssemblyTest Technol. J. 4 (Intel Corp. Internal TechnicalJournal, 2001) p. 215.14. M.T. Bohr and Y.A. El-Mansy, IEEE Trans.Electron Devices 45 (3) (1998) p. 620.15. S. Allda, in Proc. IEEE Int. Interconnect Tech-nology Conf. (Institute of Electrical and Electron-ics Engineers, Piscataway, NJ, 1999) p. 161.16. S.-T. Chen, S. Cohen, T. Dalton, R. Della-Guardia, S. Gates, S. Greco, J. Hedrick, E. Huang,M. Krishnan, K. Malone, R. Miller, C. Narayan,

S.V. Nitta, S. Purushothaman, K. Rodbell, J.G.Ryan, K. Saenger, E. Simonyi, C. Tyberg, and W.Volksen, in IEDM Tech. Dig. (Institute of Electri-cal and Electronics Engineers, Piscataway, NJ,2001) p. 23.2.1.17. E. Andideh, J. Blaine, C. Block, B. Jin, T.Scherban, and B. Sun, in Proc. IEEE InterconnectTechnology Conf. (Institute of Electrical and Elec-tronics Engineers, Piscataway, NJ, 2001) p. 257.

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