cse140l: components and design techniques for digital...
TRANSCRIPT
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CSE140L: Components and Design Techniques for Digital Systems Lab
Timing, Mux, Demux, Adders
Tajana Simunic Rosing
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Outline• Review of CMOS• Non-ideal gate behavior (3.5)
– Rise/fall time– Delay– Pulse width
• Pass gates (Appendix B)• Muxes & Demuxes (chap 4.2 pp. 171-183)• Adders (chap 5.6)
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CMOS gate design • Implement F using CMOS: F=[A*(B+C)*(AB+C)]’
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CMOS delay review• Implement F using CMOS: F=A*(B+C)
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F is not always 0pulse 3 gate-delays wide
D remains high forthree gate delays after
A changes from low to high
FA B C D
When is non-ideal gate behavior a good thing?
• Can be useful — pulse shaping circuits• Can be a problem — incorrect circuit operation• Example: pulse shaping circuit
– A’ • A = 0– delays matter
initially undefined
close switch
open switch
+
open switch
resistorA B
CD
Oscillatory behavior• Another pulse shaping circuit
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CSE140: Components and Design Techniques for Digital Systems
Muxes and demuxes
Tajana Simunic Rosing
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Pass transistor – Mux building block
• Connects X & Y when A=1, else X & Y disconnected– A_b = not(A)
Fig source: Prof. Subhashish Mitra
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Multiplexor (Mux)• Mux routes one of its N data inputs to its one output,
based on binary value of select inputs• 4 input mux needs 2 select inputs to indicate which input to route
through• 8 input mux 3 select inputs • N inputs log2(N) selects
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Mux Internal Design
• Selects input to connect to Y– selA == 1: connects A to Y– selB == 1: connects B to Y
Fig source: Prof. Subhashish Mitra
2×1
i1i0
s01
d
2×1
i1i0
s00
d
2×1
i1i0
s0
d
2x1 mux
AB Y YA
BAB
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2 -1I0I1I2I3I4I5I6I7
A B C
8:1mux
Z
I0I1I2I3
A B
4:1mux
ZI0I1
A
2:1mux Z
k=0
n
Multiplexers/selectors• 2:1 mux: Z = A'I0 + AI1• 4:1 mux: Z = A'B'I0 + A'BI1 + AB'I2 + ABI3• 8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +
AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
• In general: Z = Σ (mkIk)
– in minterm shorthand form for a 2n:1 Mux
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N-bit Mux Example
• Four possible display items– Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I),
and Miles remaining (M) -- each is 8-bits wide– Choose which to display using two inputs x and y– Use 8-bit 4x1 mux
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C0 C1 C2 Function Comments0 0 0 1 always 10 0 1 A + B logical OR0 1 0 (A • B)' logical NAND0 1 1 A xor B logical xor1 0 0 A xnor B logical xnor1 0 1 A • B logical AND1 1 0 (A + B)' logical NOR1 1 1 0 always 0
Mux example: Logical function unit
C2C0 C1
01234567S2
8:1 MUX
S1 S0
F
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Multiplexers as general-purpose logic• A 2n-1:1 multiplexer can implement any function of n variables
– with n-1 variables used as control inputs and– the data inputs tied to the last variable or its complement
• Example: F(A,B,C) = ABC + ABC’+A’BC+AB’C
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1:2 Decoder:O0 = G • S’O1 = G • S
2:4 Decoder: O0 = G • S1’ • S0’O1 = G • S1’ • S0O2 = G • S1 • S0’O3 = G • S1 • S0
3:8 Decoder: O0 = G • S2’ • S1’ • S0’O1 = G • S2’ • S1’ • S0O2 = G • S2’ • S1 • S0’O3 = G • S2’ • S1 • S0O4 = G • S2 • S1’ • S0’O5 = G • S2 • S1’ • S0O6 = G • S2 • S1 • S0’O7 = G • S2 • S1 • S0
Demultiplexers/decoders• Decoders/demultiplexers: general concept
– single data input, n control inputs, 2n outputs– control inputs (called “selects” (S)) represent binary index of
output to which the input is connected– data input usually called “enable” (G)
Demultiplexers as general-purpose logic (cont’d)F1 = A'BC'D + A'B'CD + ABCDF2 = ABC'D' + ABCF3 = (A' + B' + C' + D')
A B
0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD
4:16DECEnable
C D
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CSE140: Components and Design Techniques for Digital Systems
Arithmetic circuits
Tajana Simunic Rosing
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Design example: 1-bit binary adder
• Inputs: A, B, Carry-in• Outputs: Sum, Carry-out
– Sum = A xor B xor Cin– Cout= A B + A Cin + B Cin
= A B + Cin (A xor B)
AB
CinCout
SA B Cin Cout S0 0 0 0 0 0 0 1 0 10 1 0 0 1 0 1 1 1 01 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
A A A A AB B B B B
S S S S S
CinCout
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A
A
B
BCin Cout
@0@0
@0@0
@N
@1
@1
@N+1
@N+2
latearrivingsignal
two gate delaysto compute Cout
4 stageadder
A0B0
0
S0 @2
A1B1
C1 @2
S1 @3
A2B2
C2 @4
S2 @5
A3B3
C3 @6
S3 @7Cout @8
Ripple-carry adder critical delay path
T0 T2 T4 T6 T8
S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid
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Carry-lookahead• Evaluate Sum and Ci+1
– Sum = Ai xor Bi xor Ci– Ci+1 = Ai Bi + Ai Ci + Bi Ci
= Ai Bi + Ci (Ai xor Bi)
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G3
C0
C0
C0
C0
P0
P0
P0
P0G0
G0
G0
G0C1 @ 3
P1
P1
P1
P1
P1
P1
G1
G1
G1
C2 @ 3
P2
P2
P2
P2
P2
P2
G2
G2
C3 @ 3
P3
P3
P3
P3
C4 @ 3
Pi @ 1 gate delay
Ci Si @ 2 gate delays
BiAi
Gi @ 1 gate delay
increasingly complexlogic for carries
Carry-lookahead implementation• Adder with propagate and generate outputs
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A0B0
0
S0 @2
A1B1
C1 @2
S1 @3
A2B2
C2 @4
S2 @5
A3B3
C3 @6
S3 @7Cout @8
A0B0
0
S0 @2
A1B1
C1 @3
S1 @4
A2B2
C2 @3
S2 @4
A3B3
C3 @3
S3 @4
C4 @3 C4 @3
Carry-lookahead implementation (cont’d)• Carry-lookahead logic generates individual carries
– sums computed much more quickly in parallel– however, cost of carry logic increases with more stages
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Lookahead Carry UnitC0
P0 G0P1 G1P2 G2P3 G3 C3 C2 C1
C0
P3-0 G3-0
C4
@3@2@4
@3@2@5
@3@2@5
@3@2
@4
@5@3
@0C16
A[15-12] B[15-12]C12
S[15-12]
A[11-8] B[11-8]C8
S[11-8]
A[7-4] B[7-4]C4
S[7-4]@7@8@8
A[3-0] B[3-0]C0
S[3-0]
@0
@4
4 4
4P G
4-bit Adder
4 4
4P G
4-bit Adder
4 4
4P G
4-bit Adder
4 4
4P G
4-bit Adder
Carry-lookahead adderwith cascaded carry-lookahead logic
• Carry-lookahead adder– 4 four-bit adders with internal carry lookahead– second level carry lookahead unit extends lookahead to 16 bits
G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0
P = P3 P2 P1 P0
C1 = G0 + P0 C0C2 = G1 + P1 G0 + P1 P0 C0
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4-Bit Adder[3:0]
C0C4
4-bit adder[7:4]
1C8
0C8
five2:1 mux
01010101
adder low
adderhigh
01
4-bit adder[7:4]
C8 S7 S6 S5 S4 S3 S2 S1 S0
Carry-select adder• Redundant hardware to make carry calculation go faster
– compute two high-order sums in parallel while waiting for carry-in– one assuming carry-in is 0 and another assuming carry-in is 1– select correct result once carry-in is finally computed
What we’ve covered thus far
• Transistor design• Delay estimates• Pass transistors• Muxes• Demuxes• Adders
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