cse241 vlsi digital circuits winter 2003 lecture...

CSE241 L3 ASICs.1 Kahng & Cichy, UCSD ©2003

CSE241VLSI Digital Circuits

Winter 2003

Lecture 03:ASIC prototyping


This Class + Logistics

§ Overview of flow (preparation for Smith Chapters 12-17)

§ Read: Smith Chapter 12 (Synthesis), 13.7 (Static timing)

§ Lab #1 revised due date: Monday January 20

§ Near-term schedule:

l Ben has reserved the lab (EBU I, Room 3329) for this Friday, January 17, noon-1:20pm à a running start into synthesis

l Recitation #2 tomorrow (noon-12:50pm): not on RTL design, but on datapaths and memories

l Lab tomorrow (3:30-5pm): really Lab #1

Slide courtesy of S. P. Levitan, U. Pittsburg


Review

§ Scaling of gates vs. Scaling of wires

l What happens when you make a gate bigger?

l What happens when you make a wire taller? Wider?

§ Coupling

§ Inductance

l How does power/ground distribution affect inductance?

§ RC delay

§ Dynamic (useful) power vs. Static (useless) power

§ How do these issues impact estimates and design approaches?



Outline§ Design types and cost drivers

§ Basic flow

§ Methodologies for design convergence

§ Hierarchy


IC Design Methodologies

§ Full-Custom (high effort, leading-edge performance, high-volume)

§ Semi-Custom (strong infrastructure, economical in lower volumes)

l ASIC (Application-Specific Integrated Circuit)

l COT (Customer-Owned Tooling)

l ASIC vs. COT: “Who pays for the scrap?”

§ FPGA

§ System-on-a-Chip

l Larger components, often from outside of design team

§ Special

l Analog (custom layout, I/Os and sense amps)

l Mixed-Signal / RF (unique to each process, no scaling)



Acceleration of Gate Length Scaling

§ What are some implications?

•Slide courtesy of Numerical Technologies, Inc.


Mask NRE Cost (1999)

“$1M mask set” in 100nm, but average only 500 wafers per set


Design Technology Crises, ITRS-2001

Manufacturing

NR

E C

ost

SW Design

Verification

HW Design

TestT

urn

aro

un

d T

ime

Manufacturing

Incremental Cost Per Transistor

§ 2-3X more verification engineers than designers on microprocessor teams

§ Software = 80% of system development cost (and Analog design hasn’t scaled)

§ Design NRE > 10’s of $M ßà manufacturing NRE $1M

§ Design TAT = months or years ßà manufacturing TAT = weeks

§ Without DFT, test cost per transistor grows exponentially relative to mfg cost


Silicon Complexity ChallengesSilicon Complexity Challenges§ Silicon Complexity = impact of process scaling, new materials, new

device/interconnect architectures

§ Non-ideal scaling (leakage, power management, circuit/device innovation, current delivery)

§ Coupled high-frequency devices and interconnects (signal integrity analysis and management)

§ Manufacturing variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools)

§ Scaling of global interconnect performance (communication, synchronization)

§ Decreased reliability (SEU, gate insulator tunneling and breakdown, joule heating and electromigration)

§ Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost)


System Complexity ChallengesSystem Complexity Challenges§ System Complexity = exponentially increasing transistor counts, with

increased diversity (mixed-signal SOC, …)

§ Reuse (hierarchical design support, heterogeneous SOC integration, reuse of verification/test/IP)

§ Verification and test (specification capture, design for verifiability, verification reuse, system-level and software verification, AMS self-test, noise-delay fault tests, test reuse)

§ Cost-driven design optimization (manufacturing cost modeling and analysis, quality metrics, die-package co-optimization, …)

§ Embedded software design (platform-based system design methodologies, software verification/analysis, codesign w/HW)

§ Reliable implementation platforms (predictable chip implementation onto multiple fabrics, higher-level handoff)

§ Design process management (team size / geog distribution, data mgmt, collaborative design, process improvement)



§ Basic flow


§ Hierarchy

CSE241 L3 ASICs.12 Kahng & Cichy, UCSD ©2003Sylvester-Keutzer, Computer Nov. 99

Sylvester-Keutzer: Classic PictureSylvester-Keutzer: Classic Picture


Flow Steps

§ Preparation

l Library data preparation

l Design data preparation

§ Logic design

l Specification to RTL

l RTL simulation

l Hierarchical floorplanning

l Synthesis

l Formal verification

l Gate level simulation

l Static timing analysis

n Physical design•Physical floorplanning

•Place and route

•RC extraction

•Formal verification

•Physical verification

•Release to manufacturing

n Design for test

n Engineering change order


Library and Design Data

§ Models and technology data required to execute the design flow

§ Power, timing: ALF, DCL, OLA, .lib, STAMP

§ Layout: LEF, DEF, GDSII

§ Delays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF, SPEF, SPICE

§ Layout rules: Dracula, Calibre “deck”


Specification to RTL§ Defines the logic and fundamental structure of the chip

at the RTL level in either the verilog or VHDL language

§ Requires considerable interaction with the customer, plus specs such as the architecture, system, design, test and block specs

§ May include RTL from the customer or third party IP providers

§ Coding guidelines should be established and adhered to, and the code must be compatible with the chosen synthesis tool

§ Special design considerations such as multiple clock frequencies, asynchronous logic, high speed logic, race conditions, gated clocks, etc. must be addressed


RTL Simulation

§ RTL code, written in Verilog, VHDL or a combination of both, is simulated to verify functional correctness

§ Testbenches apply input stimulus to the design

§ Several methods are used to verify the outputs

l Self-checking testbenches automatically verify output correctness andreport mismatches

l Results can be stored in a file and compared to previous results

l Waveform displays can be used to interactively verify the outputs

§ Verification-specific tools: Verisity Specman, Synopsys Vera

§ Functional verificationl Mostly Modelsim

l Cadence’s Verilog-XL or NC-Verilog also used


Hierarchical Floorplanning§ Decide on the physical layout strategy—flat or hierarchical?

§ Advantages of a flat implementation are generally a smaller die size, and a more straightforward approach to clock and power distribution and RC generation

§ Advantages of a hierarchical design l better runtimes, l better ability to control timing within localized areas of the design, and

concurrent design

§ For hierarchical design, issues l physical partitioning of the logic into blocksl assignment of the physical locations for the block pinsl timing budgeting, l distribution of clocks, powerl signal bus routingl RC generation

§ Tool Example: Cadence’s design planner


“Blocks”

1.0

1.0

0.5,0.5

Blk A Blk B


Color-Coding a Placement


Floorplanning

§ Give placement initial clues

§ Cells that are interconnected want to be close togetherl Take advantage of RTL hierarchyl Generate a physical hierarchyl RTL hierarchy = best physical hierarchy?

§ Place big blocks on chip (memories)

§ Allow space for power/clk/busses

§ Reduce complexity of placement


Synthesis

§ Conversion of RTL to gate level netlist

l Target foundry specific library

§ Timing driven methodologyl clock information

l input arrival times, output required times

l Input driving cells, output loading

l False paths, multi-cycle paths

§ Interconnect delay is calculated based on a wireload model which uses fanout to calculate delay

§ Clocks parameters (insertion delay, skew, jitter, etc.) Are assumed to be attainable later in place and route


Synthesis …contd.

§ Hierarchical synthesis

l Block-by-block basis

l Minimizes runtimes

l Functional blocks

§ Tools:

l Cadence Buildgates

l Synopsys Design Compiler (used for this course)


Formal Verification§ RTL description and gate level netlist are compared to

verify functional equivalence, thereby verifying the synthesis results

§ An emerging technology that supplements the more traditional approach of gate level simulation

§ Tools:l Verplex Tuxedo-lec

l Design Verifier (Chrysalis), Mentor FormalPro

l Synopsys Formality (will be used in-class)


Gate Level Simulation§ Another method to verify the synthesis process, which

covers both the functionality and timingl Correctness is only as good as the test vectors that are usedl Especially critical for non-synchronous designs, verification of

false path and multi-cycle path constraints

§ Cell timing is included in the simulation models and interconnect delay is passed from the synthesis run

§ Worst case PVT conditions are used to analyze for setup violations, and best case PVT conditions are used to analyze for hold violationsl PVT = Process, Voltage, Temperature

§ Popular tools are Cadence’s Verilog-XL or NC-Verilog


Static Timing Analysis§ Verifies that design operates at desired frequency

l Implicitly assumes correct timing constraints (!), e.g., boundary conditions

§ Timing constraints are similar to those used in synthesis

§ Verifies setup and hold times at FF inputs; can also check timing from and to PI’s and PO’s; can also check point-to-point delay values (with blocking of pins, etc.)

§ As with gate-level simulation, both best- and worst-case analysis is performed

§ Typically performed on full-chip (not block) basis

l May require modified constraints for inter-block issues: multiple clock domains, multi-cycle paths, etc.

§ For compatibility with timing-driven layout flow, helps to have simple / single set of constraints

l Other issues: incremental analysis, …


Physical Floorplanning

§ Defines the basic chip layout architecture

l Define the standard cell rows and I/O placement locations

l Place rams and other macro cells

l Define power bus structures such as power rings and stripes

§ Often performed using the standard place and route tool

§ Rules of thumb for cell density are used to initially calculate design size

§ Popular standalone tools are Cadence’s design planner and avanti’s planet


Place and Route§ Automatically place the standard cells

§ Generate clock trees

§ Add any remaining power bus connections

§ Route clock lines

§ Route signal interconnects

§ Design rule checks on the routes and cell placements

§ Timing driven toolsl Require timing constraints and analysis algorithms similar to those

used during the static timing analysis step

§ Tools: l Cadence Silicon Ensemble, Synopsys Apollo, Magma Blast Fusion


RC Extraction§ Calculates the resistance and capacitance of

interconnects l Based on placement of cells

l Routing segments

§ Calculates capacitive effects of adjacent segments l Extracts capacitance between metal segments

§ RC data is transferred to l Static timing analysis (back annotation)

l Gate level simulation

l Replaces wire load model used in synthesis

§ Tools used:l Cadence Hyperextract , Magma’s Blast Fusion

l Sequence Columbus, Synopsys Star-RC, Mentor X-Calibre


Signal Integrity

§ SIl Crosstalk issuesl Inductancel Interference

§ Need new toolsl Calculate and estimate SIl New delay models with SI estimatesl SI aware routing


Formal Verification

§ Compares golden netlist to current netlist

l Logic equivalence

§ Comparison of pre- and post-layout netlist

l Similar to the formal verification step after synthesis; clock tree insertions, drive strength changes, etc. have been made

l Buffer insertion or logic optimization may have been performed


Physical Verification§ DRC – Design Rule Check

l Polygon/Layer spacing rulesl Verifies the design rules (DRC)

§ LVS – Layout Versus Schematicl Verifies that layout and netlist are equivalent at the transistor

level

§ Antenna l Manufacturing check for long netsl Net can become charged and damaged silicon

§ GDSIIl Final merge of layout , routing and placement for physical maskl Often a notch fill algorithm is used to fill in ‘holes’ within the

same electrical net

§ Example tools:l Mentor Graphics Calibre (DRC, LVS)l Cadence Dracula, Diva


Release to Manufacturing§ Final edits to the layout are made

§ Metal fill and metal stress relief rules are checked

§ Manufacturing information such as scribe lanes, seal rings, mask shop data, part numbers, logos and pin 1 identification information for assembly are also added

§ DRC and LVS are run to verify the correctness of the modified database

§ ‘Tapeout’ documentation is prepared prior to release of the GDSII to the foundry

§ Pad location information is prepared, typically in a spreadsheet

§ Cadence’s Virtuoso is used for custom-manual edits of the mask layers

§ Manufacturing stepsl generation of masksl silicon processing l wafer testingl assembly and l package test


Outline

§ Design types and cost drivers

§ Basic flow


§ Hierarchy


Sylvester-Keutzer: Classic PictureSylvester-Keutzer: Classic Picture


Basics of Design Convergence§ What must converge ?

l logic, timing, and spatial embedding

l support front-end signoff, provide predictable back-end

§ Ways to achieve Convergence through Predictabilityl correct by construction (“assume, then enforce”)

- constraints and assumptions passed downstream; not much goes upstream

- ignores concerns via guardbanding- separates concerns as able (e.g., FE logic/timing vs. BE spatial

embedding)

l construct by correction (“tight loops”)- logic-layout unification; synthesis-analysis unification, concurrent

optimization

l elimination of concerns- reduced degrees of freedom, pre-emptive design techniques- e.g., power distribution, layer assignment / repeater rules, GALS/LIS


What Must A Design Closure Tool Look Like ?§ Input

l RT-level HDL + technology + constraints

§ Outputl “go”: recipe for invocation and composition of “commodity” SP&Rl “no go”: diagnosis of RTL code problems

§ Logical and physical hierarchies co-evolvel spatial: top-down coarse placement à physical hierarchyl logic/timing: implementable RTL à logical hierarchyl limits of human fanout, organizations à always have hierarchy

- natural sequence of no-floorplanning, phys-floorplanning, RTL-floorplanning...

§ Details (must construct, predict, ignore, eliminate, ...)l pin optimizations, interconnect planning, hierarchy reconciliations,

budgeting mechanisms, compatibility with downstream SP&R, ...


KEY ISSUE: PREDICTABILITY§ Everything we do is ultimately aimed at a predictable,

estimatable back end (physical implementation after some handoff level of design)

§ Predictability == regression models?

§ Predictability == an enforceable assumption?l constant-delay paradigm (logical effort, DEC, IBM, ...)

§ Predictability == fast constructive prediction?l RT-level (Tera Systems), gate-level flat full-chip (Silicon

Perspective Corp.)

§ Predictability == remove the need for predictability?l GALS, LIS (global-asynchronous/local-synchronous; latency-

independent synchronization)l “protocol- / communication-based system-level design”


Planning Technology§ RTL partitioning

l understand interaction b/w block definition and placement qualityl recognize and cure a physically challenged logic hierarchy

§ Global interconnect planning and optimizationl symbolic route representations to support block plan ECOs

§ Controllable SP&R back end (including power/clock/scan)

§ Incremental / ECO optimizations, and optimizations that are “robust” under partial or imperfect design knowledge

§ Estimators (“initial wireload models”)l to account for resource, topological heterogeneityl to account for optimizations (placement, ripup/reroute, timing)

§ à “earliest RTL signoff with detailed P&R knowledge”


Sylvester-Keutzer: Logical + PhysicalSylvester-Keutzer: Logical + Physical

•Yesterday 1000nm • Today 130nm • Tomorrow 50nm •Required Advance in Design System Architecture

•Functional•Performance

•Testability•Verification

•SPEC

•Hw/Sw•SW•Logic•Circuit•Place•Wire•other

•Perf.•Timing•Power•Noise•Test•Mfg.•other

•Repository

•Hw/Sw•Data

•Model

•Optimize •Analyze•Comm.

•Cockpit

•Auto-Pilot

•EQ

check

•MASKS

•System •Design

•System •Model

•Perf.•Model

•System •Design

•System •Model

•File

•Synthesis•+ Timing Analysis•+ Placement Opt

•File

•Place/Wire•+ Timing Analysis

•+ Logic Opt

•SW •Opt

•Performance•Testability•Verification

•Functional•Verification

•MASKS

• RTL•SW

•Equivalence checking

•Hw/Sw•Optimization

•Multiple design files are converged into one efficient Data Model•Disk accesses are eliminated in critical methodology loops•Verification of Function, Performance, Testability and other design •criteria all move to earlier, higher levels of abstraction followed by

•equivalence checking and•assertion driven design optimizations

•Industry Standard interfaces for data access and control•Incremental modular tools for optimization and analysis•

•Logic •Design

•Software •Design

•Functional•Verification

•Performance•Verification•File

•Timing Analysis

•File

•Place/Wire

•File

•Synthesis

•File

•Timing Analysis

•RTL

•MASKS

•System •Design

•Testability•Verification


Planning / Implementation Methodologies§ Centered on logic design

l wire-planning methodology with block/cell global placementl global routing directives passed forward to chip finishingl constant-delay methodology may be used to guide sizing

§ Centered on physical designl placement-driven or placement-knowledgeable logic synthesis

§ Buffer between logic and layout synthesisl placement, timing, sizing optimization tools

§ Centered on SOC, chip-level planningl interface synthesis between blocksl communications protocol, protocol implementation decisions

guide logic and physical implementation


Gate-Level Place & Route

Gate-Level Optimization

DesignConstraintsIP Blocks

Library

Top-Level Routing

RC Extraction

Timing Analysis

Early Planning

Design Refinement

Chip Assembly

PREDICTABLE HIERARCHICAL DESIGN CONVERGENCE

ARISTO TYPICAL DESIGN FLOW

DesignNetlist

Gate-LevelVerilog

RTL Verilog

Hard Blocks

Concurrent Block Partitioning, Clustering & Placement

Block Shaping, Compaction &Concurrent Port Placement

ConcurrentBlock

Synthesis

Aristo, DAC-2000


GDSII

Tim

ing

Ro

ute

Pla

ce

log

ic

Physical Prototyping

IncreasingModeling

Detail

Design Signoff

timing librarystatistical WLM

Behavioral / RTL synthesis

RTL

Monterey, DAC-2000


SequencePlace

&Route

PrepareDatabase

3D Extraction

True-3DParasitics

DelayCalculation

TimingAnalysis

TimingAnalysis

InterconnectDriven

Optimization

InterconnectDriven

Optimization

SynthesisRTL

Timing Sign-off

Driver sizing,topology-based

optimization

Sequence, DAC-2000


Cadence, DAC-2000

§

Finalize Route/Extract/Back Ann.

Inter-block Routing and Buffering

Communication Logic Synthesis

Concurrent Placement, Synthesis And Route of Cells in Blocks

Block Area/Performance Estimation

Block Placement

RTL, chip constraints

Partitioning & Log/Phys MappingConstraints complete and

block RTLs are feasible

Ensure interblock delays

are accounted for

No iterations from here down


Magma, DAC-2000 “fixed timing”

0.6ns 0.6ns 0.6ns 0.6ns

FF

§Actively managing wire delay:l Through automatic sizing

(sizing-driven placement)l Through buffer insertion



§ Basic flow


§ Hierarchy


The Problem With Hierarchies

§ Two hierarchies: logical/functional, and physicall schematic hierarchy also typical in structured-custom

§ RTL design = logical/functional hierarchyl provides valuable clues for physical embedding: datapath

structure, timing structure, etc.l can be incredibly misleading (e.g., all clock buffers in a single

hierarchy block)

§ Main issues:l how to leverage logical/functional hierarchy during embeddingl when to deviate from designer’s hierarchyl methodology for hierarchy reconciliation (buffers, repartitioning /

reclustering, etc.)


Functional Partitioning

•Subblocks in A connected with subblocks in B result in•600 top level nets.

Source: ReShape


Physical Partitioning

Physical partitioning reduced the number of top level nets from 600 to 0

Source: ReShape


Problems With Physical Hierarchy

§ Physical hierarchy = hierarchical organization of the core layout region

§ In general, no relation to high-quality (e.g., w.r.t. timing, routability) embedding of logicl artificial physical hierarchy created by top-down placersl core region is relatively homogeneous, isotropic: imposing a

hierarchy is generally harmful

§ Of course, some obvious exceptionsl regular structures (memories, PLAs, datapaths)l hard IP blocksl but these don’t fit well in top-down placement anyway

§ General trend: non-hierarchical embedding approaches


Interconnect Complexities§ Interconnect effects play a major role in the increasing

costs for large hard-block or rectilinear-outline based design styles

§ Probabilistic wireload models fail

§ Without new capabilities for soft IP design and assembly, interconnect problems will significantly impact performance and cost for emerging IC technologies

Occ

urre

nce

Rat

e(N

orm

aliz

ed)

sizediewirelength

_~0.5

Local wires

Global wires

blocks

globalwires

Courtesy Pileggi, MARCO GSRC


Technology Scaling§ Block sizes cannot grow as rapidly as chip sizes since

block design becomes increasingly more difficult --- each block is a chip design over multiple configurations

§ If the blocks are inflexible, the global wiring problems begin to dominate all aspects of performance quality and system cost

Occ

urre

nce

Rat

e(N

orm

aliz

ed)

sizediewirelength

_~0.5

Larger chip with finer feature sizes



Soft Blocks§ With soft, flexible blocks, the system assembly can more

thoroughly exploit the available technology

§ Interconnect problem is controlled via: soft boundaries for area re-shaping; re-synthesis and re-mapping for timing; smart wires; and top-down specified block synthesis

§ Cf. “Amoeba” placement, coloring analysis of “good” placements with respect to original logic hierarchy, etc.

Occ

urre

nce

Rat

e(N

orm

aliz

ed)

sizediewirelength

_~0.5

Superior timing, power and cost



Soft-Block Assembly§ Hard rectilinear blocks make prediction of global wires

extremely difficult

§ Top-down constraint-driven assembly of soft fabrics:ability to significantly restructure circuit level blocks during the assembly process helps reach performance goalsl For example, timing-critical interconnect paths can be

completely restructured during assembly without changing any of the system level specification

§ Key issue: how to determine the soft blocks in the first placel non-classical partitioning objectives: area sensitivity, functional

and clocking structure, critical timing-path awareness, matching capabilities of block placer

l block placement: largely unsolved issue- unclear whether packing-centric or connectivity-centric approaches

are best



“Edge” Logic

§Std. cells that are associated with padcells§Usually for timing purposes, e.g.,

double data rate (DDR) interfaces§Help the physical designer find

them w/hierarchy

Source: ReShape

cse241 vlsi digital circuits winter 2003 lecture...

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