ece407/507 vlsi digital circuits lecture 01: introductionece507/lecture_1.pdf · vlsi digital...

ECE407/507ECE407/507VLSI Digital Circuits

Lecture 01: Introduction

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.

And Prof. Mary Jane Irwin ‘s lecture notes and slides]

CSE477 L01 Introduction.1 Irwin&Vijay, PSU, 2002

Course Contents

Introduction to digital integrated circuitsC OS f C OSCMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design Memory designsequential circuit design. Memory design.

Course goalsAbility to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability

Course prerequisitesECE 274. Basic Digital Circuit DesignECE 351A. Basic Micro ElectronicsECE304 Basic Analog Circuit Design


Course AdministrationI t t J t WInstructor: Janet Wang

[email protected]://apache.ece.arizona.edu/~wml/public htmlp p p _ECE Building Rm 559Office Hrs: Mon, Weds 10:00-11:00

TA: QI JI

Friday lab sessions 9:00 9:50Friday lab sessions 9:00-9:50

Office Hrs : TBA

Labs: Accounts on ECE machine in Rm 232A or Rm 250A-B

URL: http://www.ece.arizona.edu/~ece507

Text: Digital Integrated Circuits 2nd Edition


Text: Digital Integrated Circuits, 2 Edition Rabaey et. al.

Grading InformationG d d t i tGrade determinates

Two Midterm Exams ~40%Final Exam (only for undergraduate students) ~30%Final Exam (only for undergraduate students) ~30% Term Projects (only for Graduates) ~40%Homeworks ~10%Homeworks 10%Labs (teams of ~2)

- Undergraduates: Lab1-3: 10%, Lab 4: 10%- Graduates: Lab 1-3: 5%, lab 4: 5%.

Grade Curve will be posted on the course homepageMust submit email request for change of grade after discussions with the TA (Homeworks/Lab Assignments) or instructor (Exams)( )


Background from ECE274, ECE351A and ECE304ECE304

Basic circuit theoryresistance, capacitance, inductanceMOS gate characteristics

Hardware description languageVHDL or verilog

Use of modern EDA toolssimulation, synthesis, validation (Synopsys)

Basic Logic designlogical minimization, Finite State Machines, and component g , , pdesign


Courses Very Related

ECE 462/562 Computer ArchitectureECE 462/562 Computer ArchitectureInstructor: Prof. Ahmed Louri

ECE 474/574 Logic Circuit DesignInstructor: Prof. S. Lysecky

You should take these two courses if you are interested in IC design !!!in IC design !!!


Course StructureDesign and tool intensive class

Magic for layout (Cadence Virtuoso as option)O li d t ti d t t i l- Online documentation and tutorials

HSPICE for circuit simulationCadence VLSI toolsCadence VLSI tools

Lecture tentative Schedule:2 k th CMOS i t2 weeks on the CMOS inverter 3 weeks on static and dynamic CMOS gates2 weeks on C R and L effects2 weeks on C, R, and L effects 2 week on sequential CMOS circuits 2 weeks on design of datapath structuresg2 weeks on memory design1 week on design for test, margining, scaling, trends


1 week exams

Graduate Student Project List (tentative)

High Speed Link DesignHigh Speed Link Design

High Speed Router design

Chip Security Circuit Design

Chip ID designChip ID design

Chirp Communication Circuit Design

Random Number Generator Design

Sensors and Sensor fusion circuit DesignSensors and Sensor fusion circuit Design


August-September ScheduleLab tutor sessions start on Sept. 5

Sept 1 Sept 29 no lectures (Sept 1 Labor day SeptSept. 1, Sept. 29 no lectures (Sept. 1 Labor day, Sept. 29 instructor on trip)

Aug. 24 Lecture 1: IntroductionAug. 26 Lecture 2: Design MetricsAug 28 No LectureAug 31 Lecture 3: MOS transistorsAug.31 Lecture 3: MOS transistorsSept. 2 Lecture 4: Static InverterSept. 4 Tutor Session: Cadence Flow SetupSept. 7 No ClassSept. 9 Lecture 5: FabricationSept 11 Lecture 6: Static LogicSept. 11 Lecture 6: Static LogicSept. 13 Lecture 7: Pass Transistor LogicSept. 15 Lecture 8: Capacitance


Sept. 17 Tutor Session: Layout Demonstration

Transistor Revolution

Transistor Bardeen (Bell Labs) in 1947Transistor –Bardeen (Bell Labs) in 1947

Bipolar transistor – Schockley in 1949

First bipolar digital logic gate – Harris in 1956

First monolithic IC – Jack Kilby in 1959First monolithic IC – Jack Kilby in 1959

First commercial IC logic gates – Fairchild 1960

TTL – 1962 into the 1990’s

ECL – 1974 into the 1980’sECL 1974 into the 1980 s


MOSFET Technology

MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935

CMOS – 1960’s, but plagued with manufacturing problems

PMOS in 1960’s (calculators)

NMOS i 1970’ (4004 8080) f dNMOS in 1970’s (4004, 8080) – for speed

CMOS in 1980’s – preferred MOSFET technology because of power benefits

BiCMOS, Gallium-Arsenide, Silicon-Germanium

SOI, Copper-Low K, …


Moore’s Law

In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double

(every 18 to 14 months (i.e., grow exponentially with time).

Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s.

2300 transistors 1 MHz clock (Intel 4004) 19712300 transistors, 1 MHz clock (Intel 4004) - 197116 Million transistors (Ultra Sparc III)42 Million 2 GHz clock (Intel P4) - 200142 Million, 2 GHz clock (Intel P4) 2001140 Million transistor (HP PA-8500)


Intel 4004 Microprocessor


Intel Pentium (IV) Microprocessor


State-of-the Art: Lead Microprocessors


Moore’s Law in Microprocessors

Transistors on lead microprocessors double every 2 years

100

1000

2X growth in 1.96 years!

P ti ®P6

10

(MT)

286386

486Pentium® proc

0 1

1

nsis

tors

80088080

8085 8086286

0.01

0.1

Tran

40048008

0.001

1970 1980 1990 2000 2010


1970 1980 1990 2000 2010Year

Courtesy, Intel

Evolution in DRAM Chip Capacityh

64,000,000100000000

human memoryhuman DNA

4X h 3 !

1 000 000

4,000,000

16,000,000

1000000

10000000p

0.1 μm

0.07 μm4X growth every 3 years!

64,000

256,000

1,000,000

100000

1000000

city

/chi

0 35 0 4 μm

0.18-0.25 μm

0.13 μm

book

4,000

16,00010000

it ca

pac

0.7-0.8 μm

0.5-0.6 μm

0.35-0.4 μm

encyclopedia2 h s CD dio

64

256

1,000

100

1000

Kbi

1.6-2.4 μm

1.0-1.2 μm

μ2 hrs CD audio

30 sec HDTV

64

101980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

page


Year

Die Size Growth

100

Die size grows by 14% to satisfy Moore’s Law

100

Pentium ® procP6m

m)

8080 8086286

386486 Pentium ® proc

10

ie s

ize

(m

7% th

40048008

8085Di ~7% growth per year

~2X growth in 10 years

1

1970 1980 1990 2000 2010


1970 1980 1990 2000 2010Year

Courtesy, Intel

Clock Frequency

Lead microprocessors frequency doubles every 2 years

10000

1000

10000

2X every 2 years

P6Pentium ® proc

100

1000

(Mhz

)

2X every 2 years

Pentium ® proc486

3862868086808510

quen

cy (

8086

80808008

1

Freq

800840040.1

1970 1980 1990 2000 2010


YearCourtesy, Intel

Power Dissipation

100

Lead Microprocessors power continues to increase

P6Pentium ® proc

100

Pentium ® proc

486386

2868086

10

r (W

atts

)

3868085

808080084004

1Pow

er

4004

0.11971 1974 1978 1985 1992 2000

Year

P d li d di i ti ill b hibiti

CSE477 L01 Introduction.20 Irwin&Vijay, PSU, 2002Courtesy, Intel

Power delivery and dissipation will be prohibitive

Power Density

10000Rocket

1000(W

/cm

2)

Nuclear

Nozzle

100

Den

sity

( NuclearReactor

40048008 8085

8086

286 386 Pentium® procP610

Pow

er D

Hot Plate

8080 286 386486

p

11970 1980 1990 2000 20101970 1980 1990 2000 2010

Year

Power density too high to keep junctions at low temp


Power density too high to keep junctions at low temp

Courtesy, Intel

Design Productivity Trends

Logic Tr./Chip

10,000

1,000M)

10,000

100,000

Tr./Staff Month.

58%/Yr compounded

1,000

100

10per C

hip

(M

100

1,000

10,000

vity

aff -

Mo.

exity

58%/Yr. compoundedComplexity growth rate

10

1

Tran

sist

or p

10

100

Prod

uctiv

Tran

s./S

ta

Com

ple

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x0.1

0.01Logi

c T

0.1

1 (K)

003

981

983

985

987

989

991

993

995

997

999

001

005

007

009

0.001 0.01

2019 19 19 19 19 19 19 19 19 19 20 20 20 20

Complexity outpaces design productivity

CSE477 L01 Introduction.22 Irwin&Vijay, PSU, 2002Courtesy, ITRS Roadmap

Co p e ty outpaces des g p oduct ty

Technology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014Feature size (nm) 180 130 100 70 50 35Feature size (nm) 180 130 100 70 50 35Mtrans/cm2 7 14-26 47 115 284 701Chip size (mm2) 170 170-214 235 269 308 354Signal pins/chip 768 1024 1024 1280 1408 1472Clock rate (MHz) 600 800 1100 1400 1800 2200Wiring levels 6-7 7-8 8-9 9 9-10 10Wiring levels 6 7 7 8 8 9 9 9 10 10Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6High-perf power (W) 90 130 160 170 174 183Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4

For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 ( p ;doubling every two years)

http://www itrs net/ntrs/publntrs nsf


http://www.itrs.net/ntrs/publntrs.nsf

Why Scaling?

Technology shrinks by ~0.7 per generation

With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly

Cost of a function decreases by 2x

B tBut …How to design chips with more and more functions?Design engineering population does not double every two yearsDesign engineering population does not double every two years…

Hence, a need for more efficient design methodsExploit different levels of abstraction


Design Abstraction Levels

SYSTEM

MODULE

GATE

MODULE

+

GATE

CIRCUITCIRCUIT

VoutVin VoutVin

DEVICEG

n+S D

n+


Major Design ChallengesMicroscopic issues

ultra-high speedsdi i ti d

Macroscopic issuestime-to-marketd i l itpower dissipation and

supply rail dropgrowing importance of interconnect

design complexity (millions of gates)high levels of abstractionsinterconnect

noise, crosstalkreliability,

f t bilit

abstractionsreuse and IP, portabilitysystems on a chip (SoC)

manufacturabilityclock distribution

tool interoperability

Year Tech. Complexity Frequency 3 Yr. Design Staff Size

Staff Costs

1997 0 35 13 M Tr 400 MHz 210 $90 M1997 0.35 13 M Tr. 400 MHz 210 $90 M1998 0.25 20 M Tr. 500 MHz 270 $120 M1999 0.18 32 M Tr. 600 MHz 360 $160 M


2002 0.13 130 M Tr. 800 MHz 800 $360 M

Assignment

Reading Assignment 1.3


ece407/507 vlsi digital circuits lecture 01: introductionece507/lecture_1.pdf · vlsi digital...

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