cu pillar bump a 50µm pitch fine pitch vertical probe card ...€¦ · cu‐pillar bump probing:...
TRANSCRIPT
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Cu‐Pillar Bump Probing: Utilizing a 50µm Pitch Fine Pitch Vertical
Probe Card Technology
Cu‐Pillar Bump Probing: Utilizing a 50µm Pitch Fine Pitch Vertical
Probe Card Technology
Senthil Theppakuttai, Ph.D.SV Probe
Todd TsaoASE Global
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OutlineOutline
• Introduction to Fine Pitch Copper Pillar Bumps
• Testing/Probing Requirements
• Test Vehicle Design
• Probe Card Challenges
• Test Data
• Summary
• Future Work
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IntroductionIntroduction• Next Generation Flip Chip Interconnects
– 2.5, 3D Integration Process
• Electroplated Copper Pillars with Solder Caps
• Advantages– Fine Pitch Capability
– Increased I/O Density
– Improved Electrical & Thermal Performance• Superior Electro‐Migration
– Higher Reliability at Lower Cost
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Memory
Processor
Copper pillar/post(< 50 um pitch)
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Testing/Probing challengesTesting/Probing challenges
• Copper Pillar Bump Testing/Probing Challenges– P/C Availability at 50µm & Below in Array Configuration
– Small Bump Diameter• Need Very Low Probing Force
• Need Very Good Tip Alignment
– Need Probe Compliance to Accommodate Bump to Bump Variation Across Wafer
– Bump Material: Lead‐free Solder
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Goals/ObjectiveGoals/Objective• Evaluation Objective/Scope
– Probe Card Feasibility at 50µm Array
– Copper Pillar Bump Probing Evaluation• Bump Damage Assessment
• Electrical, Thermal & Mechanical Characterization
• Post Wafer Probing Tests for Reliability
• Test Equipment– Test Chip Designed by ASE
– LT50 Probe Card by SV Probe
– P‐12 XLn Prober, HP93000 Tester
– Microscope, SEM, Veeco Profilometer
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Equipment Utilized
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DockingDockingProberProber TesterTester
SEMSEM VeecoVeeco
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Test Chip DesignTest Chip Design• Test Chip Design Details
– 50µm Pitch
– Array Configuration, 4 Groups, 500 Points Total
– Daisy‐chain Resistance Measurement
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Optical PictureOptical PictureArray LayoutArray Layout
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Cu‐Pillar Structure
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Side ViewSide View
Initial Bump Height : ~25 +/‐3µmInitial Bump Height : ~25 +/‐3µm
25µm2525µµmm
25µm2525µµmmCu‐Pillar
Pb‐Free Bump
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LogicTouchTM Vertical Probing TechnologyLogicTouchTM Vertical Probing Technology
1. Probes2. Space Transformer (MST)3. PCB
1.1. ProbesProbes2.2. Space Transformer (MST)Space Transformer (MST)3.3. PCBPCB
– Technology Capable of Probing 50µm Arrays– Technology Scalable to 40µm Pitch
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PROBE CARD CHALLENGESPROBE CARD CHALLENGES
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Scalability ChallengesScalability Challenges• Space Transformer Availability at 50µm Pitch Array
– Based on Standard Thin Film Technology Capability, Difficult to Achieve Escapement Required for Routing
– Need Pad on Via at Pitch & Hence MLC/MLO not Feasible for Array Configurations at 50µm Pitch
– New Type of Interconnect was Developed Internally – the Modular Space Transformer or MSTTM
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MST™MSTMST™™
PCBPCBPCB
PHPHPH
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Scalability ChallengesScalability Challenges• Guide Plate Wall Strength
– Reduced Wall Strength due to Reduced Wall Thickness due to the Spatial Constraints at 50µm Pitch
– Probes Designed to Minimize Loading on Guide Plate (FEA)
– Stress/Life Tests at Max OT to Ensure Wall Integrity
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Lower Guide PlateLower Guide PlateLower Guide Plate
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Guide Plate ReflectivityGuide Plate Reflectivity
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Control SampleControl Control SampleSample
AR SurfaceAR AR
SurfaceSurface
P‐12 Prober Pictures: High Mag, Light Level 120, Focused 7‐8 mils above Die SurfaceP‐12 Prober Pictures: High Mag, Light Level 120, Focused 7‐8 mils above Die Surface
Veeco Reflectivity MeasurementVeeco Reflectivity Measurement
P‐12 ProberP‐12 Prober
• The MEMS Guide‐plates Used in LT50 Probe Cards have a Smooth & Polished Surface Finish– Lighting Adjustments may be Required During Probe Card
Setup at PCA & Prober• Various Anti‐reflective Surface Treatments were
Evaluated to Reduce Normal Reflection– Surface Scattering (Textured/Engineered Surface)– Interference (Thin Films/Coatings)
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PROBE CARD DATAPROBE CARD DATA
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Probe ForceProbe Force• Contact Force of 2.5 gf @ 50µm OT
• Preferred Bump Probing OT 25 to 40µm– Minimize Bump Damage
– Accommodate Bump Co‐planarity Across Wafer
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Tip AlignmentTip Alignment
• Probe Tip Alignment – 0.3 mil Radial
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PlanarityPlanarity
• Probe Planarity 0.45 mil (12µm)
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Resistance on GoldResistance on Gold
• Max Total Resistance is 3.2 Ohms (includes Cres& Path Resistance through PH, MST & PCB)
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COPPER PILLAR BUMP PROBINGCOPPER PILLAR BUMP PROBING
2020
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Test MethodTest Method
25µm25µm25 µm
Si
25µm25µm
In Out
Daisy Chain Bump Structure
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Probe MarkProbe Mark
Before Contact After Contact
*Over‐Drive: 40µm# probing: 2 TDs
Probe Mark Area Under 30%
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Tests in ProcessTests in Process• Electrical Tests
– Cres, Leakage Characterization vs. OT, # TD
• Mechanical – Probe Mark Size Characterization vs. OT, # TD
– Bump Damage Assessment vs. OT, # TD
• Thermal– Effect of Temperature (Hot, Room & Cold) on:
• Probe Card Performance (e.g. Cres Stability, Cleaning etc.)
• Probe Mark / Bump Damage
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Summary / ConclusionSummary / Conclusion• To Address Test Challenges Associated with Fine Pitch Copper
Pillar Bump Probing– A Test Chip with 25µm Pillar Bumps at 50µm Pitch Array was Designed &
Fabricated
– An LT50 Probe Card at 50µm Pitch Array was Built with SV Probe’s Proprietary ST Technology
• Test / Evaluation– Good Probe Card Tip Alignment & Planarity
– Max Total Resistance through P/C Including MST was 3.2 Ohms
– P/C Passed Opens/Shorts Test on Copper Pillar Bumps
– Probe Mark was < 30% of Bump Area at 40µm OT at 2 TDs
• Successful Collaboration between ASE & SV Probe & the Preliminary Evaluation Results to Date have been Positive
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