cvvvbvbadence lab 1 report

8/12/2019 Cvvvbvbadence Lab 1 Report

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1]I-V characteristics of NMOS & PMOS :-

Objective:-

Plot the I-V characteristics of NMOS and PMOS transistors.

1. ID vs. VDS with varying VGS for both NMOS & PMOS.

Circuit for NMOS:-


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Output graph for NMOS :-


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Circuit Diagram of PMOS:-


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Output graph for PMOS:-

Inference:-

Conclusion:-


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2] CMOS INVERTER:-

Objective:-

1. Transient analysis of CMOS inverter.

2. Transfer characteristic of CMOS inverter.

3. Transfer characteristics of CMOS inverter with effect of aspect ratio.

4. Delay of CMOS inverter.

5. Power dissipation of CMOS inverter.

Circuit Diagram:-


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Output graph for transient analysis of CMOS inverter:-


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Output graph of transfer characteristics of CMOS inverter:-


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Output graph for width variation:-

Analysis:-

1. Delay of CMOS inverter:-

2. Power dissipation of CMOS inverter:-

Inference:-

Conclusion:-


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3] Channel length modulation:-

Objective:-

1. To study effect of channel length modulation.

2. Calculation of the lambda parameter.

3. Calculation of output resistance.

Circuit diagram:-


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Output graph:-

Analysis:-

1. channel length modulation parameter lambda:-

2. Output resistance ro:-


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Inference:-

Conclusion:-

Reference:-

CMOS Digital integrated circuitsby sung-mo-kang.


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4] Body bias effect

Objective:-

1. To observe the body bias effect on drain current.

2. To calculate the vt for different values of VSB.

Circuit Diagram:-


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Output graph for ID vs VGS wIith varying VSB:-


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Output graph for ID vs VSB:-

Analysis:-

1 .vt for the different value of vsb:-

Inference:-

Conclusion:-

Reference:- microelectronics circuits by sedra & smith.


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5]CMOS inverter symbol:-

Objective:-

1.to study how to create and use symbol.

Schematic for creating CMOS inverter symbol:-


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CMOS inverter symbol:-


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Application of the symbol:-


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Output graph:-

Inference:-

Conclusion:-


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6]NAND:-

Objective:-

1. To create the NAND gate symbol & study its functionality.

2. to calculate the delay & power dissipation

.

Schematic to create NAND symbol:-


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Symbol of NAND gate:-


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Application of NAND symbol:-


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Output graph:-

Analysis:-

1.delay calculation:-

2.power dissipation :-

Inference:-

Conclusion:-


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7]NOR:-

Objective:-

1. To create the NOR gate symbol & study its functionality.

2. to calculate the delay & power dissipation

Schematic to create NOR symbol:-


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Symbol of NOR gate:-


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Application of NOR symbol:-


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Output graph:-

Analysis:-

1. delay calculation:-

2. power dissipation :-

Inference:-

Conclusion:-


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8]Chain of inverter:-

Objective:-

1. To calculate delay for chain of inverter.

2. To study the functionality.

Circuit Diagram:-


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Output graph:-

Analysis:-

1.delay calculation:-

2.Power calculation:-

Inference:-

Conclusion:-


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9] Noise margin for inverter:-

Objective:-

1. To calculate the noise margin for CMOS inverter

Circuit diagram of CMOS inverter:-


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Output graph for noise margine:-

Analysis:-

Noise margin:-

Inference:-

Conclusion:-

cvvvbvbadence lab 1 report

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