DATA PATH OF A PROCESSOR(MIPS)

Module 1.1 : Elements of computer system

UNIT 1

WHAT IS DATA PATH?

The collection of state elements, computation elements, and interconnections that together provide a conduit for the flow and transformation of data in the processor during execution.

TYPES OF ISA IN MIPS

• Broadly MIPS consists of three types of ISA:

– R-Type : arithmetic-logical instructions: add, sub, and, or, slt

– I-type : memory-reference instructions: lw, sw

– J – type : control flow instructions: beq, j

BASIC WORKING

• Generic Implementation:– Use the program counter (PC) to

supply instruction address.

– Get the instruction from memory

– Read registers

– Use the instruction to decide exactly what to do

ABSTRACT VIEW OF A MIPS IMPLEMENTATION

• Instructions start by using PC to supply instruction address to the Instruction Memory.

• After the instruction is fetched, the register operands used by the instruction are specified by the instruction fields

• Once the register operands are fetched, they can be operated upon, by the ALU to:– Compute a memory address for Load/store instructions– Compute an arithmetic result for Arithmetic instructions, or – Compute the address of next instruction for branch instructions

• For Arithmetic/logical instructions, the result from ALU must be written to a register.

• For Load/Store operations, the ALU result is used as an address to either store a value to a register in the bank or to load from a register

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

Step 3 Step 4

Step 1 : Instructions start by using PC to supply instruction address to the Instruction Memory.

Step 2

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

Step 1Step 3 Step 4

Step 2 : After the instruction is fetched, the register operands used by the instruction are specified by the instruction fields

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

Step 1Step 2

Step 4

Step 3: Once the register operands are fetched, they can be operated upon, by the ALU to:– Compute a memory address for Load/store instructions– Compute an arithmetic result for Arithmetic instructions, or – Compute the address of next instruction for branch instructions

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

Step 1 Step 2

Step 4 : For Load/Store operations, the ALU result is used as an address to either store a value to a register in the bank or to load from a register

Step 3

MIPS - SIMPLE IMPLEMENTATION• Lets look at which data path elements are needed for each class of instructions

PC

Instructionmemory

Instructionaddress

Instruction

a. Instruction memory b. Program counter

Add Sum

c. Adder

We first need a place to store instructions – The instruction memory holds and supplies instructions, given an address

The address of the instruction also must be kept in a state element, called the Program Counter

Lastly, we need an Adder to increment the PC to the address of the next instruction

MIPS - SIMPLE IMPLEMENTATIONALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

To implement R-type instructions, we need the Register file, and the ALU. We need to read two data words from the register file and write one data word into the register file.

To read, we need an input to the file that specifies the address (5 bits = 25 = 32-bit register).

To write, we need two inputs – register number, and data value. Writes are controlled by RegWrite control signal, which must be asserted for the write to occur on clock edge.

ALU control : Refer to ppt on Alu and control signals

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

THE DATAPATH FOR R-TYPE

Instruction

DATAPATH COMPONENTS FOR I-TYPE LOAD/STORE INSTRUCTIONS

• General form: – lw $t1, offset_value ($t2) or sw $t1, offset_value ($t2)

• These instructions compute a memory address by adding the base register $t2, to the 16-bit signed offset field contained in the instruction.

• If the instruction is a Store, the value to be stored must also be read from the register file where it resides in $t1. If the instruction is a load, the value read from memory must be written into the register file, in a specific register $t1.

• In any case, we will need both register file and the ALU shown in the datapath for R-type instructions.

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address

• In addition, we need a unit to sign-extend the 16-bit offset field in the instruction to a 32-bit signed value; and a memory unit to read from or write to. The data memory must be written on store instructions. Hence the DM unit has both MemRead and MemWrite control signals

THE DATAPATH FOR LOAD/STORE

16 32Sign

extend

b. Sign-extension unit

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

Instruction

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address

• The datapath for load/store does a Register access, followed by a memory address calculation, then a read/write from data memory unit and finally, a write back into the register file if the instruction is a load.

DATAPATH FOR I-TYPE CONTROL FLOW INSTRUCTIONS

• General form: – beq $t1, $t2, offset

• Three operands, 2 registers that are compared for equality and one 16-bit offset that computes the branch target address relative to branch instruction address.

• To implement beq, we must compute the branch target address by adding the sign-extended offset field of the instruction to the PC.

• Keep in mind (Chapter 3):– The MIPS ISA specifies that the base for branch address calculation is the

address of the instruction following the branch. PC+4 (address of the next instruction) is the base for computing branch target address.

– The ISA also states that the offset field is shifted left 2 bits so that it is a word offset. This shift increases the effective range of the offset field by a factor of 4.

• In addition to computing the branch target address, we must also determine whether the next instruction is the next one in sequence or the instruction at the branch target address – I.e, we need to see if the branch is taken, based on comparing the register contents.

DATAPATH FOR BRANCH

• ALU is used to to evaluate the branch condition; • The Adder is used to compute the branch target address as the sum of PC +4

and the sign-extended lower 16-bits of the instruction (the branch displacement) shifted left by 2 bits.

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

THE COMPLETE DATAPATH

• Building blocks for the 3 instruction types• To share a data element between two instruction classes, we need to allow

multiple connections to the input of an element and have a control signal to select among inputs

• Use multiplexors to stitch it all together

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

• Notice the 7 control signals i.e., PCsrc, ALUsrc, ALU operation, MemWrite, MemtoReg, MemRead, RegWrite