d. de venuto,politecnico di bari 0 the cmos common-gate amplifier: (a) circuit; (b) small-signal...

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D. De Venuto, Politecnico di Bari 1 The CMOS common-gate amplifier: (a) circuit; (b) small- signal equivalent circuit; and (c) simplified version of the circuit in (b). CMOS common-gate amplifier

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D. De Venuto, Politecnico di Bari1

The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).

CMOS common-gate amplifier

D. De Venuto, Politecnico di Bari2

The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.

The source follower

D. De Venuto, Politecnico di Bari3

(a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic;

NMOS amplifier with an active load

D. De Venuto, Politecnico di Bari4

NMOS amplifier with an active load (2)

(c) transfer characteristic.

D. De Venuto, Politecnico di Bari5

The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and (c) transfer characteristic.

NMOS amplifier with a depletion load

D. De Venuto, Politecnico di Bari6

Small-signal equivalent circuit of the depletion-load amplifier, incorporating the body effect of Q2.

Small-signal equivalent circuit

D. De Venuto, Politecnico di Bari7

(a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.

The CMOS inverter

D. De Venuto, Politecnico di Bari8

Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; and (c) equivalent circuit.

Operation of the CMOS inverter

D. De Venuto, Politecnico di Bari9

Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; and (c) equivalent circuit.

Operation of the CMOS inverter (2)

D. De Venuto, Politecnico di Bari10

The voltage transfer characteristic of the CMOS inverter.

Voltage transfer characteristic

D. De Venuto, Politecnico di Bari11

Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms;

Dynamic operation

D. De Venuto, Politecnico di Bari12

Dynamic operation (2)

(c) trajectory of the operating point as the input goes high

and C discharges through the QN;

(d) equivalent circuit during the capacitor discharge.

D. De Venuto, Politecnico di Bari13

The CMOS transmission gate.

CMOS transmission gate

D. De Venuto, Politecnico di Bari14

Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) vA is positive; (b) vA is negative.

Transmission gate (2)

D. De Venuto, Politecnico di Bari15

(a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected to the substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).

High frequency equivalent model

D. De Venuto, Politecnico di Bari16

Determining the short-circuit current gain Io/Ii.

Short circuit current gain