datasheet - stw12n170k5 - st.com · • industry’s best fom (figure of merit) • ultra-low gate...
TRANSCRIPT
TO-247
12
3
D(2, TAB)
G(1)
S(3)AM01475V1
FeaturesOrder code VDS RDS(on) max. ID PTOT
STW12N170K5 1700 V 2.9 Ω 5 A 250 W
• Industry’s lowest RDS(on) x area• Industry’s best FoM (figure of merit)• Ultra-low gate charge• 100% avalanche tested• Zener-protected
Applications• Switching applications
DescriptionThis very high voltage N-channel Power MOSFET is designed using MDmesh™ K5technology based on an innovative proprietary vertical structure. The result is adramatic reduction in on-resistance and ultra-low gate charge for applicationsrequiring superior power density and high efficiency.
Product status link
STW12N170K5
Product summary
Order code STW12N170K5
Marking 12N170K5
Package TO-247
Packing Tube
N-channel 1700 V, 2.3 Ω typ., 5 A, MDmesh™ K5 Power MOSFET in a TO‑247 package
STW12N170K5
Datasheet
DS12847 - Rev 1 - November 2018For further information contact your local STMicroelectronics sales office.
www.st.com
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VGS Gate-source voltage ±30 V
IDDrain current at TC = 25 °C 5 A
Drain current at TC = 100 °C 3 A
IDM(1) Drain current (pulsed) 10 A
PTOT Total power dissipation at TC = 25 °C 250 W
dv/dt(2) Peak diode recovery voltage slope 4.5 V/ns
dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns
TJ Operating junction temperature range-55 to 150 °C
Tstg Storage temperature range
1. Pulse width limited by safe operating area2. ISD ≤ 5 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS
3. VDS ≤ 1360 V
Table 2. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 0.5 °C/W
Rthj-amb Thermal resistance junction-amb 50 °C/W
Table 3. Avalanche characteristics
Symbol Parameter Value Unit
IAR(1) Maximum current during repetitive or single pulse avalanche 1.7 A
EAS(2) Single pulse avalanche energy 1000 mJ
1. Pulse width limited by TJmax
2. Starting TJ = 25 °C, ID = IAR, VDD = 50 V
STW12N170K5Electrical ratings
DS12847 - Rev 1 page 2/14
2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4. Static
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 1700 V
IDSS Zero gate voltage drain current
VGS = 0 V, VDS = 1700 V 1 µA
VGS = 0 V, VDS = 1700 V,
TC = 125 °C(1)50 µA
IGSS Gate body leakage current VDS = 0, VGS = ± 20 V ±10 µA
VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 4 5 V
RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 2.5 A 2.3 2.9 Ω
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance
VGS = 0 V, VDS = 100 V, f = 1 MHz
- 1380 - pF
Coss Output capacitance - 73 - pF
Crss Reverse transfer capacitance - 2.7 - pF
Co(tr)(1) Time-related equivalentcapacitance
VDS = 0 V to 1360 V, VGS = 0 V- 65 - pF
Co(er)(2) Energy-related equivalentcapacitance - 26 - pF
RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 3.8 - Ω
Qg Total gate charge VDD = 1360 V, ID = 5 A
VGS = 0 to 10 V
(see Figure 15. Test circuit for gatecharge behavior)
- 37 - nC
Qgs Gate-source charge - 10 - nC
Qgd Gate-drain charge - 19 - nC
1. This parameter is defined as a constant equivalent capacitance giving the same charging time as COSS when VDS increasesfrom 0 to 80% VDSS.
2. This parameter is defined as a constant equivalent capacitance giving the same stored energy as COSS when VDSincreases from 0 to 80% VDSS.
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 850 V, ID = 2.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 14. Test circuit forresistive load switching times andFigure 19. Switching timewaveform)
- 22 - ns
tr Rise time - 7 - ns
td(off) Turn-off delay time - 74 - ns
tf Fall time - 51 - ns
STW12N170K5Electrical characteristics
DS12847 - Rev 1 page 3/14
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD Source-drain current - 5 A
ISDM Source-drain current (pulsed) - 10 A
VSD(1) Forward on voltage ISD = 5 A, VGS = 0 V - 1.5 V
trr Reverse recovery time ISD = 5 A, VDD = 60 V,
di/dt = 100 A/µs
(see Figure 16. Test circuit forinductive load switching and dioderecovery times)
- 350 ns
Qrr Reverse recovery charge - 3.91 µC
IRRM Reverse recovery current - 22.3 A
trr Reverse recovery time ISD = 5 A,VDD = 60 V,
di/dt = 100 A/µs, TJ = 150 °C
(see Figure 16. Test circuit forinductive load switching and dioderecovery times)
- 481 ns
Qrr Reverse recovery charge - 5.07 µC
IRRM Reverse recovery current - 21.0 A
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
Table 8. Gate-source Zener diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)GSO Gate-source breakdown voltage IGS = ±1 mA, ID = 0 A 30 - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need foradditional external componentry.
STW12N170K5Electrical characteristics
DS12847 - Rev 1 page 4/14
2.1 Electrical characteristics (curves)
Figure 1. Safe operating area
GADG191120181151SOA
10 1
10 0
10 -1
10 -1 10 0 10 1 10 2 10 3
ID (A)
VDS (V)
tp =10 µs
tp =100 µs
tp =1 ms
tp =10 ms
Operation in this areais limited by RDS(on)
Single pulse, TC = 25 °C,TJ ≤ 150 °C, VGS = 10 V
Operation in this areais limited by RDS(on)
Figure 2. Thermal impedance
Figure 3. Output characteristics
GADG191120181130OCH
8
7
6
5
4
3
2
1
00 6 12 18 24 30
ID (A)
VDS (V)
VGS = 9, 10 V
VGS = 8 V
VGS = 7 V
VGS = 6 V
Figure 4. Transfer characteristics
GADG211120180929TCH
8
7
6
5
4
3
2
1
02 3 4 5 6 7 8 9
ID (A)
VGS (V)
VDS = 20 V
Figure 5. Gate charge vs gate-source voltage
GADG191120181138QVG
1200
1000
800
600
400
200
0
12
10
8
6
4
2
00 6 12 18 24 30 36
VDS (V)
VGS (V)
Qg (nC)
VDS
VDD = 1360 V, ID = 5 A
Qgd
Qg
Figure 6. Static drain-source on-resistance
GADG191120181132RID
2.40
2.35
2.30
2.25
2.200 1 2 3 4 5
RDS(on) (Ω)
ID (A)
VGS = 10 V
STW12N170K5Electrical characteristics (curves)
DS12847 - Rev 1 page 5/14
Figure 7. Normalized gate threshold voltage vstemperature
GADG191120181133VTH
1.1
1.0
0.9
0.8
0.7
0.6-75 -25 25 75 125
VGS(th) (norm.)
Tj (°C)
ID = 100 µA
Figure 8. Normalized on-resistance vs temperature
GADG191120181133RON
2.2
1.8
1.4
1.0
0.6
0.2-75 -25 25 75 125
RDS(on) (norm.)
Tj (°C)
VGS = 10 V
Figure 9. Normalized V(BR)DSS vs temperature
GADG191120181133BDV
1.08
1.04
1.00
0.96
0.92
0.88-75 -25 25 75 125
V(BR)DSS (norm.)
Tj (°C)
ID = 1 mA
Figure 10. Source-drain diode forward characteristics
GADG191120181131SDF
1.0
0.9
0.8
0.7
0.6
0.51 2 3 4
VSD (V)
ISD (A)
TJ = 150 °C
TJ = 25 °C
TJ = -50 °C
Figure 11. Capacitance variations
GADG201120181046CVR
10 4
10 3
10 2
10 1
10 0
10 -1 10 0 10 1 10 2 10 3
C (pF)
VDS (V)
CISS
COSS
CRSS
f = 1 MHz
Figure 12. Maximum avalanche energy vs TJ
GADG201120181049EAS
1000
800
600
400
200
0-50 0 50 100
EAS (mJ)
TJ (°C)
Single pulse, ID = 1.7 A, VDD = 50 V
STW12N170K5Electrical characteristics (curves)
DS12847 - Rev 1 page 6/14
Figure 13. Output capacitance stored energy
GADG201120181049EOS
30
20
10
00 400 800 1200 1600
EOSS (µJ)
VDS (V)
STW12N170K5Electrical characteristics (curves)
DS12847 - Rev 1 page 7/14
3 Test circuits
Figure 14. Test circuit for resistive load switching times
AM01468v1
VD
RG
RL
D.U.T.
2200μF VDD
3.3μF+
pulse width
VGS
Figure 15. Test circuit for gate charge behavior
AM01469v10
47 kΩ
2.7 kΩ
1 kΩ
IG= CONST100 Ω D.U.T.
+pulse width
VGS
2200μF
VG
VDD
RL
Figure 16. Test circuit for inductive load switching anddiode recovery times
AM01470v1
AD
D.U.T.S
B
G
25 Ω
A A
B B
RG
GD
S
100 µH
µF3.3 1000
µF VDD
D.U.T.
+
_
+
fastdiode
Figure 17. Unclamped inductive load test circuit
AM01471v1
VD
ID
D.U.T.
L
VDD+
pulse width
Vi
3.3µF
2200µF
Figure 18. Unclamped inductive waveform
AM01472v1
V(BR)DSS
VDDVDD
VD
IDM
ID
Figure 19. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STW12N170K5Test circuits
DS12847 - Rev 1 page 8/14
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitionsand product status are available at: www.st.com. ECOPACK® is an ST trademark.
STW12N170K5Package information
DS12847 - Rev 1 page 9/14
4.1 TO-247 package information
Figure 20. TO-247 package outline
0075325_9
STW12N170K5TO-247 package information
DS12847 - Rev 1 page 10/14
Table 9. TO-247 package mechanical data
Dim.mm
Min. Typ. Max.
A 4.85 5.15
A1 2.20 2.60
b 1.0 1.40
b1 2.0 2.40
b2 3.0 3.40
c 0.40 0.80
D 19.85 20.15
E 15.45 15.75
e 5.30 5.45 5.60
L 14.20 14.80
L1 3.70 4.30
L2 18.50
ØP 3.55 3.65
ØR 4.50 5.50
S 5.30 5.50 5.70
STW12N170K5TO-247 package information
DS12847 - Rev 1 page 11/14
Revision history
Table 10. Document revision history
Date Version Changes
20-Nov-2018 1 First release.
STW12N170K5
DS12847 - Rev 1 page 12/14
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1 TO-247 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
STW12N170K5Contents
DS12847 - Rev 1 page 13/14
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
STW12N170K5
DS12847 - Rev 1 page 14/14