delay buffer

8/3/2019 Delay Buffer

http://slidepdf.com/reader/full/delay-buffer 1/29

CMOS Circuit Design for CMOS Circuit Design for Minimum Dynamic Power and Minimum Dynamic Power and

Highest Speed Highest Speed

Tezaswi Raja, Dept. of ECE, Rutgers UniversityV ishwani D. Agrawal, Dept. of ECE, Auburn University

Michael L. Bushnell, Dept. of ECE, Rutgers University

Research Funded by: A National Science Foundation Grant



Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 2

Talk OutlineTalk Outline

M otivationObjective

Prior Work New ApproachResultsConclusion and Future Work




Mo tivati onMo tivati onPow er c o nsumpti o n due t o glitches can exceed 30-40% of to tal p ow er c o nsumpti o n.

Existing linear pr o gramming techniques eliminateglitches, but may insert delay bu ff ers w hen ov erallcircuit delay is c o nstrained.

Delay bu ff ers c o nsume p ow er themsel v es and thusreduce p ow er sa v ing ± als o chip area increases.

Ex ample: c1355, a 619-gate circuit needed 224 buffers-- 36 % increase in gates ± for 42% power saving and no IO delay increase.




Pr ob lem StatementPr ob lem StatementFind a linear program (LP) to determinegate delays in a C M OS circuit such that:

All glitches are eliminated No delay buffers are inserted in the circuitCircuit operates at the highest possible speed

permitted by the device technology.

N ote: The objective is to minimize switching power. Hence, noattempt is made to reduce short-circuit and leakage power, which isan order of magnitude lower for present CMOS technologies; thosecomponents of power may be addressed in the future research.




CMOS P ow e r Dissipati onCMOS P ow e r Dissipati onS h o rt circuit p ow erLeakage p ow er (I DDQ )Dynamic p ow er

Essential transiti o nsGlitchesEach transiti o n dissipates C V 2 /2

S h o rt circuit and leakage p ow er

co mp o nents are at least an o rder of magnitude l ow er than the dynamic p ow erin present day techn o lo gies.

V

C




Wh at A r e Glitc hes?Wh at A r e Glitc hes?

Glitches o ccur due t o di ff erential (unbalanced)path delays.Glitches are transients that are unnecessary fo rthe c o rrect f uncti o ning of the circuit.Glitches w aste p ow er in CMO S circuits.

Delay =12

2




Glitc h Supp r essi onGlitc h Supp r essi onDi ff erential P ath Delay

P ath P1

P ath P 2

Di ff erential Delay = |delay ( P1 ) ± delay ( P 2 )|; it is the w idth of the maximum p o tential glitch at the gate o utput.

F o r c o mplete glitch suppressi o n: fo r each gate,inertial delay > differential delay

T o satis f y this c o nditi o n, pre v io us l ow -p ow er design meth o dsinsert delay bu ff ers in the circuit.Pow er w ill be f urther reduced i f glitch suppressi o n c o uld beachie v ed w ith o ut bu ff ers.




Ex ample: Why Use Buffe r s?Ex ample: Why Use Buffe r s?

Delay unit is the smallest delay p o ssible fo r a gate in agiv en techn o lo gy.Critical P ath is the l o ngest delay path in the circuit anddetermines the speed of the circuit.

1

1

1

Critical path delay = 3




For glitch free operation of first gate: Differential delay at inputs e inertial delayOK

1

1

1

Ex ample (c ont.)Ex ample (c ont.)0

0

time




1

1

1

Ex ample (c ont.)Ex ample (c ont.)

For glitch free operation of second gate: Differential delay at inputs e inertial delayOK

1

0




1

1

1


For glitch free operation of third gate: Differential delay at inputs e inertial delayN ot true for gate 3

2

0




1

1

1


F o r glitch f ree o perati o n w ith n o IO delay increase: Must add a delay buffer.

Buffer is necessary for conventional gate design ± only gate output delay is controllable.

2

11




1

1

Cont r o llab le Input Dela y GatesCont r o llab le Input Dela y Gates

A ssume gate input delays t o be c o ntr o llable

Glitches can be suppressed w ith o ut bu ff ers

2

0

1

2




Dela y Mod el f o r a Ne w GateDela y Mod el f o r a Ne w Gate

S eparate the o utput (inertial) and input delayco mp o nents.d 3 - o utput delay of the gate.d 3,1 - input delay of the gate al o ng path f r o m 1 to 3.

Gate design is f easible and is under de v elo pment. ..T echn o lo gy c o nstraint: input delay di ff erence has anupper b o und, w hich w e de f ine as G ate Input Differential

Delay Upper Bound ( u b ).

d 3,1 + d 33

1

2 d 3,2 + d 3




Gate Input Diffe r ential Dela y Uppe r Gate Input Diffe r ential Dela y Uppe r Boun d (Boun d (u u bb ))

I t is a measure of the maximum difference in delay of any two IO paths through the gate, that can be designed in a givenCM O S technology.Arbitrary input delays cannot be realized in practice due to thetechnology limitation at the transistor and layout levels.The bound u b is the limit of flexibility allowed by thetechnology to the designer at the transistor and layout levels.The following feasibility condition must be imposed while

determining delays for glitch suppression:

00 ee d d i, j i, j ee uu bb




A Ne w Linea r Pr og r am A Ne w Linea r Pr og r amC o ntains fo llow ing c o mp o nents

V ariablesGate inertial delay v ariables (d i)Input delay v ariables (d i,j )T iming w ind ow v ariables

C o nstraintsGate delay c o nstraintsGate input delay upper b o und c o nstraintsDi ff erential delay c o nstraintsMaximum delay c o nstraints

Objecti v e f uncti o nL et us consider a simple example combinational circuit.




6

Ne w LP Ex ampleNe w LP Ex ample51

72

3

4

G ate inertial delay variables d 5 ..d 7 G ate input delay variables d i, j for every path through gate ifrom input jCorresponding window variables t 5 ..t 7 and T 5 ..T 7 .

d 5 ,1 + d 5

d 7 ,4 + d 7

d 5 ,2 + d 5

d 6 ,2 + d 6

d 6 ,3 + d 6

d 7 ,5 + d 7

d 7 ,6 + d 7




6

Ne w LP Ex ample (c ont.)Ne w LP Ex ample (c ont.)51

72

3

4

d 5 ,1 + d 5

d 7 ,4 + d 7

d 5 ,2 + d 5

d 6 ,2 + d 6

d 6 ,3 + d 6

d 7 ,5 + d 7

d 7 ,6 + d 7

Inertial delay constraint for gate 5: d d 55 uu 11Input delay constraints for gate 5:

00 ee d d 5,15,1ee uu bb

00 ee d d 5,25,2ee uu bb




6


72

3

4

d 5 ,1 + d 5

d 7 ,4 + d 7

d 5 ,2 + d 5

d 6 ,2 + d 6

d 6 ,3 + d 6

d 7 ,5 + d 7

d 7 ,6 + d 7

Differential delay constraints for gate 5:T5 > T5 ,1 + d 5 ; t5 < t 5 ,1 + d 5 ; d5 > T5 ± t5 ;T5 > T5 ,2 + d 5 ; t5 < t 5 ,2 + d 5 ;




6


72

3

4

d 5 ,1 + d 5

d 7 ,4 + d 7

d 5 ,2 + d 5

d 6 ,2 + d 6

d 6 ,3 + d 6

d 7 ,5 + d 7

d 7 ,6 + d 7

Differential delay constraints for gate 5:T5 ,1

> T5 + d 5 ,1 ; T 5 ,2> T5 + d 5 ,2 ;

t5 ,1 < t 5 + d 5 ,1 ; t5 ,2 < t 5 + d 5 ,2 ;




6


72

3

4

d 5 ,1 + d 5

d 7 ,4 + d 7

d 5 ,2 + d 5

d 6 ,2 + d 6

d 6 ,3 + d 6

d 7 ,5 + d 7

d 7 ,6 + d 7

IO delay constraint for each PO in the circuit:T7 e maxdelay ;

ma x delay is the parameter which gives the delay of the critical path.This determines the speed of operation of the circuit.




6


72

3

4

d 5 ,1 + d 5

d 7 ,4 + d 7

d 5 ,2 + d 5

d 6 ,2 + d 6

d 6 ,3 + d 6

d 7 ,5 + d 7

d 7 ,6 + d 7

Objecti v e Functi o n: minimize maxdelay ;This gives the fastest and lowest dynamic power consuming circuit, given the feasibility condition for the technology.




S o lution Cu r vesS o lution Cu r ves

u b=0u b=5u b=10u b=15u b=

FastestPo ssibleDesign

Minimum

Dynamicp ow er

Ma x delay

Power

Pow erco nsumedby bu ff ers

Previous solutionswith buffers

N ew so luti o ns




R esultsR esults :: Pr oce du r e OutlinePr oce du r e Outline

C++ Program

AMPL

Power Estimator

Combinational circuit netlist

Results

Constraint-set

Optimized delays




R esults on Feasi b ility Uppe r Boun d (uR esults on Feasi b ility Uppe r Boun d (u bb))

Ma x delay is normalized to the fastest possible circuit design.Each curve is a different benchmark circuit.As we increase u b, the circuit becomes faster.Flexibility required for fastest operation of circuit is proportional to the size of the circuit.




R esults: L owR esults: L ow--P ow e r Desi gnP ow e r Desi gnCircuit Un

optimizedp ow er Optimizedp ow er

N o.

of v ect o rs ma

x delay

N orm.delay u b

c43 2 1 .0 0. 5 2 56 71 4.17 5

1 .0 0.49 56 2 7 1 .58 1 01

.0 0.48 56 17 1

.001 5

c499 1 .0 0. 7 0 5 4 34 2 .2 6 01 .0 0. 7 5 5 4 1 5 1 .00 5

c88 0 1 .0 0.4 8 7 8 45 1 .5 0 1 0

1 .0 0.4 7 7 8 30 1 .00 1 5

c1 355 1 .0 0.4 7 8 7 71 2 .95 1 01 .0 0.4 6 8 7 46 1 .91 1 5




Compa r ison with Conventi onal GateCompa r ison with Conventi onal GateDesi gn (Desi gn ( uu bb =0 ) (R aja=0 ) (R aja et al et al .,., VLSI DesVLSI Des . ` 03 ). ` 03 )

C o n v enti o nal gates V ariable input delay gates

Circuit Pow er ma x delay Bu ff ers Pow er ma x delay u b

c43 2 0.7 2 1 .0 9 5 0.4 8 1 .0 1 5

0.6 2 2 .0 66 0.49 1 .58 1 0

c499 0.9 1 1 .4 4 8 0.7 5 1 .00 1 5

0.7 0 2 .2 0 0. 7 0 2 .2 6 1 0

c88 0 0. 68 1 .0 6 2 0.4 7 1 .00 1 5

0.68 2 .0 34 0.4 8 1 .5 0 1 0

c1 355 0.58 1 .0 22 4 0.4 6 1 .00 1 5

0.5 7 2 .0 1 92 0.4 7 2 .08 1 0




Conclusi onConclusi onMain idea: Minimum dynamic p ow er circuits can be

designed i f gates w ith v ariable input delays are used.

T he ne w design suppresses all glitches w ith o ut any

delay bu ff ers.

S peed of the ne w design depends o n the gate input

delay v ariability all ow ed by the techn o lo gy.

A linear pr o gram s o luti o n dem o nstrates the idea.

Results sh ow a v erage p ow er sa v ings up t o 5 2 %.

Future wo rk: V ariable input delay gate design.




Thank youThank you

delay buffer

Documents