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3/6/98 1 Carnegie Mellon Delay Metrics for the Next 50 Years Larry Pileggi Carnegie Mellon University Department of Electrical and Computer Engineering

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Page 1: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 1

CarnegieMellon

Delay Metrics for the Next 50Years

Larry PileggiCarnegie Mellon University

Department of Electrical and ComputerEngineering

Page 2: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 2

CarnegieMellon Outline

◆ Introduction– Interconnect delay dominance– Back-end models and analyses– Front-end metrics

◆ Elmore delay– Introduced in 1948– Applied to digital IC problems in early 1980’s– Somewhat ineffective for deep submicron (DSM)

◆ Probability Interpretation of Moments (PRIMO)◆ Stable n-Pole Models (SnP)◆ Conclusions

Page 3: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 3

CarnegieMellon

◆ Metal resistance per unit length is increasing, while gate outputresistance is decreasing, with scaling

◆ Average wire lengths are not scaling, so portion of delay associatedwith the interconnect is increasing

◆ Gate delay is further decreasing with increasing metal resistancedue to shielding effects

Interconnect Dominance

Page 4: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 4

CarnegieMellon

Back-end Analyses

Extraction

Physical Design

Test Generation

Design Verification Timing Verification

Simulation Floorplanning

Logic PartitioningDie Planning

LogicSynthesis

Logic Design andSimulation

Behavioral Level Design

◆ DSM interconnectdominance impacts allaspects of the top-downdesign flow

Back-end

Page 5: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 5

CarnegieMellon

◆ Model order reduction via moment matching can be usedeffectively for interconnect verification

◆ Orthonormalized moments, or Krylov subspace methods wererecently proposed for increased numerical accuracy

Back-end Verification

CalculateMoments ∑

==

n

i

tipeiktY1

)(

...)( 2210 +++= smsmmsY

Page 6: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 6

CarnegieMellon Krylov Reduction Methods

◆ Same as momentmatching if we haveinfinite precision

◆ Can capture dozensof dominant poles

◆ Approximations tothe 10’s of gigahertzis straightforward

◆ Some issues remainto be solved withregard to passivity

exact

PRIMA

MPVL

Frequency (GHz)10 20 300.00

0.05

0.10

0.15

0.20

Y11(s)60 poles

1 7

2 8

3 9

4 10

5

6 12

Coupled RLC Lines

11

Page 7: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 7

CarnegieMellon Reduction Methods

◆ But there are very fewapplications which requirethis level of detail

◆ There is a greater need forimproved interconnectmodeling at the front-endand physical design levels

Page 8: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 8

CarnegieMellon

Back-end Analyses

Extraction

Physical Design

Test Generation

Design Verification Timing Verification

Simulation Floorplanning

Logic PartitioningDie Planning

LogicSynthesis

Logic Design andSimulation

Behavioral Level Design

◆ Catching all of theinterconnect problems atback-end is too late!

Page 9: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 9

CarnegieMellon

◆ Even with an approximate interconnect topology and values,moment matching and Krylov subspace methods areinappropriate for the front-end of design

◆ Higher order moments can be calculated at a fraction of the cost[RICE] required to calculate the first one

◆ But calculating the delays requires nonlinear iterations

Front-end Metrics

CalculateMoments

∑=

==n

i

tipeikVtv d

DD1

5.0)(

...)( 2210 +++= smsmmsV

Page 10: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 10

CarnegieMellon The Elmore Delay

◆ Metric of choice for front-end applications and performance-driven physical design

◆ Explicit delay metric, yet can still capture interconnect resistanceeffects

◆ Primarily applied to RC tree circuits [Penfield & Rubenstein]R4

C4( )

44)432(2

432114

CRCCCR

CCCCRTD

+++++++=R1 R2 R3

C1 C2 C3

◆ The first moment of the impulse response

...)( 2210 +++= smsmmsH

Page 11: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 11

CarnegieMellon The Elmore Delay

◆ Elmore (1948) proposed to treat the derivative of a monotonicstep response as a PDF, and estimate the median (50% delaypoint) by the mean

100

50f

80 100 100

50f 50f 50f

100 100

50f 150f

100

150f

0.0 200.0 400.0 600.0 800.0 1000.00.0

0.2

0.4

0.6

0.8

1.0

time (ps)

impulse response, h(t)

Page 12: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 12

CarnegieMellon The Elmore Delay

◆ Exact only if h(t) is symmetrical◆ We’ve proven that RC tree impulse responses have positive

skew

0.0 200.0 400.0 600.0 800.0 1000.00.0

0.2

0.4

0.6

0.8

1.0

time (ps)

impulse response, h(t)

mean=134ps

median=100ps

Page 13: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 13

CarnegieMellon Central Moments

◆ The circuit response moments

are related to the Central Moments of the h(t) Distribution by:

◆ Roughly speaking:

266 var2

)(

312133

2122

10n11

mmmmiancemm

mmk

nmeanm kn

knk

−+−=≡−=

=≡= −

=∑

µµ

µµ

25.1

2

3

µµµ MedianMean

Skew−==

∫∞−=→+++=

++++++=

0

2210

1

1 )(!)1(

1

1)( dttht

qmsmsmm

sbsb

sasasH q

q

qmm

nn K

K

K

Page 14: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 14

CarnegieMellon

◆ Skew is a measure of the asymmetry

◆ We proved that all RC interconnect trees:– have unimodal impulse responses, h(t)– and that the h(t) distributions have positive skew

◆ It is then easily shown for such a distribution that

◆ The Elmore delay is an upper bound on the 50% step response delay

Elmore Delay Bound

negative zero positive

MeanMedianMode ≤≤

Page 15: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 15

CarnegieMellon Elmore Bound

◆ Bounds get tighter toward the interconnect loads◆ Repeated convolutions make the distributions more “normal” ---

positive skew decreases toward a constant value

impulse responses100

50f

80 100 100

50f 50f 50f

100 100

50f 150f

100

150f

0.0 100.0 200.0 300.0-1.0e+10

0.0e+00

1.0e+10

2.0e+10

3.0e+10

4.0e+10

time (ps)

Page 16: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 16

CarnegieMellon Finite Rise Times

◆ Any input voltage with a unimodal derivative will also make theresponse more normal (finite tin) --- and the first moment boundstill holds

◆ For finite rise times, the pulse response distribution becomes moresymmetrical as the rise time increases

◆ In the limit, the mean of the pulse response equals the median andthe Elmore delay becomes exact

◆ A large percentage of responses will fall into this category

)( tV in

derivative)( tV in′

response )( tv out′

Page 17: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 17

CarnegieMellon Elmore Errors

-20 0 20 40 60 80 100 120 140 1600

100

200

300

400

500

600

700Elmore

Percentage Error

◆ 1200 response nodes for 700 nets from a 0.35 micron CMOS µP

max

100ps rise times

Page 18: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 18

CarnegieMellon Dominant Time Constant

◆ The Elmore delay as a dominant time constant

◆ If one time constant dominates all others, and there are no lowfrequency zeros, we can approximate the dominant pole by m1

11 τ≈m

∑∑==

−=→−−−−−−=

n

i i

m

i im

n

zpm

pspsps

zszszssH

111

21

21 11

)())((

)())(()(

K

K

7.0)5.0ln( 11 mmtdelay ⋅≅=

◆ This approximation only scales the step response delay by aconstant factor

Page 19: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 19

CarnegieMellon Dominant Time Constant

-40 -20 0 20 40 60 800

100

200

300

400

500

600

7000.7 Elmore

Percentage Error

◆ Max error is reduced, but ramp follower responses are optimistic

max

Page 20: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 20

CarnegieMellon Using The Elmore Delay

◆ Not a good approximation forgeneral DSM trees

◆ Worst case error for busseswith near- and far-end loads

bus

◆ Works well when the rise timeis slow

◆ Or for balanced interconnectssuch as clock trees

clktree

Page 21: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 21

CarnegieMellon µP Clock Tree

◆ Given the following floorplanfor a µP clock tree, optimizethe metal widths in terms ofthe Elmore delays to balancethe skew

◆ R and C per unit lengthvalues are pre-layoutestimates

1.98pF

3.01pF

1.30pF

2.06pF2.18pF

2.75pF1.97pF

1.37pF 0.85pF

287 287

287 287

287 287

287 287

575

575

575

575718 1202

610

610

610

1077

All lengths arein microns

Page 22: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 22

CarnegieMellon µP Clock Tree

◆ Widths for zero Elmoreskew produced 8 ps ofskew with moment-matching models

◆ But correlations foroptimization of signalpaths are not as good

◆ Signal paths requiresmall absolute errors,whereas clock treesrequire only smallrelative errors

4.00

3.01pF

1.30pF

2.06pF2.18pF

2.75pF1.97pF

1.37pF 0.85pF

5.90 5.90

5.95

6.70

12.05.00

5.005.00

5.00

5.00

1.98pF

11.6

9.65

10.7

7.30 5.10

7.30 6.50

Page 23: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 23

CarnegieMellon Higher Order Metrics

◆ For signal nets is wouldappear that we should match3 moments minimally

◆ Capture shapes for goodrelative errors

◆ But we can’t afford nonlineariterations for most delaymetric applications

◆ Two potential approaches:– PRIMO– SnP

impulse responses

0.0 100.0 200.0 300.0-1.0e+10

0.0e+00

1.0e+10

2.0e+10

3.0e+10

4.0e+10

time (ps)

Page 24: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 24

CarnegieMellon PRIMO - Gamma Functions

◆ Extend Elmore’s idea to matching other distribution properties◆ Requires selection of some representative distribution◆ Incomplete gamma is similar to RC impulse responses

◆ Moment matching m1, µ2, and µ3 for time-shifted incompletegamma is provably stable

t

gλ,n(t)

Γ x( ) yx 1– e y– yd

0

∫=gλ n, t( ) λ ntn 1– e λ t–

Γ n( )-------------------------- =

n4 µ2( )3

µ3( )2----------------= λ

2µ2

µ3---------=

Page 25: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 25

CarnegieMellon PRIMO - Gamma Fitting

◆ Since provably stable, agamma integral table canbe used for delays

◆ With rise time a 2D tableis required

◆ For this example the step-delay error is < 1%

0.00e+00 1.00e-10 2.00e-10 3.00e-100.0e+00

2.0e+09

4.0e+09

6.0e+09

8.0e+09

100

50f

80 100 100

50f 50f 50f

100 100

50f 150f

100

150f

time (ps)

exact

m1-shifted gamma

Page 26: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 26

CarnegieMellon Gamma Fitting

◆ Gamma approximationstruggles for some cases

◆ DSM interconnects can havecomplex low frequency zeroeffects

◆ Step delay error isunderestimated by 8% forthis example

100

50f

80 100 100

50f 50f 50f

100 100

50f 150f

100

150f

time (ps)

0.0e+00 2.0e-11 4.0e-11 6.0e-11 8.0e-11 1.0e-100.0e+00

1.0e+11

2.0e+11

3.0e+11

exact

m1-shifted gamma

Page 27: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 27

CarnegieMellon SnP

◆ We can build provablystable n-poleapproximations

◆ Driving point poleapproximations areprovably stable

◆ k’s are fitted bymatching moments atthe response nodes ofinterest

◆ Generates stable n-exponential distributionmodel which permitstable lookup evaluation

RC Tree

...)( 2210 +++= smsmmsI

MomentMatching moments

real, stable,time constants

∑=

−=

n

i

iteikth

1

/)(

τ

Page 28: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 28

CarnegieMellon S2P

◆ A two-pole model, or doubleexponential distributionfunction, can be used with a3D table to evaluate finiterise time response delays

◆ Step delay error is less than1.5% in this example

time (ps)

100

50f

80 100 100

50f 50f 50f

100 100

50f 150f

100

150f

exact

S2P

0.0 100.0 200.0 300.00.0e+00

2.0e+09

4.0e+09

6.0e+09

8.0e+09

Page 29: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 29

CarnegieMellon S2P: Double Exponential

-10 -5 0 5 10 15 20 250

100

200

300

400

500

600

700

800S2P

Percentage Error

◆ CMOS µP example

max

Page 30: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 30

CarnegieMellon S3P

◆ It can be shown thatthree exponentials areminimally required to fitsome unimodal impulseresponses

◆ S2P step delay error is14% in this example

◆ But is a 4D tablepractical?

100

50f

80 100 100

50f 50f 50f

100 100

50f 150f

100

150f

0.0 100.0 200.0 300.0-1.0e+10

-5.0e+09

0.0e+00

5.0e+09

1.0e+10

1.5e+10

2.0e+10

time (ps)

exact and S3P

S2P

Page 31: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 31

CarnegieMellon Inductance

◆ On-chip inductance is becoming a reality for long lines◆ Impulse responses are no longer unimodal◆ Skew measure (µ3) can be used to control damping

R

3pf 3pf 3pfR = 1 ohm/cmL = 0.335 nH/cmC = 0.134 pF/cmZ0 = 50 ohms

5 cm 2.5 cm

0.0 10.0 20.0 30.0 40.0 50.0

-150.0

0.0

150.0

R

µ3 (scaled)Packaging Example

Page 32: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 32

CarnegieMellon RCL Interconnects

2 4 60.0

0.5

1.0

1.5

Time (ns)0

1.34ns

1.01ns

0.75ns

R

3pf 3pf 3pfR = 1 ohm/cmL = 0.335 nH/cmC = 0.134 pF/cmZ0 = 50 ohms

5 cm 2.5 cm

◆ The delays areaccurately predictedby the moment metricsonce the damping iscontrolled

Page 33: Delay Metrics for the Next 50 Years - Donald Pederson · 3/6/98 2 Carnegie Mellon Outline Introduction – Interconnect delay dominance – Back-end models and analyses – Front-end

3/6/98 33

CarnegieMellon Conclusions

◆ Some progress has been made on more accurate delaymetrics

◆ But more work remains to be done for the mostdifficult DSM problems

◆ Similar metrics for coupling are necessary◆ But coupled line responses are provably not unimodal

for the general case