delivering success. modeling 32 v asymmetric ldmos using aurora and hspice level 66 by alhan...

Delivering Success.

Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66

By

Alhan Farhanah, Mohd Shahrul Amran, Albert Victor Kordesch

Device Modeling Department, SILTERRA Malaysia Sdn. Bhd.

2007

ESSDERC 2007 MUNICH2

Delivering Success.

Outline

Aurora and HSPICE Level 66 Background

32V Asymmetric HV MOS Background Modeling Flow for Asymmetric HV

MOS Results and Discussion Self Heating Effect in HV MOS Conclusion


Delivering Success.

Aurora and HSPICE Level 66 Background

Aurora o product of Synopsys Inc for Modeling. o Beside HSPICE Level 66, Aurora also

offers all types of models that normally offered by other products.

Contends for the modeling and SPICE simulation of digital CMOS, analog and RF circuit that operates up to 100V.


Delivering Success.Aurora and HSPICE Level 66

Background (cont’d) HSPICE Level 66 is a proprietary product of

Synopsys.

HSPICE Level 66 model

o self heating, forward and reverse mode, asymmetric parasitic, and bias dependent RDS- based on BSIM4

o primarily targets for LDMOS (Lateral Double Diffused MOSFET) and EDMOS (Extended Drain MOSFET) device technologies.


Delivering Success.

32V Asymmetric HV MOS Background (cont’d) Structure


Delivering Success.

Modeling Flow For Asymmetric HV MOS

Golden Die

Asymmetric Behavior Checking

DC Measurement

AC Measurement

Aurora ExtractionAnd Optimization

Hspice Simulation


Delivering Success.

Modeling Flow For Asymmetric HV MOS (cont’d)Asymmetric Behavior Checking

Purpose - check the asymmetric effect of the transistor.

Measurement - swapping the bias voltage of source and drain for each measurement.

Compare IdVd curve for forward and reverse mode measurement.


Delivering Success.

Long Channel Device(W/L=25u/25u)

Almost similar ID

Modeling Flow For Asymmetric HV MOS (cont’d) Asymmetric Behavior Checking

+++ forward mode___ reverse mode


Delivering Success.Asymmetric Behavior Checking

Short Channel Device (W/L=25u/4.25u)

Significant ID decrease

+++ forward mode___ reverse mode

VGS


Delivering Success.

The results showed that shorter length device exhibits quite significant Id decrease for reverse mode measurement while the long channel device exhibits almost similar Id curve for both modes of measurement

Modeling Flow For Asymmetric HV MOS (cont’d)


Delivering Success.

Modeling Flow For Asymmetric HV MOS (cont’d) DC Measurement Measurements:

o IdVg@low Vdd with different Vbo IdVg@high Vdd with different Vbo IdVd @Vb=0 with different Vg o IdVd @high Vb with different Vg

Before measuring all the modeling devices, Wide Width and small Length transistor with different back biases and different temperatures must be evaluated first


Delivering Success.

To properly model the effect of asymmetric, the modeling structure for CV need to be designed with extra structures compare to symmetric structure.

All the CV modeling structures need to be separated into 2 different structures:

o Source design rule o Drain design rule.

Thus, the CV measurement for asymmetric transistor is almost double compare to symmetric transistor.

Modeling Flow For Asymmetric HV MOS (cont’d) CV Measurement


Delivering Success.

Extraction strategy – almost similar to BSIM4

The preferred mobility model in Level 66 o MOBMOD=0

Source and Drain parameters are not equal. e.g RSW and RDW, RSWMIN and RDWMIN

Both drain side and source side bias dependence parameters of LDD resistance can be optimized.

Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization


Delivering Success.

Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization There are reverse mode parameters available for

optimization i.e ETA0I, ETABI, DSUBI o Too many of these parameters are not

encouraged. Self heating effect can be turned on by setting

SHMOD=1 and RTH0>0. o Strongly advised to set TSHFLAG=1 during the

optimization - internal approximation of self heating effect will be used during the optimization. Hence, the speed of the optimization is significantly improved. In the final step, the optimization can be refined by setting TSHFLAG=0.

When self heating is turned on, the temperature parameters need to be extracted as much as possible before we do extraction for saturation region parameters.


Delivering Success.Modeling Flow For Asymmetric HV

MOS (cont’d) Extraction and Optimization Disadvantages of Level 66 model:

Slower model evaluation -includes internal nodes (solver need to be invoked for every bias point)

There is no reliable way to extract thermal capacitance. Thus, we need to develop a method to include thermal time constant in our model.


Delivering Success.Results and Discussion

W/L = 25um/25um

+++ Meas___ Model


Delivering Success.Results and Discussion (cont’d)

W/L = 25um/4.25um

+++ Meas___ Model



W/L = 25um/25um

+++ Meas___ Model



W/L = 25um/4.25um

+++ Meas___ Model



Idsa

t (u

A/u

m)



Vth

(V

)



+++ Meas___ Model



In this paper, IdVg and IdVd curves for 25um/25um and 25um/4.25um have been used to demonstrate model accuracy.

The model also correctly simulates self heating effect

The model scalability (across W and L) also showed a good agreement with measurement data. Less than 5%.

The accuracy of the AC behavior is excellent. Less than 1%.


Delivering Success.

Self Heating Effect in HV MOSFET

HPWELL

N-DRIFT

POLY

STIN+

STIP+

P-Sub

N-DRIFT

N+

STIHEAT

GateSourc

eDrain

If P is moderate(mW), self heating is not severe sinceit reach its thermal equilibrium with its environment


Delivering Success.

Experimental setup

VG

4.7F

50

VD

oscilloscope

VDD

Pulse Gen

Self Heating Effect in HV MOSFET (cont’d)


Delivering Success.

Dynamic response of HV NMOS to typical gate pulse

VG

VD

Self Heating Effect in HV MOSFET (cont’d)


Delivering Success.

Self Heating Effect in HV MOSFET (cont’d) RTH extraction RTH will be extracted from Aurora by fitting

the data for W=25um and different L. set SHMOD=1 and RTH0>0. This is to ensure that the RTH can be scaled

with L.


Delivering Success.

Transient drain-current characteristics of HV NMOS

y = -0.4502Ln(x) + 13.612

11

11.5

12

12.5

13

13.5

1 10 100 1000Time (us)

I D (

mA

)

Due to SHE


Delivering Success.

Time constant for self heating of HV NMOS

y = 2.3011e-0.0546x

1.0

1.2

1.4

1.6

1.8

2.0

2.2

0 2 4 6 8 10

Time (us)

Delt

a I D (

mA

)

R*C = 1/0.0546R*C = 18.32 us


Delivering Success.

Self Heating Effect in HV MOSFET (cont’d)Extracted time constant and CTH

Time constant is extracted from : y = 2.3011e-0.0546x

where thermal time constant, RTH CTH = 1/0.0546

= 18.32 us From Aurora extraction RTH = 6.85E-03 mºC/W

Hence the extracted thermal capacitance:

CTH = 18.32us/RTH

= 2.67E-03 (W*sec)/ mºC


Delivering Success.Conclusion

Modeling strategies for 32V asymmetric HV MOSFET using Aurora and HSPICE level 66 has been presented

Model shows:o Excellent DC IV results for entire DC bias

rangeo Excellent behavior of junction capacitances

Model scalability (across W and L) also showed good agreement with measurement data. Less than 5%

Correctly simulate SHE

Extraction of Thermal resistance and capacitance by Pulsed gate measurement


Delivering Success.

Thank You

delivering success. modeling 32 v asymmetric ldmos using aurora and hspice level 66 by alhan...

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