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Demands of electronics industry

Last time, we got a quick overview of the silicon MOSFET.

Today, we will examine the state-of-the-art in MOSFET technology, with an eye toward what the expected requirements are for the future.

Keep an eye out for nano-related issues that will crop up….

Ongoing trends: Moore’s (1st) Law

1970 1980 1990 2000100

1k

10k

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1M

10M

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1G

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nsis

tors

/ C

PU

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m]

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The number of components per IC doubles roughly once every 18 months.

Lateral feature sizes have also decreased exponentially with time.

Breaking the 100 nm barrier in production in 2003….

These trends cannot continue forever.

• What will replace traditional Si?

• Why will that replacement occur?

ECONOMICS.

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Ongoing trends: Moore’s (2nd) Law

1970 1980 1990 2000 20101

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Cos

t [$M

]Year

• While cost per complexity plummets exponentially (35%/yr), cost of production plant rises exponentially.

• By 2025, projected trend says fab plant cost ~ $1 trillion.

• Clearly this trend cannot continue either….

International Technology Roadmap for Semiconductors

These trends have been continuing by design for the last ~ 10 years.

SEMATECH: international consortium of semiconductor manufacturers – set goals, fund research of common interest to them all. Includes such US players as: AMD, Agere Systems, Hewlett-Packard,Hynix, Infineon Technologies, IBM, Intel, Motorola, Philips, STMicroelectronics….TSMC, and Texas Instruments

Identifies “technology nodes” and spec/cost/performance targets.

These days, nodes identified by DRAM pitch:

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ITRS production cycle

Technology nodes are labeled by production – research demonstration must come well ahead of any node goal.

Basic parts

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Current production factoids:

• Typical Pentium: ~ 107 transistors, total chip area of 310 mm2

• Active area of transistors is ~ 28 mm2

• Cost per transistor currently between 50 and 100 microcents (!).

• Total number of processing steps needed for one chip: hundreds

• Total number of masks needed for one chip: ~ 30-40

• Acceptable total yield ~ 50% (!)

State-of-the-art: Si material

Growth method: Czochralski

• A seed crystal is attached to slowly rotating rod, and is dipped into Si at just over the melting point.• The rod is slowly withdrawn from the melt.• Rate is increased at end to avoid impurity contamination.

http://www.techfak.uni-kiel.de/matwis/amat/elmat_en/kap_5/illustr/i5_1_1.html

Diameter: 300 mm

Specs needed for 99% good wafers:

Site flatness: < 130 nmNumber of particles: < 120/waferSurface metal contamination: < 1010 at/cm2

Iron concentration: < 1010 at/cm3

Stacking faults: < 1/cm2

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State-of-the-art: Lithography

Light source: 193 nm

Phase compensated masks + chemically amplified resists allow smallest features (e.g. FET channel length) to be ~ 65 nm.

Resist pattern edge roughness: < 3.6 nm (3 σ)*

Particle contamination: < 1500/m2 of size 100 nm or greater*

Number of defects in patterned film: < 0.05/cm2 of 50 nm*

Overlay accuracy of mask: 28 nm

State-of-the-art: MOSFET

p-type

Poly-Si

silicide

n-type n-type

spacer

source drainGate oxide

Oxide thickness: ~ 1.8 nmChannel length: ~ 65 nmGate position: ~ 6 nm (!)Characteristic time: ~ 0.86 psSubthreshold leakage: 0.05 µA/micron

Intel 2Q 2005:Parasitic RSD contribution: < 180 Ω-µmEnergy per switching: 1 fJ/µmStatic power dissipation: 600 nW/µm

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State-of-the-art: power

• Supply voltage in processor core: ~ 1.1 V

• High performance processor power dissipation (with heatsink): 130 W

• Battery-powered processor power dissipation: 3-5 W

Can crunch some numbers on high-performance system.

Say 107 transistors running at 2.5 GHz gives that 130 W figure.

Now consider 108 transistors in the same area, operating at 10 GHz, for example. Such a processor made with present-day designs and approaches would dissipate ~ 5 kW / cm2 (!!) This is comparable to the power density radiated by a rocket engine….

State-of-the-art: reliability

Device early failures (in first 4000 hours): 50 ppm

Long-term failures (in first 109 hours): 10-100 ppm

Electrostatic protection survival: 10 V/µm

Testing is done under “accelerated failure” conditions –typically running devices at higher-than-normal temperatures, for example.

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Reading the roadmap

• White = manufacturable solutions known and being optimized.

• Yellow = manufacturable solutions known and demonstrated, but not yet in practice (often, too expensive / yields too low / too new to be optimized yet).

• Red = “brick wall” = no known manufacturable (!) solution to given problem / means of meeting criterion.

Remember the ramp-up cycle. If there’s a red item and it’s less than two years away, the issue is a very serious one.

Roadmap goes out ~ 10 years, but is constantly under revision.

Near-term demands (2007): Si material

Site flatness: < 64 nm (critical, but hard to measure)

Number of particles: < 123/wafer (below measurable threshold)

Surface metal contamination: < 1010 at/cm2 (more critical)

Iron concentration: < 1010 at/cm3 (more critical)

Stacking faults: < 0.3/cm2 (factor of 3 over current)

General trends:

• Even when current tolerances don’t change by much, their importance increases.

• Running into metrology problems - don’t have adequate tools to efficiently assess whether criteria are being met.

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Near-term demands (2007): Lithography

Light source: 193 nm? 157 nm?

FET channel length: 35 nm.

Resist pattern edge roughness: < 2.2 nm(3 σ)

Particle contamination: < 1500/m2 of size 100 nm or greater

Number of defects in patterned film: < 0.04/cm2 of 40 nm

Overlay accuracy of mask: 23 nm

This is particularly alarming:

Running into physical limitations of lithographic patterning (not just optical, but polymer resist based in general).

Near-term demands (2007): MOSFETEquivalent oxide thickness: ~ 1 nm

Channel length: ~ 25 nm

Gate position: ~ 2 nm

Characteristic time: < 0.68 ps

Subthreshold leakage: 1 µµµµA/micron

Parasitic RSD contribution: < 20%

Energy per switching: 0.032 fJ

Static power dissipation: 53 nW

25 nm

15nm

Biggest problems: oxide thickness, contact resistances, and leakage problems due to tunneling / thermal emission.

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Long-term demands (2016): Si material

Wafer size (!): 450 mm (How does one grow and polish these?)

Site flatness: < 23 nm

Number of particles: < 75/wafer (below measurable threshold)

Surface metal contamination: < 1010 at/cm2 (more critical)

Iron concentration: < 1010 at/cm3 (more critical)

Stacking faults: < 0.06/cm2 (another factor of 5)

• Most requirements continue increasing criticality.

• Metrology even more of a problem.

• Larger wafer size desired, but may not happen….

Long-term demands (2016): Lithography

Light source: X-ray? E-beam? Imprint?

FET channel length: 9 nm.

Resist pattern edge roughness: < 0.7 nm(3 σ)

Particle contamination: < 500/m2 of size 50 nm or greater

Number of defects in patterned film: < 0.01/cm2 of 10 nm

Overlay accuracy of mask: 9 nm

Noone knows how to do this.

Biggest problems:

• Single-nm alignments across ~ 2cm chip, + across 450 mm wafers.

• Metrology.

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Long-term demands (2016): MOSFETs

Equivalent oxide thickness: ~ 0.4 nm

Channel length: ~ 9 nm

Characteristic time: < 0.15 ps

Subthreshold leakage: 0.5 µA/micron

Parasitic RSD contribution: < 35%

Energy per switching: 0.285 fJ/µm

Static power dissipation: 4.4 µW/µm

• Intel can make THz, 10 nm channel transistors, but not in bulk.

• Several finite-size problems crop up (contact resistances again)

• Irreversibly changing “1” to “0” costs, minimally, kBT ln 2 = 0.002 fJ (!)

General observations

• We’re running out of time fast for standard CMOS processing if we want to continue Moore’s (1st) law.

• At the nm scale, lack of (fast) metrology is a real killer.

• Not all coming problems are “simple” engineering or process development issues: “We have entered the era of material limited device scaling”.

• We’re approaching the era of physics-limited device scaling in certain aspects as well.

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Is industry considering alternatives?

The 2001 ITRS was the first roadmap to include a section on Emerging Research Devices.

Planners well aware that they need to be looking at:

• “Nonclassical CMOS” (Transport-enhanced/ultrathin body/source-drain engineered /double-gate/vertical MOSFETs)

• Alternative devices (single-electron transistors)

• Hybrid devices (nanotube FETs)

• Novel architectures (defect tolerance, cellular automata, biologically inspired)

• Really novel architectures (molecular computers, quantum computers)

Roles for “nano”

Pure research

Applied research

• Fundamental physics and chemistry of these materials at nm scale.

• Understanding new phenomena as they arise / become relevant.

• Learning the science of possible new architectures.

• Nanomaterials including resists.

• Metrology: how do you measure critical properties on these length scales?

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Summary and conclusions

• Moore’s Laws are obeyed by design, not by accident.

• Electronics industry wants to continue aggressive scaling, but faces many challenges along the way.

• “Nano” can and must play a role in addressing these challenges / opportunities.

• Either we’ll make some significant paradigmatic shift within 10-15 years, or computer hardware performance will plateau (e.g. passenger airplane speeds).

• One of the major limiting problems is economic.

Next time:

MOSFET scaling in detail: what’s the physics?