Design and Implementation of VLSI Systems(EN0160)

Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey Pearson]

Lecture05: MOS transistor theory

• Last time– Gate layouts and stick diagrams

• This time– MOS transistor theory (ideal case)

gate-oxide-body sandwich = capacitor

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < Vt

depletion region

(c)

+-

Vg > Vt

depletion regioninversion region

Operating modes• Accumulation • Depletion• Inversion

• The charge accumulated is proportional to the excess gate-channel voltage (Vgc-Vt)

The MOS transistor has three regions of operation

• Cut off

Vgs < Vt

• Linear (resistor):

Vgs > Vt & Vds < Vgs-Vt

Current α Vds

• Saturation:

Vgs > Vt and Vds ≥ Vgs-Vt

Current is independent of Vds

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

How to calculate the current value?

• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

• Qchannel = CV

• C = εoxWL/tox = CoxWL (where Cox=εox/tox)

• V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9)

polysilicongate

Carrier velocity is a factor in determining the current

• Charge is carried by electrons• Carrier velocity v proportional to lateral E-field

between source and drain• v = μE μ called mobility

• E = Vds/L

• Time for carrier to cross channel:

t = L / v

I=Q/t

• Now we know

– How much charge Qchannel is in the channel

– How much time t each carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

tW VC V V VL

VV V V

In linear mode (Vgs > Vt & Vds < Vgs-Vt)

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

tW VC V V VL

VV V V

Can be ignored for small Vds

For a given Vgs, Ids is proportional (linear) to Vds

In saturation mode (Vgs > Vt and Vds ≥ Vgs-Vt)

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

tW VC V V VL

VV V V

22

2

dsatds gs t dsat

gs t

VI V V V

V V

Now drain voltage no longer increases current

Operation modes summary

2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

I ds (m

A)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2

Vgs = 1

– 0.6 micron process

– tox = 100 Å

– = 350 cm2/V*s

– Vt = 0.7 V

– W/L = 4/2

PMOS is similar

What happens when we construct a INV (PMOS+NMOS)?

Inverter voltage transfer function

AB

C

ED

Summary

• This lecture– Ideal transistor modeling

• Next lecture– Non ideal transistor modeling

Inverter current transfer function