Design and Implementation of VLSI Systems(EN0160)Lecture 34: Design Methods (beyond Tanner Tools)Prof. Sherief RedaDivision of Engineering, Brown UniversitySpring 2007[sources: Weste/Addison Wesley Maxfield/Newnes]

Stage I. IC Design, Verification, and TestSpecificationDesignschematicsIdeasHDL (Verilog/VHDL)C-based design (SystemC)Test-structure InsertionSynthesislibrarygate-leveldesignsimulation/verification

Stage II. IC Physical Implementation FlowFloorplanning/placementrepeater insertionclock tree synthesisP/G network /routingmetal fill insertionDRC/LVSgate-level circuitreticles/masksmask generation / OPCCustom/Application Specific IC (ASIC)

Stage III. Fabrication and Packagingreticlesfabricate waferTest diesdice and package the good oneschips

Stage I. IC Design, Verification, and TestSpecificationDesignschematicsIdeasHDL (Verilog/VHDL)C-based design (SystemC)Test-structure InsertionSynthesisLibrarygate-leveldesignverification

Design Entry

Graphical Flowchart

Graphical State Diagram

When clock rises If (s == 0) then y = (a & b) | c; else y = c & !(d ^ e);

Textual HDL

Block-level schematic

Top-level block-levelschematic

Behavioral(Algorithmic)

System

Verilog

VHDL

VITAL

- Relatively easy to learn- Fixed data types- Interpreted constructs- Good gate-level timing- Limited design reusability- Limited design management- No structure replication

- Relatively difficult to learn- Abstract data types- Compiled constructs- Less good gate-level timing- Good design reusability- Good design management- Supports structure replication

Structural(Gate, Switch)

Functional(RTL, Boolean)

Algorithmic

System

SystemC 1.0

SystemC 2.0

RTL

Behavioral/Transaction-level

Timed

Untimed

Functional Simulation Make sure your design is logically correct.

SynthesisSynthesis transforms HDL to gates

if SEL == 00 then Y = A;elseif SEL == 01 then Y = B;elseif SEL == 10 then Y = C;else Y = D;end if;

A

B

C

D

2:1 MUX

2:1 MUX

2:1 MUX

SEL == 00

SEL == 01

SEL == 10

Y

VerificationWe cannot try all possible input combinations to check our designHow can we verify that our synthesizer is correct?Imagine you are designing a traffic light controller, how can you guarantee that the light will not be simultaneously green for both directions?Formal verification uses mathematical techniques to verify certain properties of your design.

Stage II. IC Physical Implementation FlowFloorplanning/placementrepeater insertionclock tree synthesisP/G network /routingmetal fill insertionDRC/LVSgate-level circuitreticles/masksmask generation / OPCCustom/Application Specific IC (ASIC)

Fast timing analysis using static timing analysis (STA)I1I2I3I4I5I6O1O2What is the worst delay of this circuit without regard to the dynamic input patterns?

What are the critical path(s) that lead to this delay? perhaps timing can be improved if we adjust themC17 from ISCAS85 benchmarks

Floorplanning and placementFloorplanning (chip outlining) is a small scale 2-D assignment problem determines positions for large blocks of logic/memory

Clock tree synthesis Clock net(s) delivers the periodic generated clock signal to FFs

Design objectives:Zero-or prescribed skewminimum wirelengthminimize buffers for signal integrity

Buffering (repeater insertion) for timing and signal integritysourcesinksinkThe situation is complicated in case of multi-pin nets:

Design and analysis of power supply networks[Blaauw et al., DAC98]PowerPC 750 power gridPowerPC 750 IR-drop map Power supply network delivers Vdd/Gnd signals to all components. Main challenges:

1. IR drop: voltage at delivery point is degraded than the ideal voltage performance drop signal integrity problems

2. electromigration

Routingpin p1pin p2Objective: determine routes (tracks, layers, and vias) for each net such that the total wirelength is minimized. Be careful with routing critical nets and clock netscellcongestion

Routing and parasitic extractionsourcesinksink Multi-pin nets add more complexity in routing After all routes are determined, you can calculate the parasitic capacitance between each wire and its neighbors

Fill insertion CMP (chemical mechanical polishing) is executed for each layer before buildup of other layers

Remember the DRC violations from L-Edit! How can metal fill insertion helps in smoothing surfaces?[(animation is not technically correct!] [Photos are form Quirk/Serda]

Mask preparation and resolution enhancement techniques (RET)original layoutGDSII

Mask preparation and resolution enhancement techniques (RET)Light source 193nm130nm feature[Schellenberg, IEEE Spectrum03]

Stage III. Fabrication and Packagingreticlesfabricate waferTest diesdice and package the good oneschips

Fabrication and TestTestingFunctional (yield)How many circuits work (have no defects)?Delay/Power (parametric yield)What is the speed and power of the ones that work?

Dicing and packagingwaferdice

reticles

Packaging choices

SummaryOverview of IC design flowWe are done with main lecturesWe meet in exactly one week on May 4th to give your project presentations