design for manufacturing concurrent engineering

7/31/2019 Design for Manufacturing Concurrent Engineering

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POD DESIGN FORMANUFACTURING/CONCURRENT

ENGINEERING (DFM/CE) AUDIT CHECK

LISTS

TABLE OF CONTENTS

PURPOSE AND SCOPEPAGE 2

INTRODUCTIONPAGE 2

RESPONSIBILITIES PAGE

13TERMS AND DEFINITIONS

PAGE 14NEW PRODUCT DEVELOPMENT CHECK LISTS

PAGE 15

BASIC MANUFACTURABILITY GUIDELINESPAGE 15

MANUFACTURABILITY GUIDELINES TABLE IPAGE 15MANUFACTURABILITY GUIDELINES TABLE IIPAGE 17MANUFACTURABILITY ASSESSMENT CHECK LIST

PAGE 18PCB DESIGN PROCESS FLOW CHARTPAGE 19PCB DESIGN PROCESS COMPONENT SPACING AND ORIENTATION

REQUIREMENTS PAGE 19PCB DESIGN PROCESS COMPONENT ORIENTATION REQUIREMENTS

PAGE 19PCB DESIGN PROCESS COMPONENT LAYOUT REQUIREMENTS FOR SMT

PAGE 20SCHEMATIC PAGE

21COMPONENTSPAGE 22

PCB DESIGN (PRE/POST-CAD ROUTING)PAGE 22PCB DESIGN (CAD) PAGE

26PCB DESIGN (POST CAD)PAGE 33PCB DESIGN FOR MANUFACTURING (CAM)

PAGE 33PCB FABRICATION (CAM)PAGE 33


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PCB ASSEMBLY (CAM)PAGE 33MECHANICAL DESIGNPAGE 33PCB FABRICATION DRAWINGSPAGE 33

PCB FABRICATION CAD DATAPAGE 33PCB FABRICATION SPECIFICATIONSPAGE 34PCB ASSEMBLY BILL OF MATERIALSPAGE 35PCB ASSEMBLY DRAWINGSPAGE 36

1.0 PURPOSE AND SCOPE

The purpose of this documents check-lists is to provide a systematicdesign audit/review tool and process to assess all design formanufacturing requirements using concurrent engineering. Thisdocuments purpose is also to ensure all DFM/CE team members,throughout the supply chain, provide vital input so processes can bemanaged instead of results as defect.

The scope of this check-list extends to all personnel, phases andelements required to ensure PCBs and PCBAs are manufacturable andcapable of being processed in qualified supplier capabilities.

Note: DFM encompasses all other DF requirements as DFT,design for cost, etc.

2.0 INTRODUCTION


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This set of continuously evolving and improving audit check-lists, andthe design standards they represent, is intended for use by all involvedin the POD process to optimize designs and manufacturing processesrequired to produce them. Many books, articles, and papers describeDFM/CE benefits as reduced process times and costs, improved initial

product quality, long term product reliability, and increased customersatisfaction.

Note: This document is comprised mostly of all check lists, ordocumentation reduced to check lists, found in current POD,POD, POD, and POD documentation as ISO Required ReadingFor Test Engineering Personnel (per GEB 02/07/01). Someinformation is taken directly from IPC and from work Earl Moonhas done at other companies as a consultant/contractor. Thereis little new information contained herein, but what is importantis that it be used by DFM/CE team members for all new designs

and to shore-up the continuously improving communicationssystem at POD. Weve all used this stuff before to greatadvantage.

Cost reductions, determined by organizations using DFM/CE for the firsttime, have been reported in the 25% range. Greatest savings are madewhen applying DFM/CE principles and activities at the earliest designphases, as no amount of careful layout or other design considerationseliminate costs of assembling components once on the schematic. Somestatistics reported are:

60% of overall product cost is determined by decisions made early inthe design process

75% of manufacturing cost is determined by design drawings andspecifications

70 80% of all products defects are directly related to design issues

Findings also stress to need for concurrence from the design conceptthrough all manufacturing processes. Without CE, it is not possibleinitially to qualify the design as near producible by any process

capability.

Simply, at the design level, all ideas must be visualized and thoughtthrough all subsequent processes to customer acceptance. This does notallow a single individual to make decisions concerning productmanufacturability. A team must be formed that is composed of allresponsible process managers from design through all fabrication,assembly, test, and acceptance processes, sub processes, and activities.


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To ensure all designs are manufacturable in selected and qualifiedsupplier process capabilities, it is required that DFM/CE be practicedeffectively and efficiently. Again, this first requires visualizing the affectsdesigns will have on all subsequent processes and, conversely, the

impact proven, well managed processes have on all designs.

Once a design concept is prepared, the DFM/CE team reviews it andprovides input to the EE and design process manager so the conceptbecomes more realistic. At this phase, as simple concept diagram maybegin taking form as a schematic with more clearly defined componentsselected for use in manufacturing operations. A component engineer,working with a process, manufacturing, test, and quality engineer, willhave provided input to the design engineer concerning various factorsas:

Advanced Manufacturing Engineer (AME) input vital to fabricationand assembly process management starting before any layout finalized before routing, and after routing for design verification

Component Engineer component cost, performance characteristics,reliability ratings, availability and delivery schedules, and availablepackage types, etc.

Process Engineer process and equipment types required for variousassembly operations, process and equipment qualification, mountingrequirements, solderability requirements, and process support elements,

etc.

Manufacturing Engineer manufacturing support required toassemble components, process and equipment maintenance, additionalfacilities, personnel issues, manufacturing procedures, training,continuous process improvement requirements, etc.

Test Engineer component, PCB, and PCBA ICT and functional testrequirements, etc.

Quality Engineer component reliability testing, solder joint qualityand reliability requirements, statistical data and information, etc.

The same basic requirements must be met for printed circuitry. All teammembers, from design through test of printed circuit boards andassemblies, provide input concerning all manufactuability issues as:


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PCB size, dimensions, and tolerances, materials, constructions,dimensional stability, surface coatings and solderability, soldermasks, electrical performance, thermal considerations, hole sizes,locations, and quantities, pad sizes, configurations, and locations,bare and loaded board test points, facilities, equipment, personnel,

documentation, training, and process requirements (too many to listhere though all comprise DFM check-lists in section 5.0 herein),drawing requirements, and acceptance specifications.

What it all comes down to is the design engineer and designer cannotpossibly be capable or responsible for making decisions concerning alldesign requirements. If this were so, few designs would bemanufacturable. Having said this, many designs are not for the reasonsstated. Few manufacturing capabilities would be found capable ofmanufacturing such designs (often they are wrongly chosen), and fewcustomers would receive product meeting expected requirements (none

of us want a lifetime warranty on any product we must return regularlyfor a similarly defective one).

Again and again, concurrence is the key to DFM. If a well defined,responsible, responsive, DFM/CE team is not formed and functioning,designs will not be manufacturable on time, the first time, every time, atthe lowest cost. This is exemplified by a team representative from onemanufacturing capability saying a board only can be made a certain wayto meet design requirements or another saying a specific typecomponent or mounting location must be used instead of another toensure proof of design and manufacturability.

If particular input is supported by other qualified suppliers, and most ofindustry, the design can go forth with this information implemented in it.If not, the design must be rethought or other suppliers and processcapabilities must be sought. Likewise, a process may be changed orboth design and process changes may be made to satisfy customer anddesign requirements, as usually is the case. Again, it comes down to CEpositively effecting DFM, as early in the design phase as possible.

Something often found bothersome is DFM after the fact. This occurswhen a manufacturer receives design input and attempts making

product. It occurs too often in the contract manufacturing world whereschedules drive most everything including some people crazy as theysee good, up front DFM efforts get lost because customers dontparticipate as they should. The problem shows up as defect found atsome manufacturing level and is reported back to the design team, thenchanges are made many call DFM. This isnt the way its supposed to be.


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Ideally, DFM, through concurrence, prevents defect from ever occurring.This is possible as most design requirements are made manufacturablethrough careful prior planning and continuous improvement, both indesigns and processes, is sought as they evolve based on considerableapplied past experience both with designs and processes. Concurrent

engineering supports this and ensures evolution in compatible, proven,qualified process capabilities not in reactive, results managed chaos.

Exceptions rarely come as a breakthrough instead of evolutionaryprocess requirements. If this happens, all processes must bereconsidered and much development time and money must be spent tofind designs and processes compatible at some point. In this instance,CE takes on a whole new perspective, but not new responsibilitiesthough some effort may be intensified to fine breakthrough, whateverit may be.

These requirements and design standards serve as the starting point forDFM/CE. It has been derived partly from already available industryguidelines having been derived from CE practices and participants.Even so, ongoing CE is required to ensure these requirements andstandards best serve the design effort and proof of design process meaning the design has been verified, validated, and accepted by thecustomer. The basic tools for DFM/CE are as follows:

ISO 9000 DESIGN CONTROL REQUIREMENTS 4.4 SUMMARYCompliance requires demonstrated effective control over the entireproduct design/development process including identification of customer

needs and expectations, preparation of a marketing/technicalspecification, and plans for the development project, the developmentprocess, the provision of adequate resources and qualified personnel tothe project, and regular product design reviews. It also requires thecontrol of design output as in technical data sheets, productapplications, and specifications, identification of regulatoryrequirements, and design verification and validation. Formal proceduresare required for subsequent improvements or modifications.

Key Points:

1) Procedures to control design process2) Design and development plans3) Technical interfaces identified and documented4) Customer requirements fully documented5) Identification of Regulatory requirements6) Design reviews7) Documentation available to show design output meets specification8) Design Verification


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9) Design Validation10) Control of design changes

ISO 9000 DESIGN CONTROL REQUIREMENTS 4.4 IN-DEPTH

POD, to assure adequate control of its designs and design process,assures design requirements meeting product and contractrequirements. Also, the following ISO 9000 policy, and resultantprocedures/processes, must be considered for effective, efficient designprocess management to be assured. Again, DFM/CE is effected as aneasy extension of these policies, procedures, and processes.

4.4.1 Purpose And ScopeThe purpose of this section of the POD Quality Policy Manual is toindicate that POD has established and does maintain documentedprocedures to control and verify the design of the product in order to

ensure that the specified requirements are met.

The scope of this section extends from all customer contractrequirements to all suppliers providing POD specified product andservice quality. The system and related operating procedures describedin this section comply with Standard Requirements in Section 4, QualitySystem Requirements, Paragraph 4.4 - Design Control, the followingpolicy requirements, and related documentation:

4.4.2 Design Control Responsibility And Authority Requirements

1) The Engineering Process Manager is responsible and has theauthority for all design and product development processes.

2) The Application Engineering and Systems Design Process Managersare responsible and have the authority for the design of hardware,software, and complete systems.

4.4.3 Design Control Quality System PolicyThe responsibilities and authorities indicated in 4.4.2, when properly

fulfilled, assure designs meeting intent and specified customer contractrequirements. POD assures, through concurrent engineering activities,proper design rule selections, and process capability evaluations,appropriate responsibilities and authorities are fulfilled. Standardreference documents used in the design process include:

1) Design Standards Based On Industry Guidelines And ReliabilityTesting


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2) Product Acceptance Specifications3) Health And Safety Regulations4) DoD And National Standards5) Statements Of Work6) Design Development Purchasing Requirements

4.4.4 Design And Development PlanningPOD prepares plans for each design and development activity. Theseplans describe or reference these activities, and define responsibilityand authority for their implementation. The design and developmentactivities are assigned to qualified personnel equipped with adequateresources. The plans are updated as the design evolves.

POD, at the quote evaluation phase, assures its Design and SalesProcess Managers are responsible, and have the resources required, forevaluating customer requirements compared with current product

designs and the process capabilities required to assure new productquality on time, at an agreeable cost. This provides initial assurancethese requirements can be met or whether product or process (or both)redesign is required.

Design authorities are responsible for controlling specified productdesigns and those of standard product. One authority may be appointedproject manager when multiple designs are involved. See POD, EPM -000X Procedures for particular requirements.

4.4.5 Organizational And Technical Interfaces

Organizational and technical interfaces between different groups, whichinput into the design process, are defined and the necessary informationis documented, transmitted, and regularly reviewed. This is doneconcurrently or individually between appropriate Engineering, Sales,Design, Manufacturing, and Quality Assurance process managers. Alldesign requirements are reviewed to assure manufacturability,testability, assembleability, maintenance, acceptance, and customersatisfaction.

4.4.6 Design InputDesign input requirements relating to the product, including applicablestatutory and regulatory requirements, are identified, documented andtheir selection is reviewed by POD for adequacy. Incomplete,ambiguous, or conflicting requirements are resolved with thoseresponsible for imposing these requirements.


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Design input takes into consideration the results of any contract reviewactivities. Any omissions, ambiguities, or conflicts are resolved with thecustomer before contract acceptance and performance.

4.4.7 Design Output

Design output is documented and expressed in terms that are verifiedand validated against design input requirements. Design ProcessManagement is responsible for the correct translation of all designrequirements into specifications and drawings so the designs may beverified and validated (proven to meet input or intended requirements).Design output:

1) Meets the design input requirements;

2) Contains or make reference to acceptance criteria; Identifies thosecharacteristics of the design that are crucial to the safe and proper

functioning of the product (e.g. operating, storage, handling,maintenance, and disposal requirements).

3) Design output documents are reviewed before release by the DesignProcess Manager.

4.4.8 Design ReviewAt appropriate stages of design, formal documented reviews of thedesign results are planned and conducted. Participants at each designreview includes representatives of all functions concerned with thedesign stage being reviewed, as well as other specialist personnel, as

required. Records of such reviews are maintained.

4.4.9 Design VerificationAt specified stages in the design process, POD performs designverifications to ensure the design phase output meets the design phaseinput requirements. All design verification activities are recorded in astatement of work to ensure proper correlation between output andinput.

The initial design review establishes and identifies the responsibilitiesrequired as contract performance progresses. Additional design reviews

are performed throughout the design phase to verify that design andtest data conform to the requirements along with appropriate statutoryregulations, safety requirements, or other design considerations.

Note: In addition to conducting design reviews (see 4.4.8),design verification may include activities such as:

1) Performing alternative calculations,


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2) Comparing the new design with a similar proven design, if available,3) Undertaking tests and demonstrations, and4) Reviewing the design stage documents before release.4.4.10 Design ValidationDesign validation is performed to ensure that product conforms to

defined user needs and/or input requirements. The design validationprocess is performed in accordance with design plan by reviewing finaldesign documentation before release.

Notes:1) Design validation follows successful design verification (see 4.4.7).2) Validation is normally performed under defined operating conditions.3) Validation is normally performed on the final product, but may benecessary in earlier stages prior to product completion,4) Multiple validations may be performed if there are different intendeduses.

4.4.11 Design ChangesAll design changes and modifications are identified, documented,reviewed, and approved by the Design Process Manager before theirimplementation. All design changes are subject to design reviews andno deviation from the design standard, drawings, or specifications, afterissue, is permitted except through negotiation and change proceduresand processes.

4.4.12 Related DocumentationDetailed work instructions, individual responsibilities, workmanship

standards, and records (including corrective action) are contained in thefollowing Quality System Documents:

1) POD, EPM - 000X Design Control Procedures2) POD, QPM - 300X Records Control And Retention Procedures

Note: The foregoing ISO 9000 Design Control perspective is thatof a contract electronics manufacturer. For POD, as the primecustomer, its perspective reflects its position in supply chainmanagement (SCM).

OK! So whats new? Its not new. Its DFM/CE and how it easily is inte-grated into ISOs 4.4 requirement. If you really read and apply the keypoints, it already is. This integration is DFM/CE and continuous processimprovement (CPI). ISO, unfortunately, is leaving it up to us to figureout. The following represents simple DFM/CE requirements (note howthey track the key points. Note they were in use way before ISOs rudi-mentary introduction to the USA in 1987):


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PRIMARY DFM/CE CHECK LISTS PRODUCIBILITY ASSESSMENT

MORE COMPLETE, COMPETITIVE PROPOSALS

PRODUCTION PROBLEMS IDENTIFIED AND CORRECTED EARLY

DESIGN FOR OPTIMUM COST EFFECTIVE PRODUCTION

SUBCONTRACTOR CAPABILITIES AND DEFICIENCIES CLARIFIED WITHRESPECT TO CUSTOMER AND DESIGN REQUIREMENTS AND THEREVERSE

PRODUCT QUALITY, RELIABILITY, AND MAINTAINABILITY IMPROVED

NEW TECHNOLOGIES NEEDED TO ACHIEVE DESIGN PRODUCIBILITYIDENTIFIED AND EXPLORED

PRODUCTS DELIVERED ON SCHEDULE WITHIN COST

MORE OPPORTUNITY FOR MORE PROFITABLE PRODUCTION

LOWER COST TO CUSTOMER

HIGHER CUSTOMER SATISFACTION

TEAM EFFORT

EXPERIENCED TEAM MEMBERS

RIGHT DECISIONS CONCERNING BID/NO BID

EXPERIENCE ON SIMILAR PROJECTS

MEANINGFUL PRODUCIBILITY ASSESSMENT DATA

SYNERGY REQUIRED

AFTER CONTRACT - SAME TEAM TO EFFECT DESIGN FORPRODUCIBILITY

DESIGN AND OTHER TEAM MEMBERS WORK TOGETHER

INTERACTION AND COMMUNICATION

PRODUCT ENVIRONMENT

TEAM COMPOSITION

PRODUCIBILITY ENGINEERING

DESIGN ENGINEERING

SOFTWARE ENGINEERING

MANUFACTURING

MATERIALS MANAGEMENT

SYSTEMS ENGINEERING QUALITY ASSURANCE AND INSPECTION

TEST AND ANALYSIS

OTHERS AS REQUIRED

PRODUCIBILITY ASSESSMENT TOOLS


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PRODUCIBILITY ASSESSMENT WORKSHEET AND/OR STATEMENT OFWORK (SOW)

GOALS BASED ON SIMILAR PAST EFFORTS (DESIGN/PROCESSEVOLUTION)

GOALS BASED ON DAY TO DAY WORK ON NEW EFFORTS (EVOLUTION,

REVOLUTION, OR RAPID EVOLUTION BORDERING ON REVOLUTION)

GEOMETRIC DIMENSIONING AND TOLERANCING

NOTE: This is an important area not yet even thoughtfullyconsidered in the PCB world. For the life of me, I cannotconceive why, as this elemental requirement is the concurrentengineering language most all other designs and products areconsidered and effected. PCB master drawings come closestusing some of what is included herein.

ANSI Y-14.5M EACH DIMENSION SHALL HAVE A TOLERANCE

DIMENSIONS FOR SIZE, FORM, AND LOCATION OF FEATURES SHALLBE COMPLETE TO ASSURE NO MIS-UNDERSTANDING OF FEATURECHARACTERISTICS

EACH END PRODUCT DIMENSION SHALL BE SHOWN

DIMENSIONS SHALL BE SELECTED AND ARRANGED TO SUIT THEFUNCTION AND MATING RELATIONSHIP OF A PART

DIMENSIONS SHALL NOT BE SUBJECT TO MORE THAN ONEINTERPRETATION

DRAWING SHALL DEFINE A PART WITHOUT SPECIFYINGMANUFACTURING METHODS BUT SHALL CLEARLY INDICATESPECIFIED PART REQUIREMENTS

CONCURRENT ENGINEERING TEAM WITH GD&T/DFM

SAME TEAM AS FOR PA PREVIOUSLY INDICATED PLUS:

MARKETING

TOOL AND GAGE DESIGN

PURCHASING

SUPPLIERS

SAFETY AND REGULATORY MANAGEMENT

DESIGN LAYOUT METHODOLOGY FOR PRODUCT AND PROCESSSYSTEM DESIGN

DETAILED ASSEMBLY LAYOUT

IDENTIFICATION OF CRITICAL CHARACTERISTICS


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MECHANICAL SIMULATION

DESIGN FOR ASSEMBLY

DESIGN OF EXPERIMENTS

PHYSICAL PROTOTYPING

DESIGN FOR ASSEMBLY

KISS (keep it simple stupid)

MINIMIZE PARTS OPTIMIZE PARTS HANDLING

MINIMIZE WORK SURFACES

ASSURE CLEAR VISIBILITY

MINIMIZE FASTENER USE

BOTTOM UP ASSEMBLY

ASSURE PARTS IDENTIFICATION

POSITIONING NESTS TO POSITION PARTS KNOW MANUFACTURING PROCESSES

OPTIMIZE MANUFACTURING PROCESSES VISUALIZE DESIGN AFFECTS ON PROCESSES

VISUALIZE PROCESS AFFECTS ON DESIGNS

INDIVIDUAL COMPONENT ANALYSIS

SPECIFICATION OF DATUM REFERENCE FRAME (MINIMIZE - NOT

MULTIPLE, BUT SINGLE WHEN POSSIBLE) GENERATION OF FIXTURE LAYOUT

DETERMINATION OF GAGING AND INSPECTION REQUIREMENTS

APPLICATION OF CONTROLS TO FIXTURE LAYOUT

CREATION OF THE TOOLING PACKAGE

ENGINEERING CHANGE CONSIDERATIONS

TAYLOR S PRINCIPLE

GAGING

TOOLING AND GAGE DESIGN MUST INCORPORATE TAYLOR S PRINCIPLE (SIMULTANEOUS INSPECTION OF ALL INTERRELATEDFEATURES ON THE COMPONENT - ANYTHING LESS CREATESMEANINGLESS INFORMATION CONCERNING ASSEMBLY OR FUNCTION)

SINGLE DRF (datum reference frame)

FUNCTIONAL GAGING AS MIMICKING MATING PART


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NOTE: Discrete gage, as CMM, relies on statistical samplingtechniques and mathematical algorithms not necessarily correctas it relies on single point probing of surfaces not alwaysincluding all surface elements, nor does it duplicate multiplefeature interrelationships for product function of assembly

conditions, nor (without a gaging fixture) does it establish acomponent s location based upon precedence of the datum features replicating the assembly condition - thus violatingtaylor s principle.

GAGING POLICY NOT BASED ON CURRENT STANDARDS

SPC TO CONTROL PROCESSES, NOT TO SATISFY CUSTOMER DEMANDWHERE IT SERVES NO USEFUL PURPOSE

DESIGN FOR SERVICING

REDUCES DIRECT PRODUCT COST IMPROVES RELIABILITY BY REDUCING POTENTIAL FOR FAILURE

REDUCES ADMINISTRATIVE AND INVENTORY COSTS CONCERNINGSPARES

I think you all recognize this stuff as text book. It is, and it should beclearly understood, implemented, and used in all we do as engineers. Ifdone, we all benefit from concept to customer acceptance. The mostimportant thing is we all will do it right the first time, on time, everytime, at an acceptable cost and profit. To assure all this, well detail thebasic tools in the appropriate section.

As all PCB and PCBA designs involve compromises, it must beunderstood what best design elements are required to assureacceptable product is supplied on time, the first time, every time, at thelowest cost. DFM, with CE, provides the methods and tools to make thispossible by consolidating expertise in all vital areas from design throughcustomer acceptance.

This check-lists, and the elements contained herein, start at theschematic level and proceed systematically through all design phasesand subsequent manufacturing phases. To assure schematics reflectdesign intent, DFM, with CE, must be started at this phase. Carefulconsideration must be paid to performance as well as those componentsand circuitry needed to assure designs always meet intent.

Once the schematic phase is complete, in conjunction with propercomponent selections (based on several key factors), it is possible tomove to the various design phases. Key component selection factors are


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performance characteristics, types, availability, size, power factors,mounting requirements, price, and quality as examples.

Design phases, in this document, are indicated in the table of contentsand in the matching phases following this introduction. These phases

take the design review processes logically through the processesrequired to first prove the design, then to make acceptable product.

Again, concurrence is a key factor in all design and manufacturingphases as experts in each process/phase must provide vital inputconcerning the design through verification and acceptance phases.Additionally, each team member must represent only processcapabilities proven to support designs to be produced within them.Without concurrent engineering, because no one person is capable ofknowing all required to prove a design acceptable, there is no possibilityacceptable product will be effected.

This document, and all tools and check-lists herein, provides amechanism for effective, efficient communication between allparticipation functions, groups, suppliers, customers, and all othersconcerned with preventing defect at the design level. Concurrentengineering, based on DFM/CE team involvement (see 3.0Responsibilities), is the term used to define how this communicationworks to assure nothing is mis-communicated or falls in the cracks.

Weve all been involved in this type system to one extent or another.Within a new organization, comprised of experienced personnel,

reinforcement must be made as the new system is created andimplemented. At POD, the opportunity exists to do a better job than everbefore without re-inventing the wheel that got us all here.

3.0 RESPONSIBILITIESTo be developed based on DFM/CE team composition/members andwhat each brings to the effort to manage processes instead of results.Primary purpose for DFM/CE responsibility fulfillment is to assure


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everyone on the same page and that defect is prevented at the earliestpossible time so product is delivered on time, the first time, every time,at the lowest cost

EE

Responsible, as key part of DFM team, for design conceptdevelopment, block diagrams, flow charts, schematic creation, initialcomponent selections, initial board outline and active deviceplacement requirements, and participating in DFM meetings, atscheduled times, with rest of DFM team to prevent defect first at thislevel

AMEResponsible, as key part of DFM team, for all manufacturing aspectsincluding working with EE at schematic development level to providemanufacturability input to prevent defect at the earliest possible

time. Responsible for working to develop new product introductionsand all attendant documentation including initial DRC review, masterdrawing and PCB acceptance specifications, BOMs, drawings, workinstructions, and other tools required for PCB fabrication andassembly processes.

Component EngineerResponsible, as key part of DFM team, for providing input concerningcomponent selection at the schematic level and informationconcerning price, delivery, quality, specifications, availability,alternate devices, reliability, and solderability issues as part of the

DFM team. Also responsible for participating in DFM meetings toensure latest information available.

PurchasingResponsible, as key part of DFM team, for administering businessissues primarily relating to price, delivery, and quality.

Fab Process EngineerResponsible, as key part of DFM/CE team, for providing inputconcerning process capabilities and what is required to effect thedesign as acceptable product as well as the impact design

considerations will have on quality, delivery, price, and long termreliability. Also, responsible for providing input concerning changesneeded for designs or processes.

Assembly Process EngineerResponsible, as key part of DFM/CE team, for providing inputconcerning assembly process capabilities and what is required toeffect the design as acceptable product as well as the impact design


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considerations will have on quality, delivery, price, and long termreliability. Also, responsible for providing input concerning changesneeded for designs or processes..

Test Engineer

Responsible, as key part of DFM/CE team, for providing inputconcerning test and testabilityrequirements for bare and assembled boards.

Note: Fab and Assembly process engineers may not alwaysbe available. AME may fill this void if knowledgeable aboutthese functions and their responsibilities. However, supplierfunctions must be in the loop concerning all DFM teammeetings and review findings for verification for particularprocess capabilities.


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4.0 TERMS AND DEFINITIONS

The following terms, and their definitions, do not appear in IPC-T50:


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5.0 NEW PRODUCT DEVELOPMENT CHECK LISTS

The following DFM/CE check-lists shall be used to ensure all processes,from design concept to customer acceptance, are properly managed. Byeffectively and efficiently managing processes, instead of results, defectis prevented at the earliest possible step in the new processdevelopment cycle..

5.1 BASIC PCB/PCBA MANUFACTURABILITY GUIDELINES TABLESI & II

TABLE I

Composite PCB/PCBA Design Guidelines

PRODUCIBILITY

Preferred StandardReduced

Industry Internal To Be Proven

PCB FABRICATION SECTION

REQUIREMENTS

MAX CONDUCTOR LAYERS 6 12 24

MAX BOARD THICKNESS .062 .125 .250MIN BOARD THICKNESS .062 .031 .016BOARD THICKNESS TOL 10% OF BOARD THICKNESSDIELECTRIC THICKNESS .031 .014 .002MIN CONDUCTOR WIDTH - INT .008 .004 .002MIN CONDUCTOR WIDTH - EXT .012 .008 .005CONDUCTOR SPACE & WIDTH MILS CONDUCTOR WIDTH TOL. +,- .003 .002 .001CONDUCTOR SPACE .012 .005 .003ANNULAR RING - INT .005 .002 .0012ANNULAR RING - EXT .010 .005 .0012CONDUCTOR PATTERN ACCURACY .004 .003 .002


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PLATED HOLE ASPECT RATIO 4:1 6:1 12:1PLATED HOLE DIAMETER TOL +, - .005" - .019" .003 .002 .001

.020" - .030" .004 .003 .002

.031" - .061" .006 .004 .003

.062" - .125" .008 .006 .005TOOLING HOLES .125". DIA. + .003, - .000"SOLDER MASK/PAD CLEAR .006 .005 .002(NO MASK ON PADS)

CONDUCTOR - PCB EDGE .100 .075 .050

PCB ASSEMBLY SECTION

STANDARD QFP .025 PITCH 2/5 MIL traces between pads/holes max(not preferred)FINE PITCH QFP .020 PITCH 2/4 MIL traces between pads/holes max(not preferred)X FINE PITCH QFP .016 PITCH X/X MIL X/X MIL

TYPICAL BGA .060" PITCH 4/4 MIL, 3/5 MIL traces between padsTYPICAL BGA .050" PITCH 4/4 MIL, 3/5 MIL traces between padsTYPICAL BGA/CSP .040" PITCH 4/3 MIL, 3/4 MIL, 2/5 MIL traces between padsTYPICAL uBGA .040" PITCH 2/3 MIL, 3/2 MIL traces between padsX FINE uBGA .030" PITCH

TYPICAL CSP .040" PITCH X/X MIL, X/X MILX FINE CSP .030" PITCH X/X MIL, X/X MIL

TOP SIDE COMPONENT HEIGHT RESTRICTION 2"

BOTTOM SIDE COMPONENT HEIGHT RESTRICTION .375"

TABLE II

POD Laminate MaterialCore Chart For Dimensional Stability,

MLB Laminate Integrity, And Impedance Control

REQUIREMENT PREFERRED NOTPREFERRED

PREG THICKNESS/" GLASS STYLE/% RESIN - SINGLE PLY

0.0017 106 (75%)0.0025 1080 (65%)0.0035 2113 (58%)0.0045 2116 (55%)0.0070 7628 (44%)

DIELECTRIC THICKNESS/" GLASS STYLE - MULTI PLY

0.004 106, 2113 1080,10800.005 1080, 10800.006 1080, 2113 106,106,106

0.007 1080, 2116 76280.008 2113, 21162113,1080,2113

0.009 2116, 21161080,2116,1080

0.010 2116, 21161080,2116,1080

0.011 2113, 1080, 2113106,7628,106


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0.012 1080, 7628, 10802113,2113,2113

0.013 2113, 7628, 2113 7628,76280.014 2113, 7628, 2113

7628,76280.015 2113, 7628, 2113

0.016 2113, 7628, 2113 or use 2116,7628,2116

5.2 PCB/PCBA MANUFACTURABILITY ASSESSMENT CHECK LIST

POD PCB FAB MANUFACTURABILITY AUDIT CHECK LIST

NEED/SUPPLIER A B C D E F

DATA INPUT GRBR GRBR OTHR GRBR NONE

GRBR

PHOTOPLOT INT INT OUT INT OUT INT

MATERIAL ALL ALL EPOXY

EPOXY

EPOXY

MOST

IMAGELINE/SPACE

5X5 2X2 8X8 8X8 8X8 4X4

ETCHLINE/SPACE

5X5 3X3 8X8 8X8 8X8 5X5

INSPECT AOI AOI VISU AOI VISU AOI


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AL AL

LAMINATE 10+LYR

20+LYR

6LYR 10LY R

4LYR 10+LYR

DRILL


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orientation considerations are being made. The following designprocess elements must be considered then, as some othersmust:

5.4 PCB DESIGN PROCESS COMPONENT SPACING AND

ORIENTATION REQUIREMENTS

5.5 PCB DESIGN PROCESS COMPONENT ORIENTATIONREQUIREMENTS

5.6 PCB DESIGN PROCESS COMPONENT LAYOUT REQUIREMENTSFOR SMT


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5.7 SCHEMATIC REVIEW CHECK LIST


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The following check-list shall be used at the schematic level:

DFM/CE team present (EE, AME, component engineer, purchasing,fab process engineer, assembly process engineer, test engineer,quality engineer, etc.

Schematic hard copy present for review PCB material considerations noted Electrical performance considerations noted (impedance, etc.) All components concurrently reviewed for design requirements All components concurrently reviewed for performance All components concurrently reviewed for type All components concurrently reviewed for availability All components concurrently reviewed for

quality/reliability/solderability, etc. All components concurrently reviewed for price All polarized components correctly identified

All colored/lighted devices (LEDs, etc) correctly identified All IC (PGA, BGA, DIP, SIP, SIMM, DIMM, etc.) pins correctly

identified Parts requiring sockets correctly identified Decoupling capacitors on every device requiring them Complete separation (decoupling) between planes and input

power Decoupling caps correct values Decoupling caps specified type, size, and values Pull-up caps and resistors on lines requiring them Pull-down caps and resistors on lines requiring them

Pull-up and pull-down caps and resistors specified type, size, andvalues

IC control lines (external instruction access, initialize, outputenable, etc.) have correctly identified independent pull-up/pull-down resistors

Spare IC gates included/indicated Electrically active mounting holes indicated on schematic No single point nets Net names correct syntax Reference designators for all symbols and components No duplicate or erroneous reference designators

Net-list output approved by CAD Librarian All schematic sheets have correct revisions and dates All schematic sheets have correct board title and revisions Circuit nets not having ICT test points noted on schematic Connectors or software interfaces incorporated to automate test

control or software verification


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Special grounding considerations identified on schematic(mounting holes to chassis ground with star ground or cuttablejumpers

Circuit partitioned into logical blocks for testability ease Parts list with accessory hardware

SAT components identified with default value and range Alternate BOM populations defined Special component mounting identified with proper notation

5.8 COMPONENT SELECTION REVIEWAll component selection requirements shall be based on performance,quality, reliability, solderability, availability, and price considerations. Allbut new component selections shall be made based on proven suppliercapabilities, and assembly and use characteristics.

5.9 PCB DESIGN REVIEW (PRE and POST-CAD ROUTING)All design considerations based on IPC 2221 and 782 guidelines and POD

PCB Fabrication Specification 999-004-110. All acceptance requirementsbased on IPC 600 F and 610C guidelines. All bare board qualificationrequirements based on IPC 6012 specifications. The following check-listshall be used at the pre and post-CAD routing phase:

5.9.1 DFM/CE TEAM

EE AME Component Engineer Purchasing

Fab process engineer Assembly process engineer Test engineer Quality engineer

5.9.2 PCB PHYSICAL CHARACTERISTICS AND CONSIDERATIONS

PCB physical size and space availability PCB shape and cut-out or keep-out considerations Special PCB outline considerations Dimensions, tolerances, dimensioning, and datum requirements

Warp, twist, PCB edge, and other physical requirements PCB mounting considerations and mounting hole requirements Tooling hole requirements Connector or other I/O considerations Spacing between PCB considerations Single board and panelization requirements Break away, scoring, V-groove, and routed slot considerations Plate hole requirements


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Non-plated hole requirements Blind vias Buried vias Micro vias Vias in SMT pads

Tented vias Plugged vias Blind vias plated over for flat SMT mounting pads

5.9.3 QUALITY CONFORMANCE TEST CIRCUITRY ANDCOUPONS

Quality conformance test circuitry configuration/compositionrequirements

Quality conformance test circuit panel locations Individual test coupon requirements

5.9.4 QUALITY CONFORMANCE TEST CIRCUITRY AND COUPONTEST REQUIREMENTS

X-sectioning as received and after thermal stress/shockrequirements

Hole quality drilling Hole quality hole wall preparation (etch back, smear removal,

glass fiber removal)

Hole quality electroless copper deposition or direct plate Hole quality copper electro-plating Laminate integrity and quality Solderability requirements Cleanliness requirements

5.9.5 PCB MATERIALS

Prepreg, core, and laminate material considerations (based onelectrical performance, impedance, Tg, X, Y, & Z axis properties,laminate bond strength, dimensional stability, foil bond strength,

solder termination bond strength, glass style, resin content, resinsystem, etc.)

Materials as specified for required MLB constructions (single plyprepreg/core acceptable but not with 7628 glass style. Also, no7628 facing foil or used for bond)

Use Table II, herein, to assess best possible material types, glassstyles, resin to glass ratios, thicknesses and tolerances, and single


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and multiple ply requirements for dielectric thicknesses andoverall board thicknesses.

5.9.6 MLB CONSTRUCTIONS AND OTHER MLBCONSIDERATIONS

Balanced copper weights and foil distribution Microstrip, buried microstrip, balanced stripline, and unbalanced

stripline considerations Dielectric thickness and tolerance considerations Trace width relative to dielectric thickness considerations Power and ground considerations as x-hatching Power and ground considerations as relationships to PCB edges Power and ground considerations as split reference planes Signal layers relative to reference planes considerations Overall PCB thickness considerations, dimensions, and tolerances

Layer count considerations Normal lamination considerations Special lamination considerations for different material types Sequential lamination

5.9.7 COMPONENT AND OTHER PCB CONSIDERATIONS ANDREQUIREMENTS

Active component placement and mounting requirements

Active component spacing requirements (component tocomponent, pad to pad, component to PCB surfaces and edges,orientation, etc.)

Discrete component types, placement, and mountingrequirements

Discrete component spacing requirements (component tocomponent, pad to pad, component to PCB surfaces and edges,orientation, etc,)

Schematics and BOMs Component height considerations for spacing and soldering

operations

Overall PCB thermal considerations Special electrical considerations (power, ground, speed,

impedance, etc.) Connector spacing and hole requirements as specified and

distance to edge requirements All SMT component land patterns as specified All through hole component pads and holes as specified Global and local fiducial requirements


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New, non-standard, or special component considerations BGA, uBGA, CCGA, CSP, flip chip, and other component

considerations All component type orientation for soldering requirements All component thermal considerations

Heat sink requirements Socket considerations Socket spacing requirements Test point and accessibility requirements Coax and/or fiber optic locations Critical component placement considerations Shielded components/circuits considerations Fences or mode blocks considerations Technology (ECL, CMOS, TTL, etc.) Rework considerations

5.9.8 TRACE AND SPACE CONSIDERATIONS ANDREQUIREMENTS

Trace widths and spacing requirements Routing considerations Special routing considerations for BGAs, connectors, etc. Trace to pad intersection (no acute angles, no annular ring

violations, etc.) High current carrying and thermal considerations Special grounding considerations Heat transfer from inner layers (heat pipes, etc.)

Delay or special line considerations Solder paste stencil requirements and data Pre and post-routing approval

5.9.9 SOLDER TERMINATION, CONNECTOR, SOLDER MASK,MARKING, SOLDERABILITY, ESD, AND CLEANLINESSREQUIREMENTS

Solder termination area surface finishes (gold, nickel, bare copper,

OSP/OCC, tin, white tin, silver, HASL, tin lead plate/fuse, etc.) Solder termination area surface finishes thickness/coverage Contact connector finger requirements Press fit connector requirements BGA connector requirements Micro connector considerations Other connector requirements Solder mask type, thickness, coverage, etc. requirements


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Silk screen, etched, laser, or other marking requirements Labels not on or near fine pitch or BGA devices Labels not over test point, SMT pad, or through hole pads and

holes Labels not over etched PCB nomenclature

Correct nomenclature for POD PCB # and revision in etch primary side preferred Labels not over keep out areas Cleanliness requirements ESD protection requirements Packaging, shipping, and handling requirements

5.9.10 TEST CONSIDERATIONS AND REQUIREMENTS

Engineering deliverable requirements Test point requirements

Top and bottom side pad size and test point requirements Special SMT considerations Net test requirements Bare board test requirements Test fixture tooling hole requirements Test equipment requirements ICT test requirements ICT node accessibility ICT boundary scan requirements Testability resistor requirements Oscillator requirements

Digital feedback loop requirements ECO jumper wire requirements VCC and GND access requirements PLD control requirements Analog IC isolation requirements Tri-state device requirements Custom device and ASIC requirements Functional test requirements Impedance test requirements Test tooling, fixture, pin, and software programming requirements AOI test requirements

X-ray for BGA requirements

5.9.11 DOCUMENTATION REQUIREMENTS

Master drawing notes, dimensions and tolerances, hole sizes, drillcharts, MLB constructions, and other graphic requirements

Assembly drawing requirements Bills of Materials


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Acceptance specifications CAD data format CAM program considerations and DRC requirements All documentation clear, concise, in correct format and locations,

and concurrently agreed to by all involved

All documentation, tools, data, and other vital requirements mustbe transferred effectively and efficiently with responsibilitiesassigned and receipt posted upon arrival

Note: There shall be a design review at the componentplacement level. This shall be conducted with EE and AMEDFM/CE team members to assure correct componentorientation, material selections, solder termination surfacefinishes, and any other elements affecting manufacturability.

5.10 PCB DESIGN REVIEW (CAD)

Use POD Networks to POD reference guide and check-list containedtherein and as follows:

5.10.1 INITIAL INPUT DATA FOR PCB LAYOUT

Contact info (EE/AME names, phone, and email address Tel and dvf files Hard copies of schematics, Allegro template board file Hard copy of mechanical outline drawing EEs design rules/requirements

5.10.2 WORKING WITH INITIAL DATA

Netlist loaded Board symbol checked to mechanical outline drawing Board symbol fixed as required Standard constraints set up Mechanically placed parts placed Layer stack-up updated

5.10.3 PLACEMENT

BGA dog bones removed Active placement done Active placement approved by EE Passive placement finished Assembly checks run (wave vs reflow) List of extra caps given to EE to delete from the schematic Final placement approved by EE and AME, email added to binder


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Placement boundaries adjusted once OKd by AME Ne NL loaded with extra caps removed, 100% placed Sum and DRC reports run, 100% placed/0 DRCs

5.10.4 PRE-ROUTING

Pin escapes finished Test route run Power planes added Routing rules sets Special constraint sets and areas set Critical routes added Router DO file setup Power supply router Special powers routed/split planes Via/router keepouts added

Fiducials added Layer window added Run another test route based on rules added thus far Sum and DRC reports run, 100% placed/0 DRCs Critical routing approved, email added to binder

5.10.5 ROUTING

DO file finished and tested Nets pre-routed with positive shapes having no route property

added

All above steps done Copy or pre-route board saved (in case go back needed)

5.10.6 POST ROUTE

Router clean up Back side BGA dog bones added Test points started (32 pad 100, then 70 centers) OK for 50 mil test point centers, testprep updated and run OK to use BGA dog bones for test points, testprep updated and fun List of untested nets provided to EE for evaluation

Sum and DRC reports run, 100% placed and routed/0 DRCs anddangling lines

5.10.7 TEST POINTS FINISHED

Rules for missing test points provided by EE Manually added missing test points Extra power and ground test points added


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Probe DRC run and clean Tp_rpt_gen run and clean

5.10.8 RENAME REFERENCE DESIGNATORS, IF REQUIRED

OK to rename referenced designators given by EE Copy oif board saved as prerename.brd Components renamed, except for those on mechanical outline

drawing Back annotation file created and sent to EE to update the

schematic New renamed NL provided by EE to load as a check

5.10.9 SILKSCREENS AND ASSEMBLY TEXT

Assembly text adjusted

Silkscreen text adjusted Text2pad run and clean

5.10.10 BOARD WORK

Artwork title block placed and filled out Artwork control files setup Layer window finished and checked Bar code labels added Etch nomenclature added

5.10.11 ASSEMBLY DRAWING

Assembly drawing formats filled out Assembly views labeled

5.10.12 MASTER DRAWING

Fabrication drawing formats filled out Fab notes added and updated as required Layer stackup added and adjusted Board dimensioned

NC drill parameter header filled out NC drill run, legend placed and edited Panel drawing done if required

5.10.13 CHECKING

Symrev run, all symbols up to date Sum report run, 100% placed, 100% routed, 0 dangling lines


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DRC report run, 0 DRCs Probe drc run, no errors, 100% test pointed Text2pad run, 0 DRCs Compare Allegro boards run if a respin and checked Valor run, no slivers

Board sent for final review

5.10.14 FINAL PACKAGE

Approval received from EE and AME Thieving added and adjusted Another review cycle if required by EE and AME Rename final board pcb.brd ISO forms up to date, job binder cleaned up Final Valor run, Gerber files created Output directories created (fab and assembly)

Readme.txt files edited for output directories IPC-356 report created Back annotation file created Compare Allegro boards (TPs and comp) run Bay final script edited and run Gerber files copied from Valor to fab directory Output files TARd, compressed and FTPd to Bay East Email sent to notify all of final shipment

5.10.15 CHANGES

All checks rerun

5.11 POST LAYOUT AND ROUTE CHECKAfter completing PCB design process, the following checks shall beperformed by the design team to determine all the foregoingrequirements have been met:

5.11.1 INITIAL INPUT DATA FOR PCB LAYOUT (AS 5.10.1)

Tel and dvf files Hard copies of schematics,

Initial allegro.brd file with mechanical loaded Hard copy of mechanical outline drawing EEs design rules/requirements

5.11.2 WORKING WITH INITIAL DATA (AS 5.10.2)

Dvf2txt run to create the device files Netlist loaded


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Start NETINLOG report Board symbol checked to mechanical outline drawing Board symbol modified as required Default constraints set up Parts with specific locations, places

Layer stack-up updated

5.11.3 PLACEMENT (AS 5.10.3)

BGA dog bones removed Active placement done Active placement approved by EE Passive placement finished Symrev run to check that latest symbols are being used Assembly type rules set (top reflow or top wave bottom reflow or

bottom wave)

Assembly check run Drawing summary report run, all placed DRC report run, 0 DRCs List of extra caps given to EE to delete from the schematic Final placement approved by EE and AME, email added to binder Placement boundaries adjusted once OKd by AME New net list loaded with extra caps removed, 100% placed

5.11.4 PRE-ROUTING (AS 5.10.4)

Pin escapes finished

Test route run Power planes added Routing rules sets Special constraint sets and areas set Critical routes added Router DO file setup (rules added in Allegro, not DO file) Power supply routing Special powers routed/split planes Via/router keepouts added Fiducials added Layer window added

Run another test route based on rules added thus far Sum and DRC reports run, 100% placed/0 DRCs Critical routing approved, email added to binder

5.11.5 ROUTING (AS 5.10.5)

DO file finished and tested


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Nets pre-routed with positive shapes having no route propertyadded

Copy or pre-route board saved (in case go back needed) Auto router run

5.11.6 POST ROUTE (AS 5.10.6)

Route finished and cleaned up Back side BGA dog bones added Test points started (32 pad 100, then 70 centers) AMEs OK for 50 mil test point centers, then run test prep AMEs OK to use BGA dog bones for test points, then test point List of untested nets provided to EE for evaluation Sum and DRC reports run, 100% placed and routed/0 DRCs and

dangling lines

5.11.7 TEST POINTS FINISHED (AS 5.10.7)

Rules for missing test points provided by EE Manually added missing test points Extra power and ground test points added Probe DRC run and clean Tp_rpt_gen run and clean

5.11.8 RENAME REFERENCE DESIGNATORS, IF REQUIRED (AS

5.10.8)

OK to rename referenced designators given by EE New netlist from EE to load to assure schematic and board are in

sync Copy oif board saved as prerename.brd Components renamed, except for those on mechanical outline

drawing Back annotation file created and sent to EE to update the

schematic Renamed netlist (tel and dvf) provided by EE to load as a check

5.11.9 SILKSCREENS AND ASSEMBLY TEXT (AS 5.10.9)

Assembly text adjusted Silkscreen text adjusted Text2pad run and clean up DRCs

5.11.10 BOARD WORK (AS 5.10.10)


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Compare Allegro boards (TPs and comp) run Bay final script edited and run Gerber files copied from Valor to fab directory Output files TARd, compressed and FTPd to Bay East Email sent to notify all of final shipment

5.11.15 CHANGES (AS 5.10.16)

All checks run Symrev run, all symbols up to date Sum report run, 100% placed, 100% routed, 0 dangling lines Drc report run, 0 DRCs Probe drc run, no errors, 100% test pointed Text2pad run, 0 DRCs Board check run, clean, 0 DRCs Compare alletro boards run if a respin and checked

Valor rin, no slivers

5.12 PCB DESIGN (POST CAD)

DFM/CE team present (EE, AME, component engineer, purchasing,fab process engineer, assembly process engineer, test engineer,quality engineer, etc.

Schematics, Master Drawing, PCB Acceptance Specifications,BOMs, and Assembly Drawings

All pre-routing requirements as required PCB shape and cutout or keep out considerations

Special PCB outline considerations

5.13 PCB DESIGN FOR MANUFACTURING (CAM)

DESIGN REVIEW STAGES UP FRONT, AFTER COMPONENT LAYOUT, AFTERROUTING, ETC.

5.14 PCB FABRICATION (CAM)

CAM PACKAGE FOR PCB FABRICATOR

5.15 PCB ASSEMBLY (CAM)

CAM PACKAGE FOR ASSEMBLER

5.16 MECHANICAL DESIGN CAD AND CAM

FOR ALL MECHANICAL PARTS AND HARDWARE AS SHEET METAL,MACHINED PARTS, PLASTIC PARTS, ETC.


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5.17 PCB FABRICATION DRAWINGS (MASTER DRAWINGREQUIREMENTS)

CLEAR, CONCISE NOTES, GRAPHICS, TABLES, DIMENSIONS, AND

TOLERANCES, ETC. ALONG WITH ALL SPECIAL REQUIREMENTS NOTCOVERED IN FABRICATION SPECIFICATIONS SHALL BE INDICATED ONTHE MASTER DRAWING. THE FABRICATION DRAWINGS SHALL ALLOW NOMIS-INTERPRETATIONS TO BE MADE BY ANY DFM PARTNER.

5.18 PCB FABRICATION CAD DATA

PREPARED USING POD CHECK LIST HEREIN AND DETAILED PODPROCEDURES USING IPC AND CUSTOM DESIGN STANDARDS

5.19 PCB FABRICATION SPECIFICATIONSThis check-list is derived from POD PCB Fabrication Specification 999-004-110.

5.19.1 GENERAL REQUIREMENTS

Production Conflict Deviations Negotiations with POD

Preparation for delivery Quality assurance provisions (test and procedures, and

qualification) Micro-section and solder samples Supplier selected cross sections

5.19.2 DETAILED REQUIREMENTS

Material flammability rating Material color Material thickness

Single sided boards Double sided and multilayer boards Material pits and dents Single ply material Flux Marking ink Documentation package Production artwork


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Revision level Discrepancies Touch up Conductive pattern Hole drilling

Hole position Hole quality Hole registration Plating thickness Plating finish Plating nodules Plating voids in hole wall Voids at junctions Single sided boards Plated through hole tolerance Conductive pattern plating material selection

Conductive pattern material types Tin lead plating Organic solderability preservative (OSP) Electroless nickel/immersion gold Tin nickel Contact fingers Plating quality Adhesion quality Rework Solder mask specification Solder mask coating thickness

Solder mask coating pattern Solder mask registration Solder mask and test vias Solder mask plugged vias Etch tolerance Etch feature tolerance Etching and base laminate damage Etch adhesion POD part number identification Revision level identification Source identification code

Country of origin identification Identification data legibility Marking durability Quality assurance markings Fabrication edges Bow and twist General quality conformance Nicks and pinholes


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Laminate identations Laminate damage Chemical contamination General contamination Isolated spots

Solder mask skips Plating voids Dielectric thickness Etch back Layer to layer registration Internal annular ring External annular ring Measling, crazing, delamination Thieving Surface feature tolerance Non plated through hole diameter tolerance

Non functional inner layer pads Automated optical inspection Electrical test Shelf life

5.20 PCB ASSEMBLY BILL OF MATERIALS (BOM)UPON COMPLETION OF SCHEMATIC REVIEW AND ACCEPTANCE, AND THEINITIAL COMPONENT PLACEMENT REVIEW (EE AND AME), A BOM SHALLBE CREATED CLEARLY INDICATING ALL SELECTED COMPONENTS ANDREQUIRED ASSEMBLY ELEMENTS. AS THE DESIGN EVOLVES, THE BOMSHALL BE REVISED WITH FINAL REVISION ACCEPTANCE JUST BEFORE

RELEASE TO FABRICATION AND ASSEMBLY PROCESSES.

5.21 PCB ASSEMBLY DRAWINGSPCB ASSEMBLY DRAWINGS SHALL BE CLEAR, CONCISE WITH NOTES,GRAPHICS, AND TABLES INDICATING EVERYTHING REQUIRED TOASSEMBLE PRODUCT. THERE SHALL BE NO MIS-INTERPRETATIONS,BETWEEN DFM PARTNERS, CAUSED BY LACK OF CLEAR AND DETAILEDINFORMATION.