Design of Advanced Erase MechanismDesign of Advanced Erase Mechanismfor NOR Flash EEPROMfor NOR Flash EEPROM

Amit Berman, June 2006Intel Corporation

AgendaAgenda

Flash Memory Introduction Project’s Targets Current Erase Solution Proposed Methodology for New Mechanism Lab Results and Evaluation Conclusions Questions Session

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Flash Memory IntroductionFlash Memory Introduction

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Substratep-

Drain n+

Source n+

ToxFG

ONOGate

Bit-line

(Vd)

Control Gate

Wordline

(Vg)

--- -

--

Source

(Vs)

- -

What is Flash?- Non-Volatile Memory

- Examples: Cell-phone OS, PC BIOS

MOSFET with floating gate: Information is stored as electrons in the floating gate- Many Electrons – Logic ‘0’

- Few Electrons – Logic ‘1’

Best memory alternative: Low cost, Low power, High density and High speed.

High High DensityDensity

NonNon--VolatileVolatile

UpdateableUpdateable

ROMROMDRAM/DRAM/SRAMSRAM

EPROMEPROM

FlashFlashMemoryMemory

Flash Memory Introduction (2) Flash Memory Introduction (2)

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Id (A)

Vg (V)

E

5

01 2 3 4 5

R P

Substratep-

Drain n+

Source n+

ToxFG

ONOGate

Bit-line(Vd)

Control GateWordline

(Vg)

- -- ---

- ---- -

-- -

-

Source(Gnd)

- ---

Program - CHE Erase – FN tunneling Read – Sensing

Substratep-

Drain n+

Source n+

ToxFG

ONOGate

Bit-line(Float)

Control GateWordlineVg << 0

- - -- ---

Source(Float)

---

-- -- -

-Vwell=positive Vg

Substratep-

Drain n+

Sourcen+

ToxFG

ONOGate

Vread

Control GateVcc

--- -

--

Source

- -

SenseAmp Output

REF

SEN

Drain

I

I

Project’s TargetsProject’s Targets

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Speed-up Erase operation

(bottleneck 0.9sec per block) Improve product reliability by

reducing “Post Erase Repair” phenomena (DPM)

Reduce product test time

Current Erase SolutionCurrent Erase Solution

Channel Erase Pulses Block basis (shared bulk) Increasing pulse series

Erase Verify – Vt Measurement (read) until all block is erased

Disadvantages: Since not all cells are

similar ,some will be over-erased : always logic ‘1’.

Post erase repair – soft programming is needed.

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Proposed MethodologyProposed Methodology

Detect an “Optimum Point” on channel erase where fast and normal bits are erased but slow-erased bits are programmed.

Handle Slow-erased bits with “special care” – erase via drain. Reduce over-erased cells to minimum.

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Lab Results and EvaluationLab Results and Evaluation

We can identify slow-erased bit by constant charge loss in each erase pulse. Flash Vt will be briefly reduced.

Model for slow-erased bits: on erase pulse #10. Trade-off between reducing over-erased bits and erase speed. Erase operation speed is improved from 0.9sec per block to 0.7sec

per block.

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60.00%

65.00%

70.00%

75.00%

80.00%

85.00%

90.00%

95.00%

100.00%

17 19 26 28 29 30 31 32 33 34 35 36 37

Pulse Number

% o

f Era

sed

Ce

lls

vVT 325.0

ConclusionsConclusions

Potential speedup: future implementation on embedded flash microcode and on test program platforms.

Quality and Reliability check is needed. Examine cost-effective trade-off with Q&R and device operation

speed.

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Questions SessionQuestions Session

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