design of fixed-point rounding operators for vhdl-2008vhdl-2008 adds ﬁxed-point data types...

Design of fixed-point rounding operators forVHDL-2008

Nikolaos Kavvadias and K. Masselos{nkavv,kmas}@uop.gr

Department of Computer Science and Technology,University of Peloponnese,

Tripoli, Greece∗ Special thanks to C. Lezos for presenting this paper at the DASIP 2012 venue

23 October 2012

Nikolaos Kavvadias and K. Masselos {nkavv,kmas}@uop.gr Design of fixed-point rounding operators for VHDL-2008

Introduction and motivation

The design of sophisticated DSP platforms involvesspecifications at an increasingly raised abstraction level toconfront with the growing complexity-productivity gapMATLAB and other high-level programming environmentsenable rapid algorithm development and prototypingAn interesting aspect of such frameworks is low-level designfacet generation

ANSI C reference fixed-/floating-point model generationSynthesizable HDL code

Fixed-point rounding (FXPR) is essential for theimplementation of fixed-point datapaths

Z We introduce generic and parameterized VHDL descriptionsof fixed-point rounding operators


Fixed-point rounding in contemporary EDA tools

Rounding operators control the numerical precision involvedin a series of computationsThe FPT (Fixed-Point Toolbox) MATLAB plugin definesfixed-point data typesBesides floor (round towards −∞) and ceil (+∞), it alsodefines fix (zero), round (nearest; ties to +∞), nearest(nearest; ties to greatest absolute value) convergent(nearest; ties to closest even)Supported by the MATLAB HDL CoderGraphLab, AccelDSP (discontinued) and Synopsys SynphonyModel Compiler appear to provide certain support to FXPRVHDL-2008 adds fixed-point data types (ufixed, sfixed)and primitives for arithmetic, scaling and operand resizing

Z We propose generic designs that achieve better timing byabout 30% and similar area demands to the HDL Coder


VHDL-2008 native types for fixed-point arithmetic

Fixed-point arithmetic is seen as an integral representationvariant where a binary point is defined as a notationalartifact to signify negative integer powersVHDL-2008 supports signed (sfixed) and unsigned(ufixed) fixed-point arithmeticsfixed: Assuming integer part width IW > 0, and afractional part of −FW < 0, the representable data range is2IW−1 − 2|FW | to −2IW−1

ufixed: 2IW − 2|FW | to −2IW−1

Resolution: 2|FW |

VHDL examples� �signal fxp1 : sfixed(4 downto -5);signal fxp2 : ufixed(7 downto -8);-- using generics

signal fxp3 : sfixed(IW-1 downto -FW);� �Nikolaos Kavvadias and K. Masselos {nkavv,kmas}@uop.gr Design of fixed-point rounding operators for VHDL-2008

Basic resizing and rounding

resize is a VHDL library function that can be used as arounding and saturation primitive for adjusting the size offixed-point operandsInput: a fixed-point operand (arg), a left and a right indexbound and two additional arguments that specify therounding (underflow) and saturation (overflow) mechanismsOutput: resized operand (y)Rounding of quantized integers, defined by IW > 0,−FW > 0� �if (arg’low > 0) theny := resize(arg, arg’high, arg’low);return y;

end if;� �Rounding of quantized fractionals, defined by IW < 0,−FW < 0, is trivial (assignment to zero)


Implementation of the ceil operator

arg is increased by 1 if ithas a non-zero fractionalpart, otherwise it ispassed directly to resizeThe 2nd mux allows forfixed-point numbers withany FW valueFor hardware synthesis, itis always eliminated atdesign elaboration time


fix and floor

If arg < 0, then it iseither directly resized orfirst incremented by 1,depending on thecomparison of itsfractional part to zeroUnsigned fix (fixu) onlyinvolves resizing argfloor is implemented byfixu


round

Requires comparisons tothe value of 1

2 (ONEHALF)If the fractional part of apositive arg is ≥ 1

2 , then ithas to be incrementedprior resizingThe complementary ruleapplies for a negative argroundu requires a subsetof this circuit


nearest

If the fractional part ofarg is ≥ 1

2 , then itsincremented value needsto be resizedThis is performed by thearg(-1) = ’1’

comparatorAdditional multiplexingcan be eliminated atdesign elaboration timenearestu shares thesame circuit


convergent

Requires comparisons tothe value of 1

2 as well asto determine whether theintegral part of arg is oddThe latter is needed forresolving a tieThe integral part isselected from multiplexersMUX1 and MUX2, basedon the results of thecorrespondingcomparators


Complete VHDL source code for the convergentoperator� �

function convergent (arg : sfixed) return sfixed isvariable result: sfixed(arg’high downto arg’low);variable onehalf: std_logic_vector(-arg’low-1 downto 0) := (others => ’0’);

beginif (arg’high <= 0) thenresult := (others => ’0’); return result;

end if;if (arg’low > 0) thenresult := resize(arg, arg’high, arg’low); return result;

end if;onehalf(-arg’low-1) := ’1’;if (arg(0) = ’1’) thenif (to_slv(arg(-1 downto arg’low)) >= onehalf) thenresult := resize(arg + 1, arg’high, arg’low);

elseresult := resize(arg, arg’high, arg’low);

end if;elseif (to_slv(arg(-1 downto arg’low)) > onehalf) thenresult := resize(arg + 1, arg’high, arg’low);

elseresult := resize(arg, arg’high, arg’low);

end if;end if;if (arg’low < 0) thenresult(-1 downto arg’low) := (others => ’0’);

end if;return result;

end function convergent;� �Nikolaos Kavvadias and K. Masselos {nkavv,kmas}@uop.gr Design of fixed-point rounding operators for VHDL-2008

Speed measurements (XC3S200 Spartan-3 FPGA)

sfixed versions shown

Estimated propagation delay is less than 9ns for the largestconfigurationufixed circuits are faster to sfixed ones by 17.8%(8, 32) operators are faster than their (8, 16) counterparts dueto using the MUXF5 wide multiplexer primitive


Speed measurements (XC6VLX75T Virtex-6 FPGA)

Estimated propagation delay is less than 3ns for the largestconfigurationDesigns are faster by 67% compared to XC3S200nearests has the fastest implementation


Chip area measurements (XC3S200 Spartan-3 FPGA)

sfixed versions are shown

Requirements range from a few to 105 LUTs27% less LUTs required for ufixed operatorsceil is the smallest operator


Chip area measurements (XC6VLX75T Virtex-6 FPGA)

Up to 74 LUTs required for any operator6-input LUTs appear more densely populatednearest is the smallest operator; round for ufixedarithmetic


Architectural comparison to architectures generated bythe Simulink HDL coder

Performed comparisons to fixed-point rounding VHDLimplementations generated by the MATLAB 7.8.0 (R2009a)Simulink HDL coder (hdlcoder)For a fair comparison, the proposed units were rewritten forthe numeric_std package

proposedGeneric, portable descriptions

The same principles applicable tofloating-point formats

No decrement operations needed

No extended internal precision

hdlcoderNon-portable descriptions usingbitwise tricks

Not applicable to floating-pointformats

Decrement operations

Need for an additional bit ofaccuracy


Speed measurements comparison to the Simulink HDLCoder

The proposed sfixed units outperform the hdlcoder ones, by31.3%, 27.7% and 27.6%, respectivelyExcept ceilu, unsigned hdlcoder units are faster

Z This is due to unsigned bitwise tricks applied by hdlcoder(e.g. convergentu uses a reduction OR gate)


Chip area measurements comparison to the SimulinkHDL Coder

The proposed sfixed units are comparable to the hdlcoderonesThe proposed rounds requires much less than its counterpartHowever, hdlcoder units consume much less area(38.5%-65.7%)


Conclusions

Novel schemes for implementing fixed-point binary roundinghave been introducedImplemented using vendor-independent, generic, portable,standard-compatible VHDLThorough experimental measurements have been shown overthree representative FPGA devicesComparisons to rounding units generated by the SimulinkHDL coder (hdlcoder) reveal that the proposed designs forsigned arithmetic are faster by 30% with comparable areademandshdlcoder designs are generally faster for unsigned arithmeticThe fixed-point extensions library is available as open-source:http://www.opencores.org/project,fixed_extensions


http://www.opencores.org/project,fixed_extensions

References

S. Roy and P. Banerjee, ‘‘An algorithm for trading off quantization error withhardware resources for MATLAB-based FPGA design,’’ IEEE Transactions onComputers, vol. 54, no. 7, pp. 886–896, July 2005.

MATLAB Fixed-Point Toolbox. [Online]. Available:http://www.mathworks.com/products/fixed/

R. Yates, ‘‘Fixed-point arithmetic: An introduction,’’ Digital Signal Labs, Technicalreference, July 7 2009.

Algorithmic C data types. [Online]. Available:http://www.mentor.com/products/esl/high_level_synthesis/ac_datatypes

IEEE 1076-2008 Standard VHDL Language Reference Manual, Jan. 2009.

D. Bishop. VHDL-2008 support library. [Online]. Available:http://www.eda.org/fphdl/

Simulink HDL Coder. [Online]. Available:http://www.mathworks.com/products/slhdlcoder/

B. L. Gal and E. Casseau, ‘‘Word-length aware DSP hardware design flow based onhigh-level synthesis,’’ Integration, the VLSI Journal, Elsevier, vol. 62, pp. 341–357,March 2011.

Xilinx home page. [Online]. Available: http://www.xilinx.com


http://www.mathworks.com/products/fixed/

http://www.mentor.com/products/esl/high_level_synthesis/ac_datatypes

http://www.eda.org/fphdl/

http://www.mathworks.com/products/slhdlcoder/

http://www.xilinx.com

design of fixed-point rounding operators for vhdl-2008vhdl-2008 adds ﬁxed-point data types...

Documents