Design of gate stacks for improved program/erase speed, retention and process margin

aiming next generation metal nanocrystal memories

This article has been downloaded from IOPscience. Please scroll down to see the full text article.

2009 Semicond. Sci. Technol. 24 115009

(http://iopscience.iop.org/0268-1242/24/11/115009)

Download details:

IP Address: 222.111.165.128

The article was downloaded on 09/10/2009 at 19:58

Please note that terms and conditions apply.

The Table of Contents and more related content is available

HOME | SEARCH | PACS & MSC | JOURNALS | ABOUT | CONTACT US

IOP PUBLISHING SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Semicond. Sci. Technol. 24 (2009) 115009 (11pp) doi:10.1088/0268-1242/24/11/115009

Design of gate stacks for improvedprogram/erase speed, retention andprocess margin aiming next generationmetal nanocrystal memories

Jaeman Jang1, Changmin Choi1, Jang-Sik Lee2, Kyeong-Sik Min1,Jaegab Lee2, Dong Myong Kim1 and Dae Hwan Kim1

1 School of Electrical Engineering, Kookmin University, 861-1, Jeongneung-dong, Seongbuk-gu, Seoul,136-702, Korea2 School of Advanced Material Engineering, Kookmin University, Seoul 136-702, Korea

E-mail: drlife@koomin.ac.kr

Received 29 April 2009, in final form 27 August 2009Published 9 October 2009Online at stacks.iop.org/SST/24/115009

Abstract

In this work, gate stacks in metal nanocrystal (NC) memories, as promising next generationstorage devices and their systems, are extensively investigated. A comparative analysis andcharacterization of the program/erase (P/E) speed, retention and the process margin of cobaltNC memories including high-k and bandgap engineering technologies are performed by usingthe technology computer-aided design (TCAD) simulation. It is shown that NC memory withhigh-k dielectric (HfO2) has better performance in P/E speed and retention when the diameterof NC is below 5 nm. When the diameter is beyond 5 nm, on the other hand, thebandgap-engineered bottom oxide gate structure shows improved performance in P/E speedand retention. From the process margin perspective, as the permittivity of the dielectric getslarger, the limits of the diameter and the density of NCs allow the degree of freedom tobecome larger.

(Some figures in this article are in colour only in the electronic version)

1. Introduction

Recently, memory structures employing discrete traps ascharge storage media have been under active research anddevelopment as promising candidates replacing dynamicrandom access memories (DRAMs) or flash memories. Byutilizing discrete traps as a charge storage element, nitride-based charge trap memories are known to be more immuneto local oxide defects. Thus, they exhibit longer retentiontime (RT) and allow more aggressive tunnel oxide scalingthan conventional flash memories [1–11]. While precisecharacterization and engineering of the nitride trap parameters(i.e. spatial distribution, energy level and program/erase (P/E)cycling effects) are still a challenging issue in the nitride-basedcharge trap memory technologies (e.g. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) [1–6], Nitride-Read-Only-Memory

(NROM) [7], Silicon-Al2O3-Nitride-Oxide-Silicon (SANOS)[8] and TaN-Al2O3-Nitride-Oxide-Silicon (TANOS) [9–11]),nanocrystal (NC) charge trap memories are expected to bepromising next-generation storage devices [12–16]. NCcharge trap memories give advantages over the conventionalfloating-gate or nitride-based nonvolatile memories in termsof improved designability due to very controllable state-of-the-art process forming NC arrays [17, 18]. Ultralowpower few-electron memories are also possible through theCoulomb blockade effect [19]. In particular, by adopting aconducting metal for NCs, metal NC memory has significantadvantages with higher density of states, stronger couplingwith conduction channel, wider range of available workfunction and smaller energy perturbation due to carrierconfinement [20, 21]. Also, high-k and bandgap engineering

0268-1242/09/115009+11$30.00 1 © 2009 IOP Publishing Ltd Printed in the UK

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

technologies can be employed to metal NC memories asperformance boosters [22–24].

The critical mechanisms playing major roles ofdetermining electrical characteristics of metal NC memoriessuch as three-dimensional (3D) field enhancement effectand the NC diameter/density dependence of tunnelingcurrent density/charging energy can be commonly predictableand also described in previous systematic works [20, 21,25, 26]. Nevertheless, it should be noted that researchersand engineers familiar with designing and optimizing thecritical mechanisms have difficulty in understanding variousmetal NC memories based on high-k and/or bandgapengineering technology. Between respective mechanisms andtheir technology dependence there exists a complicated trade-off. Therefore, the quantitative design guide of various gatestacks for metal NC memories is strongly required.

In this work, by investigating the effects of NC diameter(D) and density (N) (consequently NC-to-NC space (S)) on P/Espeed and retention in various gate stacks including high-k andbandgap engineering technologies, a quantitative design guidefor cobalt (Co) [27, 28] NC memories is proposed in orderto pursue high performance next generation NC memories.Main results are extracted by using the technology computer-aided design (TCAD) simulation [29–33] in which most ofthe abovementioned critical mechanisms are incorporated.Also, in advance, the validity of used TCAD simulationplatform is confirmed by comparing the simulation resultswith the experimental ones. Additionally, the related physicalmechanisms are addressed while discussing the simulationresults.

2. TCAD simulation platform for gatestack-dependent performance of NC memories

2.1. Fabrication of NC memory devices for calibratingpractical TCAD simulation parameters

The proposed device is based on the same technology thathas been thoroughly described in [27, 28]. All of thesamples were prepared on p-type Si substrates. Prior tofilm deposition, the substrates were cleaned chemically usingaqueous mixtures of H2SO4-H2O2, followed by a bufferedhydrofluoric acid dip, with deionized water rinses. HfO2

tunneling oxide layers (4 nm thick) were then deposited onthe substrates using a sputtering system. Co NCs weresynthesized using polystyrene-block-poly(4-vinyl pyridine)(PS-b-PVP) purchased from Polymer Source, Inc. Co as ametallic NC was selected not only because it has a suitablework function (φm = 4.25 eV) for such applications, butalso because it exhibits a low anneal temperature for NCformation which is advantageous to the quality of underlyingtunneling HfO2 dielectrics. Combining the advantages ofboth metal NC and high tunneling barrier, an excellent dataretention characteristic has been achieved without yielding theprogramming efficiency. Detailed NC synthesis proceduresand device fabrication methods can be found elsewhere [27].

Two kinds of samples were fabricated. To prepare theblocking oxide layers, 25 nm thick Al2O3 (sample 1) and HfO2

(sample 2) layers were deposited using a sputtering system,

using the same method as that used for the deposition of thetunneling oxide. Through the lift-off process, 100 nm thickplatinum (Pt) gate electrodes with an area of 4.70 × 10−5 cm−2

were formed. The capacitance at room temperature wascharacterized at 1 MHz using an HP4284 A impedanceanalyzer. The conduction properties were probed using theKeithley 2400 source meter and Agilent 4155C semiconductorparameter analyzer at room temperature.

Since the charge trapping efficiency of the metallic NCs(directly related to the memory window) is much higherthan that of the oxide NCs, a reduction process is carriedout using a pure hydrogen gas. After the oxygen plasmatreatment, the micelle templates, whose core was loaded withCo salt, were completely removed resulting in Co oxide NCarrays. In order to reduce the Co oxide to a metallic Co,hydrogen annealing was carried out in a vacuum furnaceat 300 ◦C for 30 min. It was confirmed by the x-rayphotoelectron spectroscopy (XPS) analysis that Co oxide hasbeen transformed to metallic Co after hydrogen annealing[27]. During hydrogen annealing, actually we performed gasannealing after the device fabrication at 400 ◦C for 30 min toreduce the dangling bonds. This temperature is higher thanthe reduction temperature. Thus, we checked the chemicalstates of HfO2 films after performing gas annealing by usingXPS analysis [27]. Also, we checked the binding energy ofthe Hf4f and O1s peaks, which are related to HfO2. Thepeaks were obtained from the binding energy of 16.7 eVand 530 eV for Hf4f7/2 and O1s, respectively. These valuesare quite matched with the stoichiometric HfO2 data. Thus,it was confirmed that the HfO2 films with a stoichiometriccomposition can be maintained after forming gas annealing[28]. The average D and N of Co NCs are as follows: D/N =14 nm/6.4 × 1010 cm−2 (sample 1) and 10 nm/1 × 1011 cm−2

(sample 2), respectively. Finally, it was confirmed thatthe hexagonal-ordered NC arrays with a very small sizedistribution were well formed.

2.2. Comparison of TCAD simulation results with measuredC–V curves

By employing the Synopsys Sentaurus TCAD simulator,simulation was performed for the Co NC memory [29].Experimental and simulation parameters are summarized intable 1. The P/E conditions are as follows: the P/E voltageVPGM/VERS = 20/−14 V and the P/E time TPGM/TERS =30/10 ms, respectively. In order to confirm the validityof the simulation result, the simulated capacitance–voltage(C–V) characteristic was compared with the measured C–Vcurve in the same structure. Figure 1 shows the 3Dschematic illustration of the hexagonal-arrayed Co NCs usedin the TCAD simulation. The simulated and measured C–Vcharacteristics are shown in figure 2 ( sample 1 in figure 2(a)and sample 2 in figure 2(b)). It is found that the simulated C–Vcharacteristic agrees very well with the measured C–V curvein terms of both the threshold voltage VT window (�VT ) andthe detailed slope of capacitance value, except for the deepdepletion of the measured C–V curve. Consequently, ourTCAD simulation platform is turned out to be well calibrated.

2

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

Table 1. Experimental and simulation parameters for metal NC memory devices.

Sample 1 Sample 2

Geometrical parameters Experimental Simulation Experimental Simulation

Bottom oxide, Tbot HfO2/4 nm HfO2 (25ε0)/4 nm HfO2/4 nm HfO2 (25ε0)/4 nmTop oxide, Ttop Al2O3/25 nm Al2O3 (8.9ε0)/25 nm HfO2/25 nm HfO2(25ε0)/25 nmNanocrystal material Cobalt Cobalt (φm = 4.25 eV) Cobalt Cobalt (φm = 4.25 eV)Nanocrystal diamter, D 14 nm 14 nm 10 nm 10 nmNC-to-NC spacing, S 24 nm 24 nm 25 nm 25 nmNanocrystal density, N 6.4 × 1010 cm−2 6.4 × 1010 cm−2 1.0 × 1011 cm−2 1.0 × 1011 cm−2

Substrate doping concentration 5 × 1016 cm−3 5 × 1016 cm−3 5 × 1016 cm−3 5 × 1016 cm−3

Figure 1. View of the 3D simulated structure with hexagonalarrayed Co NCs.

3. Modeling of NC memories with promising gatestacks

3.1. Structures of gate stacks for high-performance NCmemories

Structures of investigated metal NC memory gate stacks areshown in figure 3. A p-type doping of silicon substrate is 1 ×1017 cm−3. Co (φm = 4.25 eV) NCs were used as chargestorage media. Sample A is a conventional structure usingSiO2 as top and bottom oxides. For sample B, a bandgap-engineered bottom oxide (ONO: SiO2/Si3N4/SiO2) is used forimproved P/E efficiency and retention characteristic [30–33].Sample C has a double stacked NC improving the retentioncharacteristic utilizing the quantum confinement and Coulombblockade in lower NCs [34, 35]. Al2O3 used in sampleD and HfO2 used in sample E, as a high-k dielectric, areemployed as the top oxide for suppressed inter-layer leakageand improved electrostatic field [36]. In the simulation,the dielectric constant εr = 3.9, 8.9 and 25 and the bandgapEg = 9 eV, 8.9 eV and 5.7 eV, the band offset from gate�EC gate = 3.15 eV, 2.75 eV and 1.55 eV, �EV gate =5.75 eV, 6.05 eV and 4.05 eV, the band offset from Si �EC Si =3.15 eV, 2.75 eV and 1.55 eV, �EV Si = 4.68 eV, 4.98 eVand 2.98 eV,and the band offset from NC �EC NC = 3.7 eV,3.4 eV and 2.2 eV, �EV NC = 5.2 eV, 5.4 eV and 3.4 eV forSiO2, Al2O3 and HfO2, respectively, are used with parameterssummarized in table 2. To combine the advantages of samplesB and D, high-k dielectric (Al2O3) is stacked on the bandgap-engineered bottom oxide for sample F. The band offset, from

(a)

(b)

Figure 2. Comparison of the simulated C–V curve andcorresponding experimental ones for (a) sample 1 (D/N =14 nm/6.4 × 1010 cm−2) and (b) sample 2 (D/N = 10 nm/1 ×1011 cm−2), respectively.

SiO2 to Si3N4 �EC = 1 eV and �EV = 3 eV, is used forbandgap-engineered bottom oxide. The range of D and N is3–7 nm and 1 × 1011–1 × 1012 cm−2, respectively. For afair comparison, the equivalent oxide thickness (EOT) of topoxides for all samples is set to be the same (table 2).

3.2. P/E and retention dynamics of metal NC memories

Figure 4 shows the schematic energy band diagram of sampleA that is a reference sample. As shown in table 2, an NC isseparated from the channel by a thin bottom oxide (∼3 nm)so that the direct tunneling becomes a dominant mechanism

3

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

Figure 3. The schematics of various metal NC memory gate stacks.

(a) (b) (c)

Figure 4. The schematic energy band diagram of sample A during (a) program, (b) erase and (c) retention operations.

Table 2. Parameters for the simulation of various metal NC memory gate stacks.

A B C D E F

Bottom oxide SiO2 O/N/O NC/SiO2 SiO2 SiO2 O/N/OTbot 3 nm 1.2/1/1.5 nm D = 1/3 nm 3 nm 3 nm 1.2/1/1.5 nm

Top oxide SiO2 SiO2 SiO2 Al2O3 HfO2 Al2O3

Ttop 12 nm 12 nm 12 nm 20 nm 50 nm 20 nmNC material Cobalt (φm = 4.25 eV)Substrate doping 1 × 1017 cm−3 (Boron)

for injecting and extracting NC charges. The injection of anelectron dominantly occurs from the inversion layer to theNC (Je SN in figure 4(a)) when the control gate is sufficientlypositive biased (program operation in figure 4(a)). In contrast,the extraction of an electron dominantly occurs from the NCto the accumulation layer (Je NS in figure 4(b)) when thecontrol gate is sufficiently negative biased (erase operationin figure 4(b)). Furthermore, figure 4(c) corresponds to aretention operation. In our model, all of the tunneling currentcomponents such as Je SN: the electron tunneling current from

Si to NC, Je NG: the electron tunneling current from NCto gate, Jh NS: the hole tunneling current from NC to Si,and Jh GN: the hole tunneling current from gate to NC areincluded. The main mechanisms are the Fowler–Nordheim(FN) tunneling and the direct tunneling. They depend on boththe oxide thickness and the bias voltage which mechanism isdominant. For instance, the dominant mechanism of Je NG

during P/E operation is FN tunneling due to thick top oxidewhile it is the direct tunneling during a retention operation, asseen in figure 4. Electron tunneling current densities are given

4

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

Figure 5. Equivalent capacitor model in the metal NC memories.

as follows:

Jdirect tunneling = Aφb

VOX

(2φb

VOX− 1

)E2

OX

× exp

(−B[1 − (1 − VOX/φb)1.5]

EOX

),

for VOX <φb (1)

JFN tunneling=AE2OXexp

( −B

EOX

), for VOX > φb (2)

A=q3/(8πhφb), B = 8π(2mOX)1/2φ3/2b

/(3hq). (3)

Here, φb is the oxide tunneling barrier height determined byband offset, VOX is the voltage across the tunneling oxide,EOX is the electric field across the tunneling oxide, mOX isthe oxide effective mass, q is a single electron charge andh is Plank constant. The temperature effect was consideredby the TCAD model as the integration of allowable energylevels in calculating a tunneling probability. Also, a classicallucky electron model and the hydrodynamic model wereincorporated into our TCAD model.

After program operation, these injected charges screen thegate field and reduce the potential in the inversion layer. Asa result, the threshold voltage of the device (VT ) is shifted tobe more positive and the magnitude of the shift (�VT ) can bedescribed as [25, 37]

�VT = R�Qinj

Ctop 3D≈ qNp

εTOX

[Ttop +

εTOX

2εNCD

](4)

R = β

(D

D + S

)= β × D

√N (5)

Ctop 3D = k · Ctop 1D. (6)

Here, p is the average number of electrons stored per single NC,εTOX is a top oxide dielectric constant, εNC is an NC dielectricconstant, Ttop is the thickness of top oxide, R (a function of Dand S) is a factor correcting for the nonuniform coverage ofthe channel area by discrete NCs, β is a correction constantand k is also a correction constant translating a uniform plateto a spherical curvature as shown in figure 5. A change in theinjection charge density (�Qinj) of the NC during the programtransient was calculated by using the continuity equation as

�Qinj. = (Je SN − Je NG + Jh NS − Jh GN)�t (7)

Figure 6. Simulated program time evolution of the injection charge,Qinj in the single NC at VG = 12 V and 9 V for sample A, D = 5 nm,and N = 5 × 1011 cm−2.

(a) (b)

Figure 7. The schematic diagram of energy band in sample Aillustrating the effect of the NC charging energy CE on (a) programand (b) retention operation.

where Jh GN is negligible because Ttop is sufficiently large.The erase transient is analyzed by observing the holes. Inthe case of program dynamics, the injection time of the nthelectron (tn) can be written as [25]

tn = t(n−1) +q

σJnet(n − 1)(8)

where σ is the capture cross section and Jnet(n − 1) is the netcurrent density when the (n − 1)th electron is injected to theNC. Figure 6 shows the saturated injection charge (Qinj) after10−5 s and 10−1 s for the gate voltage VG = 12 V and 9 V, (forsample A, D = 5 nm, and N = 5 × 1011 cm−2) respectively.Here, the charging energy (CE) of single NC is given as

CE = q2

CNC total= q2

Ctop 3D + Cbot 3D + Cnei(9)

where Cnei is the capacitance between NC and NC. As thecharge is injected into the NC during a program operation,both the conduction band minimum level (EC) of NC and theCE increase as shown in figure 7(a). Then, the increasedCE suppresses the succeeded injection of the next charge.Consequently, the simulation result shown in figure 6 is veryreasonable. The other significant mechanism in P/E operationis the 3D field enhancement effect illustrated in figure 8. Basedon the Gaussian law, the increase of NC curvature and Sreinforces the 3D field enhancement.

5

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

Figure 8. The schematic diagram illustrating the 3D fieldenhancement effect around NCs. Dotted lines indicate potentialcontours. As the curvature of NC increases and the NC-to-NC spacegets larger, the 3D field enhancement becomes more reinforced.

During the retention, a discharge current caused by theelectron tunneling from NC to the substrate (Je NS) plays amajor role in retention properties. Here, the RT is definedas the time taken for the stored charges to be decreased by afactor 10% at zero gate bias (as shown in figure 12(a)). Inthis case, the hole tunneling from Si to NC (Jh SN), Je NG

and Jh GN is ignorable due to a large barrier height at thetunneling interface and a large Ttop. The discharging currentfrom NC to the neighboring NCs can also be ignored becauseof relatively small potential difference. Thus, the dischargecurrent strongly depends on the level of EC in NCs, i.e. theCE of NC. The decrease of CE results from the increase ofCtop 3D, Cbot 3D and Cnei and mitigates both EOX and VOX in(1). Eventually, the decrease of CE leads to the increase of RT,i.e. improved retention properties as illustrated in figure 7(b).As qualitative design guides, the engineering techniques suchas employing high-k top oxide and/or thinner Ttop, andenlarging D make the retention better. Here, it should be notedthat the parameters determining Ctop 3D, Cbot 3D and Cnei (e.g.Ttop, εTOX, D, S and N) are not perfectly independent of oneother. For instance, both D and N significantly influence onCtop 3D being entangled with the 3D field enhancement effect.Also, the decrease of CE by reducing Tbot worsens retentionproperties due to the increase of EOX in (1). On the otherhand, the decrease of CE by making Ctop 3D larger can degraderetention properties due to the increase of coupling ratio (CR)followed by the increase of Qinj. Also, there is a trade-offbetween (�VT ) and RT as seen in (4) and (9). Therefore, aquantitative guide becomes more important.

(a) (b)

Figure 9. The threshold voltage VT versus (a) program time and (b) erase time in metal NC memories for D = 3 nm, S = 11 nm, N = 5 ×1011 cm−2.

Figure 10. The VT window (�VT ) versus NC diameter D for allsamples with N = 5 × 1011 cm−2. P/E condition: Fowler–Nordheim (FN), VPGM/VERS = ±12 V, TPGM/TERS = 30 ms.

4. Results and discussion: gate stack-dependentcharacteristics of metal NC memories

4.1. NC diameter D-effect on the characteristics of metal NCmemories

Figure 9 shows the P/E speed of NC memories with D =3 nm and S = 11 nm (N = 5 × 1011 cm−2) for samplesA–D. The P/E operation is performed by biasing the controlgate voltage VPGM/VERS = ±12 V, respectively, keeping thesource and drain grounded. In order to analyze the programefficiency much clearly, we need to separate two effects. Oneis Qinj under a fixed VPGM/VERS. The other is �VT undera fixed Qinj. Table 3 shows VT for samples A–D with thesame injected charge density Qinj. (VT 1 and VT 2 correspondto Qinj = −6.6 × 10−19 and 0 (C/NC), respectively.) Inorder to make the sample-dependence VT clearer under a fixedQinj, a doubled Qinj (−6.6 × 10−19 C/NC) in the case ofsample A (with D = 3 nm, VPGM = 12 V, TPGM = 30 ms) wasused. Sample A shows the largest VT at the same NC charges,meaning the best efficiency transforming the NC charges tothe channel potential. Nevertheless, sample D with Al2O3 topoxide shows a faster P/E speed than other samples (samplesA–C) with SiO2 top oxide as shown in figure 9. It is attributed

6

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

(a) (b)

Figure 11. (a) E-field and potential in the programming condition of VPGM = 12 V for sample A (N = 5 × 1011 cm−2). (b) The potentialcontour of NC memories for samples A and E (D = 3, 7 nm) for the monotonic potential contour spacing is 0.44 V.

(a) (b)

Figure 12. (a) The injection charges versus time at VG = 0 V and T = 85 ◦C. RT is defined as the time required by the injection charge todecrease by a factor 10%. (b) RT versus NC diameter, D for respective samples. RT increases with the increase of D due to lower CE(= q2/CNC total). Sample B with a bandgap-engineered bottom oxide shows better retention characteristic than those of the others, atD > 5 nm due to the thick O/N/O layer.

to a higher CR between NC and the channel in sample D,i.e. the increase of Ctop 3D despite the same EOT of top oxideregardless of sample type. Additionally, a thicker top oxidein sample D helps to suppress the electron tunneling currentfrom the NC to the control gate (Je NG in figure 4(a)) duringthe program operation.

The diameter D-dependent threshold voltage window�VT (VT is defined VGS at IDS = 0.1 μA for VDS = 0.05V) under a fixed N (5 × 1011 cm−2) is shown in figure 10.In order to explain this complicated gate stack dependenceof the relation between P/E speed and D, the E-field andpotential contour of samples A and E are shown in figure 11.As D increases, the program efficiency increases due to boththe reduced CE and the increased electric field (E-field)resulting from higher Ctop 3D by the shrunken Ttop

′ (defined

Table 3. The NC memory gate stack dependence of VT under thesame injection charges.

Diameter Sample A Sample B Sample C Sample D

VT 1 (V) [Qinj = −6.6 × 10−19 (C/NC)]2 nm 3.43 3.12 3.43 2.923 nm 3.17 2.87 3.16 2.77

VT 2 (V) [Qinj = 0 (C/NC)]2 nm 0.64 0.61 0.65 0.563 nm 0.61 0.58 0.62 0.55

(VT 1–VT 2)/VT 2

2 nm 4.36 4.11 4.28 4.213 nm 4.20 3.95 4.10 4.04

by Ttop−D as seen in figure 3) although the NC sphericalcurvature-induced E-field enhancement effect is mitigated by

7

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

Figure 13. The electrostatic potential contours of sample A withD = 3 nm, VG = 12 V. (a) N = 1 × 1011 cm−2 and (b) N = 1 ×1012 cm−2. The potential contour spacing is 0.44 V.

shrunken S. These physical mechanisms agree well with thesimulated D-dependence of E-field and potential as seen infigure 11(a). Particularly, it is worthy to note that the P/Eefficiency enhancement with increasing D in samples withhigh-k dielectrics is alleviated compared to those in othersamples (as in figure 10). As above mentioned in figure 8,the larger �VT with increased D is compensated in the samples

(a) (b)

(c) (d )

Figure 14. (a) The number of injected electrons per single NC versus NC density, N (D = 5 nm). (b)–(d) �VT versus NC density, N forsamples with D = 3, 5 and 7 nm. FN P/E condition: VPGM/VERS = ±12 V and TPGM/TERS = 30 ms.

with high-k dielectrics (samples D–F) due to a high-k inducedrelease of E-field, consistent with the simulated potentialcontour shown in figure 11(b). Moreover, in cases of sampleswith high-k dielectrics, the increase of CR (between a controlgate and NCs) due to increasing D followed by thinner Ttop

′

gets diminished in comparison with cases of samples A–Cbecause of thicker top oxide of samples D–F (i.e. the shrunkenratio of �Ttop’/�D). Consequently, as the permittivity of thedielectric becomes more higher, the P/E efficiency becomesless sensitive to D, and the merit of higher P/E speedof samples using high-k is diluted for the diameter D >

4–5 nm.Next, the retention characteristics of the NCs with

specified gate stacks are comparatively investigated withTCAD simulation. Figure 12(a) shows the time-dependentcharge loss per single NC for sample A with simulationparameters as D = 5 nm, S = 9 nm (N = 5×1011 cm−2), VG =0 V and T = 85 ◦C. RT is extracted by the 10% charge loss atthe same initial charges (−8.0 × 10−18 C/NC) for all samples.As shown in figure 12(b), RT increases with increasing D dueto the lower CE (=q2/CNC total). Sample B with a bandgap-engineered bottom oxide shows a more improved retentioncharacteristic than those of others for D > 5 nm because of thethick O/N/O layer (the charge loss (Je NS) can be suppressedduring the retention) [30–33]. The D-dependence of RT in

8

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

(a) (b)

(c) (d )

Figure 15. (a) Simulated conduction band minimum EC diagram for sample A (D = 5 nm, Qinj = −8.0 × 10−18 C/NC) with N = 2.5 ×1011 cm−2 and N = 7 × 1011 cm−2, respectively. As N increases from 2.5 × 1011 cm−2 to 7 × 1011 cm−2, the CE increases about 0.5–1 eV.(b)–(d) RT versus NC density, N for all samples with D = 3, 5 and 7 nm, respectively.

samples with a high-k dielectric becomes less conspicuous,because the increased CNC total (decrease of the CE) withincreasing D is relatively weak function of D, as is the case ofthe D-dependence of P/E efficiency, since the decreased ratioof Ttop

′ is smaller due to thicker Ttop.

4.2. NC density N-effect on the characteristics of metal NCmemories

Figure 13 shows the electrostatic potential contours of sampleA with D = 3 nm, VG = 12 V and N = 1 × 1011 cm−2 (a)and N = 1 × 1012 cm−2 (b). The increased N under a fixedD (shrunken S) makes CE higher and reduces the 3D fieldenhancement as shown in figure 8 [38]. Thus, Qinj decreasesas shown in figure 14(a). However, the final injection charges,�Qinj, are determined by the multiplication of NC density Nand injection charge per single NC, as shown in (4). Thus, �VT

increases and is saturated or decreases again with increasing Nunder the same D, as seen in figures 14(b)–(d). Sample E usingHfO2 as a top oxide shows more enhanced P/E efficiency thanthose of the others, at D = 3 nm (figure 14(b)); however, inthe case of D = 7 nm, sample B with a bandgap-engineeredbottom oxide has better performance as shown in figure 14(d).

As shown in figure 15(a), the level of EC of NC becomeshigher by 0.5–1 eV due to increasing CE when N is changedfrom 2.5 × 1011 cm−2 to 7 × 1011 cm−2. Figures 15(b)–(d)show the RT versus N for D = 3, 5, and 7 nm. While sampleE with HfO2 as the top oxide shows more improved retention

characteristics than those of the others at D = 3 nm, sample Bwith a bandgap-engineered bottom oxide has better RT for thecase of D = 7 nm.

In conclusion, from the perspective of the N-dependenceof �VT , there is an optimum condition as shown in figure 14.However, the N-dependence of RT shows the negative slopedue to the increase of CE. Furthermore, it shows thecomplicated sample dependence as shown in figure 15 sinceRT is entangled with the sample-dependent CR and �Qinj.

4.3. Process margin on the characteristics of metal NCmemories

Process margins for metal NC memories are investigated andschematically shown in figure 16. The process margin ofNC memories in the perspective of D and S (eventually N) islimited by the performance parameters defined by the systemrequirement and the available process technology. In eachplot, five lines correspond to respective criteria as follows:(1) �VT � 4 V limit at VPGM/VERS =±12 V during TPGM/TERS

= 30 ms, (2) 10 year RT limit at T = 85 ◦C, (3) NC-to-NC interaction limit (S � 4 nm), (4) the minimum N (>1 ×1011 cm−2) and (5) the available range of D (>1 nm, <10 nm).The area of the shaded region means the allowed range ofD and S, i.e. process margin, whose area is relatively givenas 92:104:90:101:152:112 (in the order of samples A–F),respectively. It is noticeable that sample E clearly shows thewidest process margin.

9

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

(a) (b)

(c) (d )

(e) (f )

Figure 16. Process margins for various metal NC memory gate stacks. For all samples, the lines indicate required criteria for acceptablememory cell performance: �VT (>4 V), RT (>10 years), minimum and maximum D (>1 nm, <10 nm), N (>1×1011 cm−2) and NC-to-NCinteraction limit, S (>4 nm), respectively. The area of shaded region means the allowed range of D and S, i.e. process margin, which is92:104:90:101:152:112 (in the order of samples A–F). It is noticeable that sample E shows the widest process margin.

(a) (b)

Figure 17. (a) �VT versus program voltage VPGM for the scaled NC memory gate stacks (by adding the first type combiningbandgap-engineered bottom oxide/HfO2 dielectric as top oxide with Ttop = 15 nm and the second type corresponding sample F with Ttop =12 nm) in comparison with samples B and E. (b) The retention characteristics as a function of D for the scaled NC memory (sample F withTtop = 12 nm).

10

Semicond. Sci. Technol. 24 (2009) 115009 J Jang et al

4.4. Design for low P/E voltage operation of metal NCmemories

For low-voltage P/E operation, the EOT of the top oxideshould be scaled down to enhance the CR between a controlgate and NCs. However, the scaling of the physical thicknessof the top oxide induces an increased inter-layer leakagecurrent. Eventually, the high-k dielectric is a promisingsolution as the top oxide dielectric. As shown in figure 17(a),the scaled NC memory (bandgap-engineered bottomoxide/HfO2 dielectric as the top oxide with Ttop = 15 nm)has available memory window (�VT = 1.5 V) even withVPGM/VERS = ±5.5 V (below 6 V). Also, as shown infigure 17(b), the scaled NC memory (sample F with Ttop =12 nm) has better a retention characteristic thanabovementioned samples B and E due to the decreased CEby increasing Ctop 3D.

5. Conclusion

The P/E speed, the retention and the process margin of metallicCobalt NC memories, as a promising next generation highperformance storage device, including high-k and bandgapengineering technologies were comparatively investigated andbenchmarked by using the TCAD simulation. In addition,complicated N- and D-dependence of the P/E speed andretention characteristic was systematically characterized inperspective of 3D CR, E-field enhancement effect, high-keffect and NC CE. These results show that, in terms of P/Espeed and RT, NC memory with high-k dielectric (HfO2) showsbetter performance when D of NC is below 5 nm. When D islarger than 5 nm, on the other hand, the bandgap-engineeredbottom oxide gate structure shows improved performance inP/E speed and RT. From the viewpoint of the process margin,the permittivity of the dielectric becomes higher, limits of Dand N of NCs allow the degree of freedom to be larger. Ourresult gives a unified guideline for and insight into the designand analysis of advanced gate stacks for next generation metalNC memories.

Acknowledgments

This work was supported by the Korea Science andEngineering Foundation (KOSEF) grant funded by the Koreagovernment (MEST) (no R11-2005-048-000 00-0), and theCAD software was supported by IC Design Education Center(IDEC).

References

[1] Tsai W J, Zous N K, Liu C J, Liu C C, Chen C H, Wang T,Pan S and Lu C-Y 2001 IEDM Tech. Dig. pp 719–22

[2] White M, Yang Y, Ansha P and French M L 1997 IEEE Trans.Compon. Packag. Manuf. Technol. 20 190–5

[3] She M, Takeuchi H and King T J 2003 IEEE Electron DeviceLett. 24 309–11

[4] White M H, Adams D A and Bu J 2000 IEEE Circuits Devices16 22–31

[5] Xuan P, She M, Harteneck B, Liddle A, Bokor J and King T-J2003 IEDM Tech. Dig. pp 609–13

[6] Sugizaki T, Kobayashi M, Ishidao M, Minakata H,Yamaguchi M, Tamura Y, Sugiyama Y, Nakanishi Tand Tanaka H 2003 VLSI Symp. Tech. Dig. pp 27–8

[7] Eitan B, Paven P, Bloom I, Aloni E, Frommer A and Finzi D2000 IEEE Electron Device Lett. 21 543–5

[8] Zhao Y, Wang X, Shang H and White M 2006 Solid-StateElectron. 50 1667–9

[9] Wang X and Kwong D-L 2006 IEEE Trans. Electron Devices53 78–82

[10] Wann H C and Hu C 1995 IEEE Electron Device Lett. 16 491–3[11] Lee C H, Choi K I, Cho M K, Song Y H, Park K C and Kim K

2003 IEDM Tech. Dig. pp 613–6[12] Hanafi H I, Tiwari S and Khan I 1996 IEEE Trans. Electron

Devices 43 1553–8[13] King Y C, King T-J and Hu C 2001 IEEE Trans. Electron

Devices 48 696–700[14] Liu Z, Lee C, Narayanan V, Pei G and Kan E C J. Solid-State

Circuits to be published[15] Tiwari S, Rana F, Chan K, Hanafi H, Chen W and Buchanan D

1995 IEDM Tech. Dig. pp 521–4[16] Straub S et al 2003 IEDM Tech. Dig. pp 601–5[17] Romanov A E and Speck J S 1999 Appl. Phys. Lett. 74

22801–3[18] Heidemeyer H, Single C, Zhou F, Prins F E, Kern D P

and Plies E 2000 J. Appl. Phys. 87 4580–5[19] Molas G, Deleruyelle D, De Salvo B, Ghibaudo G, Gely M,

Jacob S, Lafond D and Deleonibus S 2004 IEDM Tech. Dig.pp 877–80

[20] Liu Z, Lee C, Narayanan V, Pei G and Kan E C 2002 IEEETrans. Electron Devices 49 1606–13

[21] Liu Z, Lee C, Narayanan V, Pei G and Kan E C 2002 IEEETrans. Electron Devices 49 1614–22

[22] Lee J J, Wang X, Bai W, Lu N, Liu J and Kwong D-L 2003VLSI Symp. Tech. Dig. pp 33–4

[23] Lee J J and Kwong D-L 2005 IEEE Trans. Electron Devices52 507–11

[24] Chiang T-Y, Chao T-S, Wu Y-H and Yang W-L 2008 IEEEElectron Devices 29 1148–51

[25] Hou T-H, Lee C, Narayanan V, Ganguly U and Kan E C 2006IEEE Trans. Electron Devices 53 3095–102

[26] Hou T-H, Lee C, Narayanan V, Ganguly U and Kan E C 2006IEEE Trans. Electron Devices 53 3103–9

[27] Lee C, Kwon J-H, Lee J-S, Kim Y-M, Choi Y, Shin H, Lee Jand Sohn B-H 2007 Appl. Phys. Lett. 91 153506

Lee J-S, Kim Y-M, Kwon J-H, Shin H, Sohn B-H and Lee J2009 Adv. Mater. 21 178–83

[28] Kim Y-M and Lee J-S 2008 Appl. Phys. Lett. 92 102901[29] Sentaurus Device User Guide Synopsis Version Z-2007.03[30] Lue H T et al 2005 IEDM Tech. Dig. pp 547–50[31] Lue H T, Wang S Y, Lai E K, Hsieh K Y, Liu R and Lu C Y

2007 VLSI Symp. Tech. Dig. pp 16–7[32] Lue H T, Wang S Y, Hsiao Y H, Lai E K, Yang L W, Yang T,

Chen K C, Hsieh K Y, Liu R and Lu C Y 2006 IEDM Tech.Dig. pp 495–8

[33] Chen T S, Wu K H, Chung H and Kao C H 2002 IEEEElectron Device Lett. 25 205–7

[34] Ohba R, Sugiyama N, Uchida K, Koga J and Toriumi A 2000IEDM Tech. Dig. pp 313–6

[35] Lee C, Gorur-Seetharam A and Kan E C 2003 IEDM Tech.Dig. pp 557–61

[36] Lee W-H, Clemens J T, Keller R C and Manchanda L 1997VLSI Symp. Tech. Dig. pp 117–8

[37] Tiwari S, Rana F, Chan K, Hanafi H, Chan W and Buchanan D2001 IEDM Tech. Dig. pp 521–4

[38] Lee C, Ganguly U, Narayanan V, Hou T-H, Kim J andKan E C 2005 IEEE Electron Device Lett. 26 879–81

11