design rules as on 05-08

7/27/2019 Design Rules as on 05-08

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DESIGNRULESANDLAYOUT

B.Lokeshwar

Asst professor.

RVR & JC College of Engineering


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DESIGNRULES

Design rules are set of rules that represent the

physical limits of a particular manufacturing

process.

The wafer fabrication vendor defines these rules.

Factors influencing the design rules:

Cost to manufacture

Minimum feature size and processing steps

Maturity of manufacturing tools and process

The layout designer must follow the design rules to

fabricate a microchip.


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DESIGNRULES(CONT..)

Design rules acts as a contract between Designer

and Process Engineer.

Designer wants:

Smaller designs

High circuit density

High performance

Process Engineer wants:

Reproducibility

High-yield process

Design rules are compromise and satisfy both


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DESIGNRULES(CONT..)


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DESIGNRULES(CONT..)

Q: Why we need the design rules

A:Due to the Fabrication Errors like


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DESIGNRULES(CONT..)

So, we need rules to ensure that the inaccuracy in

the fabrication will not result in malfunction IC.

Design rules can be classified into

Minimum feature or width rule

Minimum spacing rule

Minimum surround of overlap rule

Exact rule


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MINIMUMFEATURE/WIDTHRULE

It is defined as the minimum side length of a

polygon or path on the same layer

It defines the limits of manufacturing process

When min.width is violated An open circuit occur due to breaks in the shape


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MINIMUMFEATURE/WIDTHRULE(CONT..)

The following figure shows, if any violation in min.width


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MINIMUMSPACINGRULE

The space rule defines the minimum distance b/w two

shapes on the same layers and also applied to shapes

on different layers.

The space rule prevents an unwanted short b/w two

polygons


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MINIMUMSPACINGRULE(CONT)

Violating spacing rules may results in adjacent

polygons on the same layer touching each other

Due to this short circuit may result

The following figure shown


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MINIMUMOVERLAPRULE

It defines the minimum overlap distance of the larger

polygon over the polygon embedded in the latter

Both the polygons are on different layers

Ex: overlap of polysilicon over the contact

The overlap prevents unwanted shorts or pen ckt

connections due to misalignment b/w the polygons

The variation of the overlap rule is called extension rule

Spacing rule


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MINIMUMOVERLAPRULE(CONT)


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EXACTSIZERULE

The polygon can have only one size

It is usually associated with contact cuts and vias

One and only one size used for these polygons


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GENERAL DESIGN RULES

Q: How to specify the design rules?

A: We can specify the design rules using some

convenient units,

e.g., microns but what happensif we want to manufacture the chip using

different manufacturers?

use an abstract unit, the lambda(), and scale the

design to the appropriate actual dimensions whenthe chip is to be manufactured


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GENERAL DESIGN RULES(CONT)


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TYPESOF DESIGN RULES

There are 2 kind of design rules :

rules (scalable)

Enables technology changes

Enable design reuse

Reduce design cost

Used by some foundry

Micron rules

optimal density of design

used by industry scalable


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LAMBDABASEDDESIGNRULES

Mead and Conway developed a set of simplified

scalable -based design rules, which are valid for a

range of fabrication technologies

In these rules, the minimum feature size of a

technology is characterized as 2 . All width and

spacing rules are specified in terms of the

parameter

One lambda ()= one half of the minimum "mask

dimension, typically the length of a transistorchannel


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LAMBDABASEDDESIGNRULES(CONT..)

Suppose,

we have design rules that call for aminimum width of 2 , and a minimum spacing of 3

If we select a 2 um technology

i.e., = 1 um,

the above rules are translated to

a minimum width of 2 um and

a minimum spacing of 3 um

On the other hand,

If a 1 um technologyi.e., = 0.5 um is selected,

then the same width and spacing rules are nowspecified

as 1 um and 1.5 um, respectively.


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LAMBDABASEDDESIGNRULES(CONT..)

Therefore,

lambda can be used to derive design rules and to

estimate minimum dimensions of a junction area and

Design rules based on single parameter,

Simple for the designer

Wide acceptance

Minimum feature size is defined as 2


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RULESFOR TRANSISTOR

Poly layer should obey the basic 2 rules for widths

and spaces


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RULESFOR TRANSISTOR(CONT..)

DIF layer is having 2 width rule

Poly and Dif layers ,which dont meet intentionally

to form a contact

The source and drain diffusion is masked by thegate oxide remaining under the poly region

The S & D & Channel are thereby self aligned to

the gate

NOTE: Thin oxide mask= union of n-diffusion or p-diffusion

and channel regions


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RULESFOR TRANSISTOR(CONT..)

To form a transistor, Poly must crosses DIF

completely

Thus, a minimum of 2 poly overlap is required

beyond the edges of the DIF region

Similarly, DIF must extend beyond the Poly gate

So that diffused regions definitely exist to carry charge

into and out of the gate region


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The minimum of 2 separation is required from contact cut to

transistor


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NMOSDEPLETIONMODETRANSISTOR


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RULESFORCONTACTCUTS

The only other interaction b/w layers involve

contacts

Contacts are made using a min. of 2 square CUT

When making contacts b/w poly and dif in nMOS

ckts it should be recognized that there are 3

possible approaches

Poly to metal

Diff to metal

Metal2 to metal1 called Via


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RULESFORCONTACTCUTS(CONT..)

Metal1 to poly:

When making connection from metal1 to poly in a circuit

a mini. of 2 square CUT contact

Basically, 2 X 2 contact CUT is extending by 1 in

all directions around the contact area


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Metal1 to Diff:

A mini of 2 square CUT is required to contact from

metal1 to n or p Diffusions

1 of Diff surrounding CUT is the rule to avoid forming

of unwanted transistors.


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Metal2 to metal1:

This type of connection is called Via

Here, contact CUT is followed the rule as 2 X 2

Contact b/w poly to Diff are made via metal


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DRAWINGLAYOUT

The simplest way to begin a layout representation

is to draw the stick diagram

In layout designs, we need to take care about the

physical interconnection of different layers

By simply drawing one layer above the other it not

possible to make interconnections, because of the

different characteristics of each layer

Contacts have to be made whenever such

interconnection is required.


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DRAWINGLAYOUT

The power and the ground connections are made

using the metal

and the common gate connection using the

polysilicon

The metal and the diffusion layers are connected

using contacts

These layouts are governed by DRC's and have to

be atleast of the minimum size depending on the

technology used


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NMOSDEPLETIONLOADINVERTER

Vout

Vdd = 5V

Vin

* Note the depletion mode device

Vin

Vout


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NMOSDEPLETIONLOADINVERTER(CONT..)

Layout:


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CMOS INVERTER

Vout

Vdd = 5V

Vin


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CMOS INVERTER(CONT..)


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DESIGNRULES(CONT..)

CMOS circuits are formed from a number of

different layers, which are isolated from each other

by silicon dioxide insulating layers. Each layer has

a different function in an integrated circuit

design rules as on 05-08

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