designing a programmable analog signal conditioning circuit without loss of measurement range

1482 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

Designing a Programmable Analog SignalConditioning Circuit Without Loss

of Measurement RangeSebastian Yuri Cavalcanti Catunda, Jean-François Naviner, Gurdip Singh Deep, and Raimundo Carlos Silvério Freire

Abstract—Programmable analog signal conditioning circuitscan be programmed in the field to permit their use in severalapplications with a variety of sensors with different output signalcharacteristics. The digital programming of the gain and dclevel shift of a conditioning circuit can affect the measurementresolution and cause a reduction in the range of the measuringsystem in which it is employed. For a specified maximum accept-able loss in the measurement resolution, a procedure for definingand employing the programming values that guarantees the fullmeasurement range is proposed. The proposed methodology takesinto account practical implementation considerations and can beemployed for designing either discrete or integrated circuits.

Index Terms—Analog circuits, gain programming, measurementsystem, programmable circuits, signal conditioning.

NOMENCLATURE

Upper limit values.Lower limit values.Ideal values.Signal range or span.Rounding to the nearest smaller integer.One, if it is true and zero otherwise.

I. INTRODUCTION

A PROGRAMMABLE analog signal conditioning circuitsuitable for measurement applications can be pro-

grammed to match the design specifications of a measurementsystem and adapt it to be used with a class of sensors withdifferent output signal characteristics. This circuit must thusprovide functions for signal amplification and dc level shift forthe cases of single-ended signals (other functions, as filtering,and linearization are usually also required). The conditionedsignal can be converted to a digital form by means of ananalog-to-digital converter (ADC), for which the resolutionand input signal span are specifieda priori.

Manuscript received May 26, 2002; revised May 12, 2003. This work wassupported in part by the CNPq, in part by Pronex, in part by CAPES-COFECUB,and in part by PROCAD.

S. Y. C. Catunda is with the Universidade Federal do Maranhão, São Luís,Brazil (e-mail: [email protected]).

J.-F. Naviner is with the Ecole Nationale Supérieure des Télécommunica-tions, Paris, France (e-mail: [email protected]).

G. S. Deep and R. C. S. Freire are with the Universidade Federal deCampina Grande, Campina Grande, Brazil (e-mail: [email protected];[email protected]).

Digital Object Identifier 10.1109/TIM.2003.818556

The functions of amplification and dc level shift can beperformed in programmable gain amplifiers [1]–[3], and thereare also some commercial programmable analog or mixedintegrated circuits available today that can be used for thispurpose [4]–[6]. However, in these works and products, theprogramming values are defined empirically without consid-ering their effect in the final measurement quality.

Due to the inherent nature of discrete programming, not allvalues for the gain and dc level shift can be obtained over a spe-cific range. Values of the dc level shift different from the idealones might cause the conditioning circuit signal to saturate (atamplifier’s or ADCs output signal limits) leading to a reductionof the effective measurement range. Also, gain values smallerthan the ideal ones cause the conditioned signal to lie over afraction of the specified ADC input range, amounting to a lossin the measurement resolution.

For several practical applications, it is more crucial to en-sure the full measurement range than to put up with some lossin the measurement resolution. The loss in measurement rangecannot be recovered, while the loss in measurement resolutioncan be compensated by specifying an ADC with higher reso-lution during the design phase. For a specified admissible lossin the measurement resolution, a procedure for defining andemploying the gain and dc level shift programming values ispresently proposed. This procedure guarantees the full measure-ment range and still yields the smallest size of the set of admis-sible discrete programming values taking into account the prac-tical implementation constraints.

The procedures for defining the programming sets for the caseof a single-stage signal conditioning circuit are developed inSection III. The procedures for a multistage pipelined case aredeveloped in Section IV based on the results obtained for thesingle-stage case. In Section V, we extend these results for thecases of fully differential signals.

II. PRELIMINARY DEFINITIONS

Fig. 1 shows a single-stage conditioning circuit block dia-gram. The main role of the signal conditioning circuit is to adjustthe sensor’s output signal span to match the ADC input range.The sensor’s output signal is first dc level shifted byand then amplified with a gain . In the absence of an adequatesignal conditioning, the conditioned signal may exceed theADC input range causing saturation at its output. This effect isrepresented by the saturation block in Fig. 1. The ADC input

0018-9456/03$17.00 © 2003 IEEE

CATUNDA et al.: DESIGNING A PROGRAMMABLE ANALOG SIGNAL CONDITIONING CIRCUIT 1483

Fig. 1. Single-stage conditioning circuit model.

signal range is defined in terms of its upper and lower limitsas . Likewise, the range and the upper andlower limits for the input signal and for the actual conditionedsignal are related as and ,respectively.

Normally, the sensor output signal range (input to the condi-tioning circuit) does not correspond to the ADC input span. Theupper and lower limits of the input signal can be expressed re-spectively as

and (1)

where represents input signal without dc level, and rep-resents the input signal dc level that must be ideally compen-sated.

The values of gain and dc level shift must be chosen for eachspecific sensor employed, even though these can assume onlysome discrete values. Consequently, the errors in programmingthe gain and dc level shift are defined respectively as

(2)

and

(3)

where and are the actual (available) and the ideal gain re-spectively and is termed as the gain error. is the dc levelshift provided by the conditioning circuit and is the errorin the dc level shift (dc level residue).

A. Conditioned Signal

The conditioned signal without the effect of saturation can be

calculated as . In this way, with ,the conditioned signal upper and lower limits can be expressedin terms of the gain error and dc level residue, from (1), (2), and(3), respectively as

(4)

and

(5)

The conditioned signal span, as defined before, may be writtenas

(6)

B. Loss in Measurement Resolution

The measurement resolution is affected by a mismatched pro-grammed gain, which makes the conditioned signal span to bedifferent from the ADC input signal span. The loss of resolutionis defined as and it can be expressed (in number of bits) ei-ther in terms of the relative gain error or in terms of the idealand actual gain values [7], respectively, as

(7)

The loss of measurement resolution caused by the conditioningcircuit is in addition to the loss due to the ADC nonidealities andboth should be considered in determining the total measurementresolution loss.

C. Requirements to Ensure the Complete Measurement Range

To eliminate loss in the measurement range there should beno saturation in the ADC output. Thus, for the upper limit ofthe conditioned signal value at the ADC input, we must have

and from (4) we have

(8)

(9)

where always assumes negative values.Similarly, for the lower limit value of the conditioned signal,

we must have and from (5) we have

(10)

Considering the equal to zero, we have

(11)

Thus, from (9) and (11), we can observe that the dc level shiftmust be equal to or greater than zero. Therefore, as the ac-tual gain is always positive, (11) always holds true. If we forcethe gain error (by choosing an under-dimensioned gain) highenough to guarantee (9) we will also guarantee no loss in themeasurement range. Thus, the requirements to eliminate loss inthe measurement range are as follows.

• The dc level shift must not be over-dimensioned.• The relative gain error must be high enough to assure (9),

making the gain under-dimensioned.

III. SINGLE-STAGE CONDITIONING CASE

The loss in the measurement range can be caused by an in-correct dc level adjustment and/or by employing an over-dimen-sioned gain, which causes part of the conditioned signal spanto lie outside the specified ADC input limits. Further, if we al-ways employ an under-dimensioned gain, we can cancel the lossof measurement range due to the ill chosen adjustment in thedc level. Although, this restriction on the gain introduces some


extra loss in measurement range and influences the choice of theset of dc level shift programming.

A. Gain Programming Set

We define the maximum and minimum ideal gains, accordingto the output signal characteristics of a chosen group of sensors,

as and . The complete gain programming set con-sists of values and it is denoted as ,

with and . In addition, we mustdefine the maximum acceptable loss in the measurement rangeas .

As stated in the previous section, the gain must be alwaysunder-dimensioned to ensure the full measurement range. Thekey idea in the programming strategy is to choose, from theprogramming set, the next value smaller than that equal to orsmaller than the ideal required gain. Thus, the gain to be em-ployed from the set is (as function of the programmingindex ), with given by

otherwise(12)

where is a gain value, not included in the set, used fordefining when the last gain value is to be employed. The valueof is determined later on.

For this strategy, the maximum relative gain error is givenby the ratio of the gain values separated by two gain steps, andthe minimal relative gain error is given by the ratio of the gainvalues separated by one gain step. From (7) and consideringthe maximum admissible loss of resolution, we can define themaximum ratio of the gain values separated by two steps of gainas and, for , we can write

(13)

In order to determine the relationship between two consecutivegain values we can decompose the ratiointo two fractionsand , so that . In this way, we can define relationshipbetween the gains with even and odd index as

(14)

and

(15)

This choice of gain values defines the limits of the relative gainerror as

(16)

The minimum gain programming set, as function ofand , canbe written as

(17)

where , which makes the relative gainerror different from zero for the first programming value, and

is equal to one if is even and zero other-

wise. For example, for , the complete set is given by.

The gain values that compose the set define a series and canbe calculated (for ) as .The value of is given by the next value of the series afterthe last gain value in the set, so .The number of the elements in the gain programming set canbe determined by completing the series until finding the max-imum gain value that is equal to or smaller than the maximum

ideal gain, or . Alter-natively, the number of programming values can be determinedas

(18)

The best relationship among the gain ratios is , be-cause these define a constant minimum relative gain error overthe full programming range. However, the values ofand canbe chosen for defining gain values which are easy to implementin practice, as it is shown in the application example.

B. DC Level Shift Programming Set

Considering the signal to be single-ended we define themaximum and minimum dc level adjustment, according tothe sensor output signal characteristics of a given group ofsensors, as and . The complete dc level shiftprogramming set consists of values and it is denoted as

. As the required gain and dc levelshift are independent, the best choice for the dc level shiftprogramming set is the one that consists of equally spacedvalues. Thus, the dc level shift programming values can becalculated, for , as

(19)

The dc level shift employed (as function of the pro-gramming index ) must be smaller than or equal to the de-sired value, so . Theworst-case dc level residue can be calculated as

(20)

The value of depends on the maximum value of the actualgain and on the minimum loss in the measurement resolution.The minimum loss of measurement resolution is attained for thesmaller of the and values. From (9), (16) and consideringthe worst-case dc residue and the maximum programming gainvalue, we have

(21)

The number of programming values is then

(22)


Fig. 2. Several pipelined stages of gain and dc level shift.

The required number of bits for programming the dc level shiftvalues is given by the base two logarithm of .

IV. M ULTISTAGE CONDITIONING CASE

For large values of the actual gain and large number of dclevel shift programming values, , the conditioning circuit toimplement the gain and dc level shift can become quite com-plex and expensive. Although, it is possible to split the condi-tioning circuit in several stages (as shown in Fig. 2), and this hasthe advantage of reducing the ratio between the largest and thesmallest programming element values for the circuit and maylower the gain bandwidth product specifications of the opera-tional amplifiers to be used. In Fig. 2, for the sake of generalityevery gain stage is considered to have its own output saturationlimits.

A. Multistage Gain Programming Sets

The complete gain set given by (17) can be easily divided insmaller sets. One of the sets must contain part of the series

defined by the one-stage case, starting with the minimum gain.The other sets can have just two values of gain, which are used toobtain the desired total gain. The conditioning stage employingmore than two gain values is more complex than the others andis more susceptible to noise. Thus, this stage is chosen to be thelast one, which minimizes the effect of the noise introduced intothe system. The complete gain sets are

...

(23)

where are integers and is the number ofgain values for the last set.

For these sets, we must ensure that , i.e.,the product of the gains employed in each stage, which gives thetotal gain, must provide at least the gain set defined by (17).

The amplifiers in the conditioning stages except the last onecan be set to use a single gain value greater than one, for thesecan be simply bypassed, shorting the signal path, to employ again equal to one. The gain programming strategy is the sameas for the single stage in such a way that it must provide thesame necessary minimum and maximum relative gain errors toensure the full measurement range.

B. Multistage dc Level Shift Programming Sets

For conditioning signal stages there must bedc levelshift programming sets,

. The programming values for each stage are chosensimilarly as for a single conditioning stage, and the problemconsists in determining the number of programming values foreach stage. The first stage must compensate the sensor outputsignal dc level and the following stages should compensate thedc level residue from its preceding stage multiplied by the as-sociated gain. The output signal at theth conditioning signalstage, without saturation, may be written as

(24)

with

(25)

(26)

(27)

and with and .In order to determine the number of dc level shift program-

ming values necessary for each stage, an analysis of the outputsignal at each stage is carried out, from the last to the first one.As the dc adjustment is considered always under-dimensioned,there exists no saturation at the lower saturation limit of anystage. The output signal upper limit in the last stage can be ex-pressed as

(28)

for which one must guarantee . Following this pro-cedure for the th signal conditioning stage, other than the laststage, the upper limit on the conditioned signal can be expressedas

(29)

for which we must ensure . Thus, as the worst-case,the highest value of the right side of (29) occurs for theth stagemaximum gain and for the gains equal to one in the followingstages. This makes (29) similar to (28) with the difference thatthe dc level may not be equal to zero for the first stage. There-fore, considering no saturation in the previous stages and fol-lowing a similar procedure to achieve (9) and, later on (22), ageneralized expression can be written as

(30)

with for .


Finally, the maximum dc level at each stage input ,can be calculated as

(31)

V. FULLY -DIFFERENTIAL CASE

When the target application happens to use only differen-tial signals (as with fully-differential amplifiers) or single-endedsignals without dc level, there is no need to employ dc levelshift and the design of the conditioning circuit can be simplified.The programming strategy can be defined to use the first avail-able gain in the set that is smaller than or equal to the desiredideal gain. The complete gain set may consist of gain valuesof even index of the gain set defined in (17) and is defined as

, with . The number

of programming gain values is given bywhich yields a set with approximately half the size of the set de-fined earlier in Section III. Likewise, the programming set canalso be easily divided in several smaller sets for employing amultistage conditioning.

VI. A PPLICATION EXAMPLES

As a design example, we consider a measurement system withan ADC input and amplifiers’ output saturation limits equal to[0, 2 V], which may be obtained in circuits biased with 3.3 V,and the maximum acceptable loss of resolution equal to 1 bit.The necessary gain and dc level shift limits are [1, 256] and [0,1 V], respectively.

A. Single-Stage Design

For a single stage design, we have: V,

bit, V, . For themaximum acceptable loss of resolution we have and wechose and , which yields passive componentsof easy practical implementation. Directly from (18) we have

, which requires 4 bits for programming the gain. From(22) we have , which requires 8 bits for programmingthe dc level shift and from (20) we have the maximum dc levelresidue mV. From (17), the complete gain set is

(32)

Fig. 3 shows the upper and lower limits of the relative gain errorgiven by (16), the minimum value of the relative gain error nec-essary to ensure the full measurement range calculated from (9),and the actual relative gain error, which happens to be the samefor the single-stage and two-stage designs.

B. Two-Stage Design

For a two-stage pipelined conditioning design, consideringthe same saturation limit for both stages, the gain set found in(32) can be divided into two gains sets as

Fig. 3. Actual relative gain error and limits.

Fig. 4. Ideal and actual gain values.

The number of programming values for the first stage, from (30)is , requiring 4 bits for programming each one. From(31), the maximum value of the dc level at the second stage inputis 0.5 V and for this value we have . The ideal gainand actual gain are shown (for both single-stage and two-stagedesigns) in Fig. 4, as function of the ideal gain, making evidentthe proposed strategy for selecting the appropriate gain values.

From the presented example, it can be seen that for a largerange of the desired gain it is more interesting to divide the con-ditioning circuit into several stages. For the single-stage design,the maximum gain value employed and the maximum ratio be-tween gain values are 128 and 170.7, respectively, and for thetwo-stage design, they are both equal to 16 (for the last stage).Thus, for the two-stage design (as compared to the single-stagedesign) the maximum ratio between passive components is re-duced by a factor of 10.7. The gain bandwidth product spec-ification for the second-stage amplifier is lowered by a factorof approximately five (considering the effect of cascading two


amplifiers in the total gain bandwidth product). Likewise, thenumber of bits for programming the dc level shift is reducedfrom eight to four bits.

VII. CONCLUSION

A new methodology is proposed to define and select the ap-propriate programming values for the gain and dc level shift forone or several pipelined signal conditioning stages, which as-sures no loss in the measurement range. This procedure is il-lustrated by an example, where it can be seen that it is moreadvantageous to divide the conditioning into several pipelinedstages, for a wide range of gains and dc level shifts. Dividingthe signal conditioning circuit into several stages may also havethe advantage of lowering the required specifications of the op-erational amplifiers in respect of the gain bandwidth product.

The proposed procedure can therefore be employed for a dis-crete component signal conditioning circuit as well as for anintegrated one, independent of the circuit technique to be used.Nevertheless, the methods and analysis were carried out at thefunctional level, and an analysis of the practical limitations andimperfections of the analog circuits must be carried out, whichmay result in a trade-off between the number of stages and thesignal conditioning accuracy.

REFERENCES

[1] W. Q. Yang, “Combination of ADC and DAC to measure small variationwith large standing signal,” in3rd Int. Conf. Advanced A/D and D/AConversion Techniques and Their Applications, Manchester, U.K., 1999.

[2] P. Malcovati and F. Maloberti, “A fully integrated CMOS magnetic cur-rent monitor,” inProc. IEEE Int. Symp. Circuits and Systems, Pavia,Italy, 1999.

[3] M. E. Gruchalla, J. O’Hara, D. Barr, T. Cote, L. Day, D. Gilpatrick,M. Stettler, and D. Martinez, “Beam profile wire-scanner/halo-scrapersensor analog interface electronics,” inProc. Particle Accelerator Conf.,Albuquerque, NM, 2001.

[4] FIPSOC—Field Programmable System on Chip, 2001. SIDSA.[5] ispPAC10—In-System Programmable Analog Circuit Datasheet, 2001.

Lattice.[6] Cypress Microsystems 2002, 2002. PsoC MCU devices.[7] S. Y. C. Catunda, J.-F. Naviner, G. S. Deep, and R. C. S. Freire, “Mea-

surement system gain and DC level shift programming,” inIEEE Instru-mentation and Measurement Technology Conf., Baltimore, MD, 2000.presented.

Sebastian Yuri Cavalcanti Catunda was born in1971 in João Pessoa, Brazil. He received the B.S.and M.S. degrees in electrical engineering from theFederal University of Paraíba (UFPB), CampinaGrande, Brazil, in 1993 and 1996, respectively, andthe Ph.D. degree in electrical engineering from ajoint doctoral program at UFPB and Ecole NationaleSupérieure des Télécommunications (ENST), Paris,France, in 2000.

Since June 1997, he has been an Assistant Pro-fessor with the Department of Electrical Engineering,

Federal University of Maranhão, São Luís, Brazil. His research interests includeelectronic instrumentation and sensors, control systems, and mixed-signal mi-croelectronic circuits.

Jean-François Naviner received the engineeringdegree in telecommunications and the Ph.D. degreefrom the Ecole Nationale Supérieure des Télécom-munications (ENST), Paris, France, in 1987 and1992, respectively.

From 1988 to 1992, he was a Research Engineerwith ARECOM, Paris, where he was involvedin CAD tools design for digital layout synthesisand VLSI circuit design for image processing. In1992, he joined the analog electronics group ofthe ENST Electronics Department. From 1995 to

1997, he spent a two years sabbatical at the Federal University of Paraíba,Campina Grande, Brazil, as Visiting Professor successively with the ElectricalEngineering Department and then the Computer Science Department. He iscurrently head of the Analog and Mixed Integrated Systems group of the ENSTElectronics and Communications Department. His research interests includearchitecture and design of mixed-signal ICs in CMOS technology, data con-verters, CAD techniques for mixed-signal design, and analog and mixed-signalreconfigurable circuits for telecommunications and instrumentation. Hiscurrent projects include parallel analog-to-digital converter architecture, analogfront-end architecture and design for multimode-multistandard receivers,telecommunications data converters synthesis, and reconfigurable sensorinterface for instrumentation.

Gurdip Singh Deep received the B.Tech.(Hons.)degree in electrical engineering from the IndianInstitute of Technology (IIT), Kharagpur, in 1959,the M.E. degree in power engineering (electrical)from the Indian Institute of Science, Bangalore, in1961, and the Ph.D. degree in electrical engineeringfrom the IIT, Kanpur, in 1971.

From 1961 to 1965, he was an Assistant Professorat Guru Nanak Engineering College, Ludhiana, India,and from 1965 to 1972, he was with IIT, Kanpur,as a Lecturer/Assistant Professor. From July 1972 to

April 2002, he was a Titular Professor with the Center of Science and Tech-nology, Federal University of Campina Grande, Campina Grande, Brazil. Hisresearch interests are electronic instrumentation, sensors, and transducers.

Raimundo Carlos Silvério Freire was born on Oc-tober 10, 1955, in Poço de Pedra, Brazil. He receivedthe B.S. degree in electrical engineering from theFederal University of Maranhão, Maranhão, Brazil,in 1980, the M.S. degree in electrical engineeringfrom the Federal University of Paraíba, CampinaGrande, Brazil, in 1982, and the Ph.D. degree inelectronics, automation, and measurements from theNational Polytechnical Institute of Lorraine, Nancy,France, in 1988.

He was an Electrical Engineer for Maranhão Edu-cational Television from 1980 to 1983. He was a Professor of electrical engi-neering at the Federal University of Maranhão from 1982 to 1985. Since De-cember 1989, he has been with the Electrical Engineering Department, FederalUniversity of Campina Grande. His research interests include electronic instru-mentation and sensors and microcomputer-based process control.

designing a programmable analog signal conditioning circuit without loss of measurement range

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