designing of efficient fpga based random number generators using vhdl

International Journal of Advance Foundation and Research in Computer (IJAFRC)

Volume 2, Issue 8, August - 2015. ISSN 2348 4853, Impact Factor 1.317

63 | 2015, IJAFRC All Rights Reserved www.ijafrc.org

Designing Of Efficient FPGA Based Random Number Generators

Using VHDL. Mr. P.A.Deshmukh Prof. D. R. Dandekar Prof. Mrs. Y. A. Sadawarte

P.G.Student Associate Professor Assistant professor

B.D.C.O.E,SEVAGRAM,WARDHA B.D.C.O.E,SEVAGRAM,WARDHA

B.D.C.O.E,SEVAGRAM,WARDHA

[email protected] , [email protected], [email protected].

ABSTRACT

Random Number Generator is an electronic circuit or it can be software or can be optimized

architecture. In many practical applications such as cryptography, model simulation, sampling,

games of chance, numerical analysis, there is a need of the generation of series of random

number. This is achieved for ex. by means of tables, specific algorithms or electronic circuits. This

Random number can be generated by either specific software or a FPGA based architectures. Field

Programmable Gate Array (FPGA) optimized random number generator (RNG) are more resource

efficient than software optimized RNG because they can take the advantage of bitwise operations

and FPGA specific features. Hence for generation of random number, FPGA architecture is

generally used. By using different FPGA platform, random number can be generated. There are

several algorithms by which the random number has been generated. Each algorithm had used a

different FPGA platform for generation of random number. In this paper generation of 8, 16, 256

bit random number by means of four method i.e. EX-OR Shift method, Fibonacci series method,

Galois liner feedback shift register method and Blum Blum Shub method. Moreover for analysis

Altera platform is used i.e. for simulation Modelsim software and for synthesis Quartus II

software is used. Hence by using these four algorithms, random numbers have been generated

and each algorithm has shown different performance parameters i.e. area, speed and power.

Index TermsRandom number generator RNG, Field programmable gate array FPGA, Linear

Feedback Shift Register LFSR,

I. INTRODUCTION

Random Number Generator is an electronic circuit or it can be software or can be optimized architecture.

In many practical applications such as cryptography, model simulation, sampling, games of chance,

numerical analysis, there is a need of the generation of series of random number. This is achieved for ex.

by means of tables, specific Algorithm or electronic circuits. Moreover there are again some FPGA

architecture by which we can generate the series of random number. Each algorithm uses a different

FPGA platform and the random number can be generated. FPGA optimized RNG are more resource

efficient than Software optimized RNG because they can take Advantages of bitwise operation and FPGA

specific features These FPGA architectures shows huge performance in terms of area and speed. In this

paper the 8 bit random number is generated by two methods i.e. Fibonacci series method and Galois liner

feedback shift register method..

II. INTRODUCTION ABOUT LINEAR FEEDBACK SHIFT REGISTER




In computing, a linear feedback shift register (LFSR) is a shift register whose input bit is a linear function

of its previous state. The most commonly used linear function of single bits is XOR. The initial value of the

LFSR is called the seed, and because the operation of the register is deterministic, the stream of values

produced by the register is completely determined by its current (or previous) state. Likewise, because

the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an

LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and

which has a very long cycle Applications of LFSRs include generating pseudo-random numbers, pseudo-

noise sequences, fast digital counters and whitening sequences

Figure 1. Block Diagram of Basic Linear Feedback Shift Register

III. PSEUDO-RANDOM NUMBER GENERATOR BASED ON FIBONACCI SERIES METHOD

The Bit positions that affect the next state are called the taps. In the diagram the taps are [7, 6, 4, 3] .The

rightmost bit of the LFSR is called the output bit. The taps are XOR'd sequentially with the output bit and

then fed back into the leftmost bit. The sequence of bits in the rightmost position is called the output

stream.

A maximum length LFSR produces an m-sequence i.e. it cycles through all possible 2n - 1 state. The

sequence of numbers generated by an LFSR can be considered a binary numeral system just as valid as

Gray code or the natural binary code. The arrangement of taps for feedback in an LFSR can be expressed

in finite field arithmetic as a polynomial mod

Figure 2. Block Diagram of Fibonacci Series Method

This means that the coefficients of the polynomial must be 1's or 0's. This is called the feedback

polynomial or reciprocal characteristic polynomial. For example, if the taps are at the 7th, 6th, 4th and

3th bits (as shown), the feedback polynomial is X7+ x6 + x4 + x3 +1. The 'one' in the polynomial does not

correspond to a tap it corresponds to the input to the first bit (i.e. x0, which is equivalent to 1).




The powers of the terms represent the tapped bits, counting from the left. The first and last bits are

always connected as an input and output tap respectively.

i.The LFSR is maximal-length if and only if the corresponding feedback polynomial is primitive. This

means that the following conditions are necessary (but not sufficient):

ii.The number of taps should be even.

iii.The set of taps taken all together, not pair wise (i.e. as pairs of elements) must be relatively

prime. In other words, there must be no divisor other than 1 common to all taps.

IV.PSEUDO-RANDOM NUMBER GENERATOR BASED ON GALOIS LFSR METHOD

In the Galois configuration, when the system is clocked, bits that are not taps are shifted one position to

the right unchanged. The taps, on the other hand, are XOR'd with the output bit before they are stored in

the next position. The new output bit is the next input bit.

The effect of this is that when the output bit is zero all the bits in the register shift to the right unchanged,

and the input bit becomes zero.

Figure 3 Block Diagram of Galois LFSR Method

When the output bit is one, the bits in the tap positions all flip (if they are 0, they become 1, and if they

are 1, they become 0), and then the entire register is shifted to the right and the input bit becomes 1.

Galois LFSRs do not concatenate every tap to produce the new input (the XOR'ing is done within the LFSR

and no XOR gates are run in serial, therefore the propagation times are reduced to that of one XOR rather

than a whole chain), thus it is possible for each tap to be computed in parallel, increasing the speed of

execution.

In a software implementation of an LFSR, the Galois form is more efficient as the XOR operations can be

implemented a word at a time: only the output bit must be examined individually.

V.PSEUDO-RANDOM NUMBER GENERATOR BASED ON EX-OR SHIFT METHOD

In computing, a linear feedback shift register (LFSR) is a shift register whose input bit is a linear function

of its previous state. The most commonly used linear function of single bits is XOR.

Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some

bits of the overall shift register value. The Bit positions that affect the next state are called the taps. In the

diagram, the taps is only at [7]. The rightmost bit of the LFSR is called the output bit.




The taps are XOR'd sequentially with the output bit and then fed back into the leftmost bit. The sequence

of bits in the rightmost position is called the output stream.

Figure 4. Block Diagram of EX-OR SHIFT Method

The sequence of numbers generated by an LFSR can be considered a binary numeral system just as valid

as Gray code or the natural binary code. The arrangement of taps for feedback in an LFSR can be

expressed in finite field arithmetic as a polynomial. This means that the coefficients of the polynomial

must be 1's or 0's. This is called the feedback polynomial or reciprocal characteristic polynomial

For example, if the taps are at the 7th (as shown),the feedback polynomial is X7+1. The 'one' in the

polynomial does not correspond to a tap it corresponds to the input to the first bit (i.e. x0, which is

equivalent to 1).

VI.PSEUDO-RANDOM NUMBER GENERATOR BASED ON BLUM BLUM SHUB METHOD

Blum Blum Shub (B.B.S.) is a pseudorandom number generator proposed in 1986 by Lenore Blum,

Manuel Blum and Michael Shub that is derived from Michael O. Rabin's oblivious transfer mapping. Blum

Blum Shub takes the form Xn+1`= Xn2 Mod M

where M = pq is the product of two large primes p and q. At each step of the of the algorithm, some

output is derived from Xn+1, the output is commonly either the bit parity of Xn+1 or one or more of the

least significant bits of Xn+1.

Figure 5. Block Diagram of BLUM BLUM SHUB Method

The main property of the BBS generator is that it is proven to be next-bit unpredictable to the left and to

the right, if the prime factors of a large integer N are unknown. Consequently, the security of the

generator is based on the intractability of factoring large integers, which is also used in the encryption

scheme. Next bit unpredictability to the right (to the left) means that for every positive polynomial p and

for sufficiently large m the following condition holds The seed x0 should be an integer that is co-prime to

M (i.e. p and q are not factors of x0) and not 1 or 0. If m-1 consecutive output bits are known, then for




every polynomial-time algorithm, it is impossible to guess the next output bit with a probability larger

than 1.

The BBS generator is quite slow, but due to the characteristic explained above, it is recommended for

cryptographic tasks which only need a small amount of random numbers

VII.APPLICATION OF RANDOM NUMBER GENERATOR AS SCRAMBLER AND DESCRAMBER

A scrambler is a device which transposes signals or encodes a message at the transmitter to make the

message unintelligible at a receiver. Scrambling is accomplished by the addition of components to the

original signal or the changing of some important components of the original signal in order to make

extraction of the original signal difficult

Figure 6. Block Diagram of SCRAMBLER and DESCRAMBLER

In the transmitter, a pseudorandom cipher sequence is added (modulo 2) to the data (or control)

sequence to produce a scrambled data (or control) sequence. In the receiver, the same pseudorandom

cipher sequence is subtracted (modulo 2) from the scrambled data (or control) sequence to recover the

transmitted data (or control) sequence. A receiver descrambles the received data or control sequence by

subtracting the same pseudorandom cipher sequence used for scrambling.

Since the subtraction is modulo 2, this is equivalent to adding the pseudorandom cipher sequence i.e. the

procedure is identical to that used for scrambling in the transmitter. The receiver must ensure that the

state of the descrambler register is synchronized with that of the scrambler register.

In the above application i.e. Scrambler and Descrambler, whatever random number have input as a plain

text in the scrambler, the same plain text in the form of random sequence is getting at the receiver I.e.

descrambler. Hence functionality of scrambler and descrambler is verified.

VIII. RESULT ANALYSIS

For simulation and synthesis of the algorithm Altera platform is used, Modelsim software is used for

simulation of the four methods and for synthesis, Quartus II software is used. In that Quartus II 9.1 build

350 03/24 /2010 SP 2 SJ web edition version is used. Moreover the family is cyclone II and the device is

EP2C20F484C7 is used.




0

5

10

15

20

25

30

EX-OR Shift

Method

Fibonacci

Series

Galois

Method

Blum Blum

Shub

Device Utilization Summary

Power Dissipation

Propagation Delay

Graph 1. Graphical Representations of Different Architectures for 8 Bit

In Graph 1, the comparison for 8 bit for different architectures has been shown. In that as per

comparison, Galois LFSR architecture has less device utilization summary, less power dissipation and less

propagation delay. Hence Galois Architecture is found efficient for 8 bit random number generation.

In Graph 2, The comparison for 16 bit for different architectures has been shown. In that as per

comparison, Galois LFSR architecture have less device utilization summary, less power dissipation and

less propagation delay. Hence Galois LFSR Architecture is found efficient for 16 bit random number

generation.

0

10

20

30

40

50

60

EX-OR Shift

Method

Fibonacci Series

Method

Galois Method Blum Blum

Shub Method

Device Utilization Summary

Power Dissipation

Propagation Delay


In Graph 3, the comparison for 256 bit for different architectures has been shown. Thus for synthesizing

for 256 bit, each architecture showing different device utilization summary, propagation delay and power

dissipation.




0

50

100

150

200

250

300

EX-OR Shift Fibonacci Series Galois Method

Device

Utilization

Summary

Power

Dissipation

Propagation

Delay


IX. CONCLUSION

In this paper, After simulation and synthesis of four architectures for device utilization summary,

propagation delay and power dissipation, as per synthesis result, it is found that Galois LFSR is power

efficient and time efficient when applied for a particular application i.e. Scrambler and Descrambler for

different bit i.e. 8 bit, 16 bit and 256 bit. Thus Galois LFSR is efficient for Random number generation as

per above results.

X. REFERENCES

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[2] Carols Gayoso, C.gonzalez in 2013 on Pseudorandom Number Generator Based on the Residue

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Distributions Via the Inversion Method




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designing of efficient fpga based random number generators using vhdl

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