development of the depfet sensor with signal … · 1 ais seminar slac, 26.10.12 development of the...
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AIS Seminar SLAC, 26.10.12
Development of the DEPFET Sensor with Signal Compression: a Large Format X-ray Imager with Mega-Frame Readout Capability for the
European XFEL
SLAC, 26.10.2012
Matteo Porro on behalf of the DSSC Consortium
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AIS Seminar SLAC, 26.10.12
M. Porro1,2, L. Andricek2,3, S. Aschauer8, L. Bombelli4,5, A. Castoldi4,5, G. De Vita1,2, I. Diehl7, F. Erdinger6, S. Facchinetti4,5, C. Fiorini4,5, P. Fischer6, T. Gerlach6, H. Graafsma7, C. Guazzoni4,5, K. Hansen7, H. Hirsemann7, P. Kalavakuru7, A. Kugel6, P. Lechner8, G. Lutz8, M. Manghisoni10, D. Mezza4,5, D. Moch1,2, U. Pietsch9, E. Quartieri10, V. Re10, C. Reckleben7, C. Sandow8, S. Schlee1,2, J. Soldat6, L. Strueder1,2, A. Wassatsch2,3, G. Weidenspointner1,2, C. Wunderer7
1) Max Planck Institut fuer Extraterrestrische Physik, Garching, Germany 2) MPI Halbleiterlabor, Muenchen, Germany 3) Max Planck Institut fuer Physik, Muenchen, Germany 4) Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy 5) Sezione di Milano, Italian National Institute of Nuclear Physics (INFN), Milano, Italy 6) Zentrales Institut für Technische Informatik, Universitaet Heidelberg, Heidelberg, Germany 7) Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany 8) PNSensor GmbH, Muenchen, Germany 9) Fachbereich Physik, Universitaet Siegen, Siegen, Germany
10) Dipartimento di ingegneria industriale, Università di Bergamo, Bergamo, Italy
DSSC Consortium
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Introduction
DSSC Concept overview
• Requirements and Design Parameters • Focal Plane overview • Non-linear DEPFET working principle • Non-linear system properties • Readout ASIC
Main Achievements
System simulation
Conclusions
Outline
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Up to ~2700 bunches in 600 µs, repeated 10 times per second producing 100 fs X-ray pulses (~27 000 pulses/second).
max bunch rate: 4.5 MHz
We want to readout 1024 x 1024 pixel
frames every 220 ns
Bunch structure of the European XFEL
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2D detectors for EuXFEL
Three Detector Developments at the European XFEL (coordinator: M. Kuster)
Adaptive Gain Pixel integrating Pixel Detector Consortium (AGIPD) (Project Leader: H. Graafsma) o DESY o PSI / SLS Villingen o Universität Hamburg o Universität Bonn
Large Pixel Detector Consortium (LPD) (Project Leader: M. French)
o Rutherford Appleton Laboratory / STFC o University of Glasgow
DEPFET Sensor with Signal Compression Consortium (DSSC) (Project Leader: M. Porro)
o Max Planck Halbleiterlabor Munich o DESY o Universität Heidelberg o Politecnico di Milano / INFN o Università di Bergamo o Universität Siegen
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DSSC – Design Parameters
Parameter
Energy range op+mized for 0.5 … 6 keV
Number of pixels 1024 x 1024 Sensor Pixel Shape Hexagonal Sensor Pixel pitch ~ 204 x 236 µm2
Dynamic range / pixel / pulse
~5000 ph @ 0.5 keV > 10000 ph @ E≥1 keV
Resolu+on Single photon detec+on also @ 0.5 keV
Frame rate 0.9-‐4.5 MHz Stored frames per Macro bunch ≥ 640
Opera+ng temperature
-‐20˚C op+mum, RT possible
1 Mpixel camera with:
• Single photon sensitivity event at 0.5 keV
• high-dynamic range (>10000 ph/pixel)
• Frame rate up to 4.5 MHz (1 image every 220 ns)
All the properties have to be achieved simultaneously
DSSC will be the first instrument to fulfill this requirement
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DSSC Overview - Concept
● DEPFET Active Pixel Sensor
● Readout Concept Fast analog shaping Immediate 8 Bit digitization (9 bit for f ≤ 2.2 MHz) In-Pixel SRAM Readout during macro bunch gaps
● Power cycling
Focal Plane
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• 1024x 1024 pixels
• 16 ladders/hybrid boards
• 32 monolithic sensors 128x256 6.3x3 cm2
• DEPFET Sensor bump bonded to 8 Readout ASICs (64x64 pixels)
• 2 DEPFET sensors wire bonded to a hybrid board connected to regulator modules
• Dead area: ~15%
x-y Gap
128 x 256 Pixel Sensor
21 c
m (1
024
pixe
ls)
DSSC Overview-‐ Focal Plane Overview
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DSSC overview – ladder module
~3 mm
1-2 mW/pixel peak power (SENSOR+FRONT-END) 1-2 kW peak power
Power cycling about 1/100
<400 W mean power inside vacuum
I/O Board
Regulator Bo
ard
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DSSC DEPFET
4.5 MHz frame rate
Every DEPFET pixel provides detection and amplification with:
Intrinsic low noise due to the small anode capacitance single photon
sensitivity even at 0.5 keV
Signal compression at the sensor level thanks to the special internal
gate topology high dynamic range
Charge collection time ~ 60 ns
Cu layer for bump-bonding allowing
full parallel readout
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DSSC DEPFET Principle
Standard DEPFET principle
o p-‐FET on depleted n-‐bulk
All signal charge collected in poten+al minimum below FET channel "internal gate"
all signal charges cause an equal effect on the FET current
linear ΔI/Qsig characteristics
o reset via ClearFET
o low capacitance & noise
DSSC adaptation
signal charges at high levels also stored under source
less/no effect on FET current
non-linear ΔI/Qsig characteristics
gain curve engineering by dose & geometry of implantations
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DSSC DEPFET – Simulation and Layout
236 µ
m
272 µm Pitchx: 204 µm Pitchy: 236 µm
DEPFET
Dri_ rings
• hexagonal shape
- side length 136 µm (A=48144 µm2)
- compatible with C4 bumping @ IBM
• technology
- 2 polySi layers
- 2 + 1 metal layers
- 12 implantations
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In the linear region the noise is dominated by electronics noise of the sensor and the readout electronics
Single photon detection properties are given by the electronics noise of the system with empty internal gate
For a high input signals more photons fall within one ADC bin. The quantization noise is dominant.
The quantization noise is always below the poisson noise of the photon generation process
Analog to digital conversion – single photon detection and quantization noise
Electronics noise ADC bin size
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Dynamic range
1 ph @1keV Dynamic range for 3keV
ph – 8 bits (~8300 ph.)
256 x bin size @3 keV
The achievable dynamic range depends on: • The shape of the DEPFET non-linear characteristic • The number of bits of the ADC • The number of bins of the ADC associated to the signal produced by the first collected photon • The photon energy.
• The dynamic range increases with the photon energy. This is because as the photon energy increases, the number of photon falling in the low-gain region of the DEPFET response also increases: it is possible to allocate more photons in the same number of bins
Dynamic range for 1keV ph – 8 bits (~2400 Ph.)
256 x bin size @1 keV
8 bit 28 bins = 256 bin
Bin size
Bin size
1 bin / ph.
1 ph @3keV
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Dynamic range
1 ph @1keV Bin size
Dynamic range for 1keV ph – 8 bits (~2400 Ph.)
256 x bin size @1 keV
The achievable dynamic range depends on: • The shape of the DEPFET non-‐linear characteris+c • The number of bits of the ADC • The number of bins of the ADC associated to the signal produced by the first collected photon • The photon energy.
• The dynamic range increases with the number of bits
1 bin / ph.
Dynamic range for 1keV ph – 9 bits (~12080 ph.)
512 x bin size @1 keV
9 bit 29 bins = 512 bin
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DSSC overview - ASIC
Every ASIC pixel comprises in 206 x 236 µm: • A trapezoidal analog filter (optimum filter for white series noise) • A single slope 8 bit ADC (9 bit for f≤2.2 MHz) • An SRAM able to store ≥640 frames
Gain and offset can be adjusted pixel-‐wise
Single slope ADC ASIC final format : 64 x 64 pixels 130 nm CMOS Process C4 Bumps
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MAIN ACHIEVEMENTS (on sensor and readout ASIC)
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Sensor - Measured Non-linear 7-cell DEPFET Prototype
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spectroscopy
o Fe55 source
linear region of the gain curve
noise peak ~ 10 el. ENC
Mn-Kα line ~ 150 eV FWHM @ 5.9 keV
Response to a pulsed laser/electrical charge injection
increasing number of identical pulses
peaks are equidistant in terms of signal charge
signal compression @ large charge amount
"energy" calibration using Fe55 spectrum
non-linear gain of DEPFET prototype
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non-‐linear gain DEPFET (pxd-‐7)
signal compression
o seven cells of a cluster
o standard variant (W/L = 25/3)
o sensitivity in the linear region
gq ≈ 600 pA/el.
o compression factor
~ 17.5
o current dispersion
ΔI/I ≈ 10 %
non-linear vs. spectroscopy type DEPFET
o equal gate dimensions
W/L = 25/3
o performance at small energy
equal within sample-to-sample variation
o spectroscopy-type DEPFET stays linear
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13sep11
The full format sensors in the final technology are in production
3 sensors in final 128 x 256 format
7 prototypes in 128 x 64 format
small test structures
- 8 x 8, bump-bonded matrices - 7 pixel clusters wire bonded
structures
Only the Cu layer is still missing PXD-‐8 wafer – layout program screenshot
Full size sensor production
1st probe station measurements
DEPFET characteristics IS(VGS)
threshold voltage
Vth = 1.9 V
transconductance
gm ≈ 100 µA/V @ IS = 100 µA
all measured paramters are within specs
• We expect a successful end of the production by spring 2013
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• UBM – third metal layer Cu
– Cu electro-‐pla+ng process installed and commissioned – sensor dummies and test structures produced – Tests on double-‐sided diodes and MOS caps in the DSSC technology
– No altera+on of the electrical proper+es Leakage current of double sided diodes CV curves of MOS structures
~6µm of Cu, on SiO2
interconnection – Cu deposition
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Flip-chip at HLL
Bumped chips with daisy chains:
:- Al-BCB-Cu (~4µm) technology
:- PacTech SAC305 bumps, ~200 µm pitch, ~4000
bumps/chip
:- 1.4x1.5 cm²
Test substrates:
:- landing pattern for chips, daisy chains
:- Al-BCB-Cu (~4µm) layer, no solder stop
:- two chips/substrate
Segmentation of the daisy chains:
max: 2048 solder connections
min: 32 solder connections
SAC305: Sn96.5Ag3.0Cu0.5, Liquidus: 220 °C, Solidus: 217 °C
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flip chip – daisy chains
“Perfect” (self) alignment (for this pitch at least)
Daisy chain results Chip 1: all of 4096 good Chip2 : 1 line of 32 bumps faulty
» 1 or 32 bumps bad??? Bump??
If 32/8196 bad: 99.6 % yield If 1/8196 bad: 99.99 % yield
profiler measurements show that the chips and substrate are almost perfectly plane-parallel on the 5µm level
gap between chips: 150 µm (left), 148 µm(right)
150 µm
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8 x 8 Mini-ASIC prototype
229 x 204 µm
13.0 el
1 MHz
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~15 e 250ns filtering
Noise fully compatible with expectations
55Fe
8 x 8 Matrix ASIC measurements
ADC characteristic Monotonic, no missing codes INL~ 0,5 LSB, DNL~16%
Full readout chain measurements:
55Fe spectrum acquired with the full chain and standard DEPFET
Non-linear DEPFET characteristic
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System Simula+on
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DSSC simulation: 1 keV photons 1 keV calibration: one bin per photon noise as estimated for 4.5 MHz operation Split events ASIC measured parameters
[pho
tons/pixel]
[pho
tons/pixel]
input photon distribu+on
reconstructed photon distribu+on
System Simula+on
T4 virus diffraction pattern S. Kassemeyer, “Femtosecond free-electron laser x-ray diffraction data sets for algorithm development,” Opt. Express, vol. 20, no. 4, pp. 4149–4158, Feb 2012.
False photon detec+on: P(1|0) = 0.003
False detection
Difference smaller than Poisson error of input signal
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Summary & Conclusions
We are developing a Pixel Detector system for the European XFEL based on innovative non-linear DEPFET devices
In our fully parallel readout scheme, the signals coming from the pixels are filtered, digitized and stored in the focal plane
The DEPFET signal compression principle has been experimentally verified
An 8x8 readout ASIC comprising the whole pixel readout chain has been produced and tested.
Estimations based on the first experimental result show that it will be possible to achieve single photon detection and high dynamic range also for low energies.
The first DSSC Sensor full format sensors will be available in spring 2013. One working quadrant (512 x 512 ) will be available in 2015
The full camera will be available in the middle of 2017
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Thank You
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