device simulation of esd protect elements
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Diss. ETH No. 14466
Device Simulation of
ESD Protection Elements
A dissertation submitted to the
SWISS FEDERAL INSTITUTE OF TECHNOLOGY
ZURICH
for the degree of
Doctor of Technical Sciences
presented byKAI ESMARK
Dipl. Phys.
University of HamburgBorn 25.11.1970
Citizen of Germany
Accepted on the recommendation of
Prof. Dr. W. Fichtner, examiner
Prof. Dr. H. Melchior, co-examiner
2001
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AcknowledgmentsThe results I present in this thesis were gained during an excellent collaboration
between a scientific (Integrated Systems Laboratory, Swiss Federal Institute of
Technology Zurich -ETH Zrich-, Switzerland) and an industrial partner(Infineon Technologies AG, division CPD DAT LIB 10, Munich, Germany).
I wish to thank Prof. Dr. Wolfgang Fichtner (Head of Integrated Systems
Laboratory, IIS) for his guidance and assistance throughout this work. Beside
the provision of an outstanding working environment he always asked me the
"right" questions leading to a continuous development of the thesis and finallyto the success of the project.
I am
gratefulto Prof. Dr. Hans Melchior
(ETHZ)for his
biginterest to co-
examine this thesis.
I would like to express my sincere appreciation and gratitude to my mentor and
adviser, Dr. Wolfgang Stadler (Infineon Technologies AG, IFX). Whether
discussing latest ESD device simulation results, finalizing conference abstracts
and papers before deadline late in the night, or simply organizing things for mewithin the company, no doubt, he always lend me a helping hand.
A big word of thanks goes to Dr. Harald Gossner (IFX). Several parts of this
thesis base on his interesting questions, ideas and actual case studies.
Additionally I owe him the very valuable collaboration with the Technical
University of Vienna.
Of course I do not want to forget to address my best regards to all current and
former members of the ESD and Latch-up Team at IFX: Frau Dr. Silke
Bargstdt-Franke, Xaver Guggenmos, Dr. Harald Gossner, Dr. WolfgangStadler, Dr. Martin Wendel, Dr. Klaus Oettinger, Dr. Martin Streibl, Dr. PhilippRiess, Michael Meyer, Kurt Schubert, Reinhold Grtner, Dr. Tilo Brodbeck, Dr.
Jacek Szatkowski, Franz Zngl, Dr. Johannes Bieger. It was really a pleasure forme to be part of this group. I enjoyed an incredible and spiritual working
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atmosphere, whether during technical discussions or in the extremely friendlyintercultural exchange of Bavarian and Hanseatic habits. Thank you very much! !
I would like to express my gratitude to all members of the IIS. A special thank
you to Dr. Dlf Aemmer, Dr. Norbert Felber, Christine Haller, Bruno Fischer,
Dr. Andreas Schenk, Dr. Andreas Wettstein, Dr. Wladislaw Grabinski either for
their continuous technical or administrative support. I really enjoyed workingwith you! Furthermore I would like to specially thank Dr. Andreas Strieker for
introducing me to TCAD, ESD, and Swiss habits ("Zvieri").
This thesis would not be that valuable without the perfect collaboration with the
team members of the Institute of Solid State Electronics of the Technical
University of Vienna. Together with Prof. Dr. Erich Gornik, Dr. Christoph
Frbck, Martin Litzenberger, and Dr. Dionyz Pogany we have brought the
Backside Laser Interferometry to the point that it became a tremendous toolallowing the interpretation of thermal and carrier distributions under ESD stress
conditions. Of course I do not want to forget to mention Dr. Matthias Stecher
and Dr. Gerhard Groos from IFX AI for their valuable contribution in this
project as well.
Many people from all over the different departments of IFX have helped me to
draw up this thesis. Thanks to the SIM group (Dr. Hartmut Dettmer, Dr. Ingo
Bork, Dr. Karl-Heinz Bach, Dr. Dietrich Bonart, Dr. Matthias Hierlemann,
Dr. Ernst Strasser, Dr. Paul Kuepper, Dr. Cajetan Wagner, Dr. Matthias
Stiftinger, Dr. Andreas v. Schwerin, Manfred Eller), to Dr. Jrgen Holz and Dr.
Thomas Schafbauer providing me perfect introduction to "their" technology
babies, and also to Stephan Schoemann from the Physical Failure Analysis
group. Additionally I would like to mention Dr. Heinz Endriss and Dr. Ulf
Schlichtmann for their helpful administrative support.
I would like to thank Prof. Dr. Winfried Soppa and his coworkers Achim Stangeand Bernd Ramler from the Fachhochschule Osnabrck as well as StephanMettler from Bosch. I really enjoyed our very good and fruitful collaboration in
the PARASITICS project.
A big thank you to Henry Wolf, Dr. Horst Gieser from the Fraunhofer
Gesellschaft in Munich but also to Christian Muhoff from IFX for their
valuable support concerning special electrical measurements and the
unconventional troubleshooting of our TLP test equipment.
Thanks to the members of the ISE AG for their quick and continuous support in
case of questions regarding the simulation tools.
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I would also like to say thank you to Dr. Christian Russ (Sarnoff Corporation),Robert Gauthier and Chris Putnam (IBM), and Charvaka Duwury (TI) for very
interesting and intense discussions about ESD.
A
specialthanks
(Mitfreundlichen
Grssen) goesto Richard Aburano
(IFX).His patience and endurance during his very careful proofreading of my thesis is
highly appreciated.
I give my parents a big hug for crossing fingers and continuous support during
writing my thesis. Whenever they visited me "down under" they enjoyed life in
the cities of Munich and Zurich like me.
In general, I would like to express my gratitude to the Infineon TechnologiesAG. In the sense of "Never stop thinking" I enjoyed openness with respect to
sharing of information, and publishing papers as well as the continuous support
throughout my studies.
Thanks to Infineon's canteen cooking the best Kaiserschmarrn in the world and
last but not least, I am grateful to aconcagua, eismeer, andorra, rio,
pearl and all the other workstations for happy number crunching .
Now I declare open the discussion about "Device Simulation of ESD ProtectionElements"
...
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Zusammenfas sung
In keiner anderen Branche ist das sogenannte first time right" Prinzip so
ausgeprgt wie in der Halbleiterindustrie. Es stellt das zentrale Leitmotiv im
Hinblick auf die Entwicklung und Einfhrung einer neuen Prozesstechnologiedar. Zu der eigentlichen Entwicklung der einzelnen Prozessschritte gesellt sich
parallel der Aufbau einer sehr komplexen und umfangreichen Infrastruktur, die
von der Entwicklung einzelner Zellbibliotheken bis hin zur Realisierung des
schlussendlichen Produkts, dem integrierten Schaltkreis reicht.
In all diesen Entwicklungsebenen mssen die Probleme, die mit dem
Phnomen elektrostatische Entladung (ESD)" einhergehen, beachtet werden,insofern als das Manahmen zum Schutz vor elektrostatischen Entladungensowohl in der Prozesstechnologie als auch im spteren Produkt abgeleitetwerden mssen.
Wege und Mglichkeiten zur Optimierung der intrinsischen ESD Festigkeitder Prozesstechnologie sowie die Entwicklung von Strategien und Lsungen fr
ESD Schutzkonzepte mssen schon in einem relativ frhen Stadium der
Prozesstechnologie durchdacht und ausgearbeitet werden. Damit insgesamtsowohl der finanzielle als auch der zeitliche Entwicklungsaufwand so gering wie
mglich gehalten wird, um so die Zeit bis zur Marktreife zu verkrzen, wird in
der Halbleiterindustrie seit lngerem Gebrauch von Simulatoren, sogenannter
TCAD1 Software, gemacht. Whrend diese TCAD Werkzeuge bereits eine
wichtige Rolle in der gewhnlichen Prozessentwicklung spielen, so waren sie
eher von untergeordneter Rolle im Bereich der ESD Entwicklung. Ein
Hauptproblem besteht darin, dass der normale Betriebsbereich, fr den die
physikalischen Modelle getestet und verifiziert worden sind, fr die
Nachbildung eines ESD Ereignisses verlassen wird. Diese Modelle selber stellen
ja die Berechnungsgrundlage fr das Bauelementeverhalten dar. Ein anderes
Problem besteht in der Frage, ob das Verhalten von ESD Schutzelementen unter
ESD Belastung berhaupt mit den standardmig zur Verfgung stehenden 2-D
Simulatoren beschrieben werden kann oder ob nicht 3-D Effekte das
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Technology Computer Aided Design
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Bauelementverhalten so dominieren, dass hier eigentlich nur 3-D Simulatorenzum Zuge kommen knnen. Zusammengefasst bedeutet dieses: man musszunchst verifizieren, ob sowohl der gemachte Simulationsansatz als auch der
Gltigkeitsbereich der Simulatoren so gegeben ist, dass typische
Problemstellungenin der ESD
Entwicklung berhauptmit der
heute zurVerfgung stehenden TCAD Software angegangen werden knnen.
In Bezug auf den Gltigkeitsbereich der physikalischen Modelle gab es zu
Beginn dieser Arbeit ein Informationsdefizit insbesondere auf bauelementinterne Vorgnge unter Hochinjektions- und Hochtemperaturbedingungen, wiesie fr ESD nun einmal typisch sind. Die seit kurzem zur Verfgung stehendenneuen experimentellen Mglichkeiten, wie beispielsweise die elektrische
Charakterisierung unter erhhten Umgebungstemperaturen oder die
Bestimmung von Temperaturverteilungen im Inneren von Bauelementen unterESD Stress Bedingungen, gestatten den Versuch, gemessene und simulierte
Ergebnisse unter ESD Bedingungen zu vergleichen. Mit Hilfe der
experimentellen Vorgaben knnen die physikalischen Modelle nun kalibriertund teilweise nachgebessert werden, sodass sie auch unter
Hochtemperaturbedingungen sinnvolle Resultate produzieren.
Der ggNMOS2 Transistor ist ein gngiges ESD Schutzelement und dientdieser Arbeit als Beispiel, um die notwendigen Arbeitsschritte zu erlutern,damit verwertbare Informationen im Hochstrombereich mit Hilfe eines
kommerziellen Bauelementesimulators gewonnen werden knnen. Das Ziel ist
es, die Bauelementesimulation als Vorhersageinstrument fr den ESD Designeraufzubauen. Darber hinaus ist es notwendig, ein verbessertes Verstndnis frdas bauelementspezifische Verhalten unter Hochstrombedingungen zuerarbeiten, wie beispielsweise das Phnomen des zweiten Durchbruchs.
Aus der Sicht des ESD Entwicklers und dem Design von geeigneten ESD
Schutzkonzepten sind zwei Dinge wichtig. Dieses betrifft die Bestimmung vonelektrischen Parametern im Hochstrombereich, sowie der Vorhersage von
Ausfallschwellen.Wie
in dieserArbeit gezeigt wird, knnen viele
Fragestellungen mit Hilfe eines gut kalibrierten 2-D Bauelementesimulatorsbeantwortet werden, einige bleiben aber offen.
Unter der Voraussetzung, dass das Schutzelement homogen aufsteuert, dasheit gleichfrmig entlang der Bauelementweite funktioniert, sind dieberechneten Strom- und Temperaturverteilungen in sehr guter bereinstimmungzu den Messergebnissen. Die bereinstimmung ist so gut, dass damit in einerfrhen Phase flchenoptimierte ESD Schutzkonzepte abgeleitet werden knnen.
2
grounded gate NMOS
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Auf dem Arbeitsgebiet der ESD Entwicklung bedeutet dieses einen Meilenstein,
da man dem Ziel first time right" damit schon recht nahe kommt.
Die Regeln, die in dieser Arbeit fr die Vorhersage von Ausfallschwellen
erarbeitetwerden,
basieren auf der
Auswertungvon
Temperaturverteilungen,sowie dem Detektieren des zweiten Durchbruchs. Hier wird wiederum eine sehr
gute bereinstimmung mit experimentellen Vorgaben erzielt. Das
Fehlerkriterium ist unabhngig vom jeweiligen Stresspuls anwendbar, egal ob
das Bauelement nun nach dem Human Body Model" (HBM) oder mit Hilfe
von Transmission Line" (TL) Pulsen gestresst wird. Durch die sehr gute
Wiedergabe von gemessenen Temperaturprofilen kann eine Optimierung der
Prozesstechnologie, sowie des jeweiligen ESD Schutzelements im Hinblick auf
die thermische Belastung unter ESD Stressbedingungen erzielt werden.
Bauelemente, die wie ein ggNMOS Transistor ein Rcksprungverhalten
aufweisen, mssen nicht im gesamten Einsatzbereich gleichfrmig entlang der
Bauelementweite aufsteuern. In einigen Fllen kann das Bauelementeverhalten
aber auch im gesamten Operationsbereich, unter Einschluss des Ausfalls, von
dreidimensionalen Effekten geprgt sein. Es ist offensichtlich, dass in diesen
Fllen ein 2-D Bauelementesimulator das Verhalten nicht nachstellen kann. Hier
ist der Einsatz von 3-D Bauelementesimulatoren unabdingbar, um mehr
Hintergrundinformationen zu bekommen, welche Layout- und
Designeigenschaften der Struktur eine Stromfilamentierung beschleunigen und
damit die ESD Festigkeit des Bauelements begrenzen.
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Abstract
"First time right" is the guiding principle for every semiconductor companywith respect to the introduction of a new process technology. Beside the
development of the single process steps, a whole new and complexinfrastructure has to be set up, which reaches from the development of singlecells of a specific I/O library to the realization of a complete product, an
integrated circuit.
The problem regarding electrostatic discharge (ESD) is present at every stageof the development level, as considerations concerning the protection againstelectrostatic discharge are encountered in the definition of a new process as well
as in the product.
Strategies and solutions for ESD protection concepts and suggestions for the
optimization of the process concerning its intrinsic ESD characteristics have to
be found by the engineer in a very early stage of the process development. To
achieve very short time to market and reduce the development effort, one tries to
make use of the benefit of simulation tools. Whereas TCAD1 tools have been
used a long time in the ordinary process development, simulators have had a
minimal role in ESD engineering. The reason is the operational regime of an
ESD protection element is far outside the range the physical models have been
tested and verified. These models serve as the basis for such kinds of
calculations. A further question is, if the conventional 2-D simulation approachof today's TCAD tools is able to describe ESD protection elements under ESD
conditions or in how far 3-D effects need to be considered too. To sum up: to
use TCAD software for typical problems in the field of ESD it needs a
verification, if the simulation approach is correct and if the physical models are
valid under ESD like conditions.
Before this thesis, there was a great lack of information concerning internal
device processes under high current injection and high temperature conditions
that are characteristics of ESD events. Recently available new experimental
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Technology Computer Aided Design
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techniques, like 7F-tracing at elevated temperatures and thermal mapping of
ESD protection structures under ESD stress conditions, make an attempt to
compare measured and calculated results under ESD conditions. Based on the
experimental results, the single physical models were calibrated and partly
improved,so
theyfit
quitewell in the
high temperature regimeand
providereasonable results.
The ggNMOS2 transistor is a widespread ESD protection element and servesin this thesis as the test case to discuss the necessary steps to gain reliable and
usable information from a commercial device simulator under high current
operation. The goal is to make device simulation a predictive tool for ESD
designers. This is achieved through a greater understanding of device specificbehavior under ESD stress conditions, for example 2 breakdown.
From the viewpoint of an ESD engineer and designing an appropriate ESD
protection concept, two issues are of particular interest. They are the
determination of electrical parameters in the high current regime and the
prediction of failure thresholds. As shown in this thesis, many questions can be
answered by means of a well calibrated 2-D device simulator, but some of them
cannot.
Under the condition that the protection device is triggered homogeneously
meaning it is operating uniformly along the device width, the calculated current
density and temperature distribution are in very good agreement to the measuredvalues. The correspondence is so good, that area optimized pre-Si ESD
protection concepts can be derived very early. This itself represents a milestone
in the field of ESD, since this comes very close to the target of "first time right".
The rules for the prediction of failure thresholds derived in this thesis are
based upon the evaluation of temperature profiles and the detection of 2nd
breakdown; here again, an excellent agreement to experimental results wereachieved. The failure criteria are applicable independent of the stress type,whether the device is tested
accordingto the Human
Bodymodel
(HBM)or
with Transmission Line (TL) pulses. In addition the very good reproduction of
measured temperature distributions allows optimization of the process
technology and the particular protection element with respect to thermal stress
under ESD stress conditions.
Unfortunately, devices pushed into snap back like the ggNMOS transistor do
not always necessarily operate homogeneously along the device width, even
though the current regime that the device operates non-uniformly can be
restricted to a very small current region. In some cases, the device behavior is
2
grounded gate NMOS
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affected by 3-D device effects in the whole operating regime, including the
device failure under ESD condition. It is obvious in this case that these issues
cannot be handled in a 2-D device simulator. The use of 3-D device simulation
is very valuable to gain background information about layout and technologyissues that accelerate the
processof current filamentation and limit the ESD
robustness of the device.
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Contents
Acknowledgments i
Zusammenfassung iv
Abstract vii
1 Introduction and Motivation 1
2 ESD Protection Elements and Calibration of the Device 7
Simulator
2.1 General Considerations 7
2.2 The ggNMOS Transistor 11
2.3 Technology Under Investigation 13
2.4 Calibration of the Device Simulator 15
2.4.1 Process Technology Specific Calibration 16
2.4.2 Simulator Specific Adjustments 20
2.4.3 Device Simulation Mesh and Boundary 26
Conditions
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3 ESD Device Simulation: I) Verification and First 33
Applications
3.1 Electrical Parameters in the Snap Back and High 33
Current
Regime
3.2 Derivation of an Area Optimized Pre-Silicon ESD 46
Concept
3.3 3-D Device Simulation 49
3.3.1 Set-up of 3-D Devices in the Device Simulator 49
3.3.2 First 3-D ESD Device Simulation Results 52
3.3.3 Rise Time Dependent Effects 56
3.3.4 Discussion of Triggering Behavior 60
3.3.5 Concluding Remarks 69
3.4 Simulation of Temperature Profiles 70
3.5 Summary 76
4 ESD Device Simulations: II) Failure Mode Detection 77
4.1 Experimental Results 78
4.2 Correlation of Failure Modes and Simulated Parameters 87
4.2.1 Definition and Implementation of a Failure 87
Criteria
4.2.2 Discussion of Failure Modes 89
4.2.2.1 Occurrence: Tmax > Tmdti Si 89
4.2.2.2 Occurrence: 2nd Breakdown 94
4.2.3 Final Evaluation of 2-D Simulation Results 107
4.3 Failure Modes Related to 3-D Effects 110
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4.4 ESD Robustness due to HBM 114
4.4.1 Introduction to HBM 114
4.4.2 Evaluation of the
DischargeWaveform 115
4.4.3 Simulation of the HBM Damage Threshold 118
4.4.4 Influence of Tester Parasitics 125
5 Conclusion 129
5.1 Major Results 129
5.2 Outlook 130
Appendices 133
A Experimental Techniques 133
Al Backside Laser Interferometry (BLI) 133
A2 Transmission Line Pulsing (TLP) 136
B Symbols and Short Forms 137
Bibliography 139
Curriculum vitae 149
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Chapter 1
Introduction and Motivation
An electrostatic discharge (ESD) is a re-balancing of charge between objects
brought into close contact. Depending on the configuration of the objects, the
exchange can result in a very rapid (a few ns to 200 ns) and very high current
pulse of several amps. In general, the presence of electrostatic discharges has
always been a serious problem in the semiconductor industry [Wagner93]. Due
to the small size of semiconductor devices, the amount of energy, which is
deposited in the elements can be so high that the semiconductor material can
suffer local melting. Another aspect, which accompanies the topic ESD is the
occurrence of high electric fields. They can cause electric breakdown of the
sensitive isolation layers, especially the thin gate oxides in CMOS technologies.In sum, these effects can result in latent damage or even a breakdown of the
whole integrated circuit (IC), which is in some cases a relevant safety issue.
It can not be avoided that throughout its ordinary "lifetime", the chip is
several times endangered by an ESD event. Typical situations include the
handling of a wafer during chip fabrication, the bonding and packaging of the
silicon as well as the installation of an IC into an electronic application by a
machine or human being. One efficient countermeasure to prevent the
destruction of the chip is to safely ground every human being or machine thatcomes into contact with the integrated circuit. In addition to that the product is
equipped with an adequate ESD robustness by implementing a kind of lightningconductor or shunt path in the form of a protection element or a protection
circuitry on the product itself. Then, to assign the chip an ESD robustness, the
IC is tested and qualified based on several standardized stress models which
reflect the typical discharge events described above. Among them the most
important are the Human Body Model (HBM) [ESD98] and the Charged Device
Model (CDM) [CDM93].
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Introduction and Motivation
As the demand for higher performance and a higher level of integration on the
chip steadily increases, the minimum feature size of the single devices in an IC
has to shrink, driving the need to develop completely new process technologies.The reduction of the area consumption of the single devices has to be achieved
in common with characteristic features like speed, leakage current and drive
capabilities, while adhering to necessary reliability criteria (e.g. gate oxide
lifetime). With respect to ESD, it is not obvious that for a novel process
technology the protection devices and concepts can be adopted from a preceding
technology. New ESD protection strategies might be worked out, as its triggerand voltage clamping capabilities are no longer conforming with the electrical
boundaries in the new technology. Furthermore, protection concepts need to be
reworked for novel I/O interface standards like a USB.
The tough competition between the different semiconductor companies has
led to a strong reduction in the time to market and the development cycle for a
new process technology. Concurrent engineering becomes inevitable, which
causes conceptual disadvantages in the field of ESD (Fig. 1-1):
Within the process definition (PD) of a new technology, a set of pre-SiESD guidelines as well as a pre-Si ESD library has to be provided for
pilot products. Without additional information and verification on silicon,both the guidelines and libraries have to be derived empirically by the
engineer on basis of experience with preceding technologies. Therefore, it
cannot be fully guaranteed that the delivered pre-Si ESD library isappropriate and the ESD protection concepts implemented in the new
technology pilot products will operate properly from the beginning. In the
worst case scenario, this would mean the loss of valuable developmentresources and competitive disadvantage through the loss of a development
cycle, high re-design costs, and lost time to market.
Since the electrical properties of all the possible elements for a new
technology ESD concept are not known a-priori in the ESD relevant highcurrent
regime,it is
impossibleto focus on a fixed set of
protectionstructures. This may require that the first evaluation ESD test chip (T.C.)available in the new process technology has to cover dozens of different
protection device prototypes. Due to the quantity of devices to be
evaluated as well as the large number of analysis tools, the evaluation of
the test chip can become very time consuming. The characterization
methods range from low current (DC) and high current characterization
(via transmission line pulsing) to ESD stress testing (HBM/CDM). The
characterization includes optical investigations and physical failure
analysis as well. This can endanger the subsequent milestones of the
technology ESD development, like the delivery schedule of post-Si
guidelines (Fig. 1-1).
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Process
Definition
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ca
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Figure
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1:
Deve
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for
ESD
pro
tec
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I/O
-lib
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in
a
new
tec
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logy
.
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Introduction and Motivation
As first reliable silicon material is only available after a certain delay, it is
nearly impossible to come up with suggestions to improve single process
steps with respect to ESD issues until process freeze.
The
only wayto overcome the
conceptual problemof concurrent
engineeringfor ESD engineers is to make use of a simulation tool right from the beginningof the process definition. At least the characteristic tendencies regarding the new
process (doping profiles, geometry of the devices) are available very early. Theycan be processed with a Technology CAD (TCAD) package for quick and
efficient ESD engineering as Strieker has recently demonstrated in [StrickerOO].In general, the application of TCAD tools in the field of ESD device engineeringseems to be attractive for many reasons:
1. The large number of test structures and particularly its layout variations
on an ESD test chip can be greatly reduced, since the main influencingelements have already been selected in the preliminary simulation study.Since the electrical properties of the relevant protection devices (like
triggering behavior and voltage clamping) are available in the simulator,an efficient IO-specific and area optimized pre-Si ESD concept can be
derived.
2. It can provide suggestions for process optimization. Technology
development includes fine tuning of one or more process steps to achieve
an overall optimum in the technology performance. Even with theknowledge of an expert it is difficult to estimate the impact of process
changes onto the ESD robustness for complex protection devices such as
thyristors. The use of TCAD tools provides not only the possibility to
look inside the device to evaluate pros and cons with respect to
hypothetical process changes, it helps to shorten the development cycle
dramatically, since the expensive and time consuming production of
wafers is avoided. Of course, a final verification always has to be
performed on silicon.
In addition to the already discussed operational area, further fundamental
questions and issues with respect to ESD can be treated in a simulator. These
include:
3. Which physical process may be responsible for the breakdown of an ESD
protection element (e.g. the melting of contact holes or thermal
destruction of a /-junction) and how can the device be improved with
respect to its failure behavior?
4. Investigate the interaction of the protection element with the rest of a
complex I/O-pad [MergensOl].
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Outline of the Thesis
Within this work, the focus is on the first three items, where it has been
successfully demonstrated that they can be treated in a device simulator. At the
beginning of that study, the feasibility of device simulation to the area of ESD
was questionable due to the unusual situation of the simultaneous occurrence of
highcurrent
densities and high temperatures. It required to prove the validity ofthe physical models and the practicality of the numeric calculation. Concurrent
to this thesis, there were several industrial projects (e. g. ESDEM [ESDEM99],PARASITICS [PARASITICSOO]) in the last three years that verified and
corrected the physical models applicable in the high temperature regime.
Organization of the Thesis:
The focus throughout this investigation about ESD device simulation is on the
grounded gate NMOS (ggNMOS) transistor, which represents one of the
workhorses for the development of effective ESD protection devices. This
particular element is attractive not only for its use in a pre-Si ESD concept.Further aspects are the possibility to design it self-protected and its robustness
with respect to a technological transfer from a fab A to fab B. Chapter 2 first
introduces the fundamental parameters, which are necessary to completelycharacterize ESD protection devices in the breakdown and high current regime.Then the necessary steps to calibrate and prepare the device simulator for ESD
device simulation are discussed in great detail on base of the ggNMOS.
The main part of this thesis, dealing with the application of ESD device
simulation is divided thematically into two sections:
Chapter 3 is dedicated to the verification of some simulated electrical and
thermal properties of the protection element under high current conditions on
base of measured data. Additionally the influence of 3-D device effects are
addressed. A further topic concerns the derivation of a pre-Si ESD concept.
Chapter 4 deals with the feasibility to model and reproduce typical failure and
breakdown scenarios of ESD protection devices by means of a device simulator.
This includes thermal overstress (i.e. 2nd breakdown), effects caused by the 3-Dnature of the device as well as the ESD robustness determined via the HBM.
After conclusion and outlook in Chapter 5, the thesis ends with a short
introduction to an optical characterization method, the so-called Backside Laser
Interferometry (BLI). The possibility to verify calculated current and thermal
properties of ESD protections under high current injection by means of BLI
enhances the reliability of ESD device simulation data.
For ESD basics, the reader is referred to the standard text books of
[Amerasekera95], [Dabral98] and [Russ99]. In the thesis of [StrickerOO], the useof TCAD tools for ESD device simulation has been discussed extensively.
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Seite Leer /Blank leaf
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Chapter 2
ESD Protection Elements and
Calibration of the Device Simulator
The purpose of this chapter is two-fold. First, it provides some generalconsiderations of ESD protection elements, such as important electrical
parameters and how the devices are effectively implemented into an I/O-cell.
Second, it discusses the essential steps in preparing and calibrating the device
simulator to accurately model elements under ESD conditions. Here, the focus
will be on the grounded-gate NMOS (ggNMOS) transistor that represents one of
the standard ESD protection elements.
2.1 General Considerations
The effective use of a protection element is shown for the bi-directional
I/O-pad in Fig. 2-1. In the situation, where the pad is electrically stressed againstone of the power rails Vdd or Vss, the charge that has accumulated on the padmust be shunted safely via a low ohmic path to the particular power rail. This
guarantees that the gate dielectrics in the NMOS and PMOS in the input buffer
are protected against electrical breakdown, as the pad is directly connected totheir gate oxides. The small gate oxide thickness of modern technologiesincrease the susceptibility to electrical breakdown. For the same stress
conditions, the weak parts of the output driver are the /^-junctions. They can
suffer thermal breakdown. In particular, there are two strategies to prevent the
different components of an I/O-pad from breaking down:
1) Provide a specified ESD robustness through proper device design. This is
known as making a device self-protecting. This concept is applicable only
if the driver widths are sufficiently large.
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ESD Protection Elements and Calibration of the Device Simulator
ESD protection/ element
VDD
A
ESD sensitive parts
vss
input buffer output driver
Figure 2-1: Simple schematic for a ESD protected bi-directional I/O-cell. The
ESD protection elements are placed to guard all sensitive parts ofan I/O pad.
2) More generally applicable is the availability of a parallel discharge path
by incorporating special ESD protection elements (Fig. 2-1).
Beside a high area efficiency, the protection element as part of an effective ESD
protection concept has to fulfill certain electrical requirements, which are
summarized in the so-called ESD design window shown in Fig. 2-2 (see also
[Russ99]). In general the considerations in determining a well operating ESD
concept are:
1) The protection element must not interfere with the rest of the I/O-padunder normal operating conditions. This requires usually a small leakagecurrent Ileak and a low input capacitance.
2) The breakdown and trigger voltages Vbd and Vti as well as the clamping
capabilities at relevant ESD stress currents have to be kept low to avoid
destruction of the gate oxides to ensure protection of the internal circuit.
The value for gate oxide breakdown depends on the thickness of the
dielectric as well as on the duration of the electrical stress [Fong87,
WuOO]. The electrical breakdown of other technology spcifie parasitics,such as between n-n diffusions must also be taken into consideration.
3)To avoid unintentional
triggeringof the
protection element,the minimum
sustaining point Vsp has to be larger than the signal voltage plus
incorporating a safety margin due to noise or voltage overshoot.
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2.1 General Considerations
4) A good ESD robustness It2 of the protection element demands a lowinternal power dissipation and for some specific elements suitable
triggering of their multi-fingers. Latter one can be guaranteed by choosingan appropriate design for the protection element through suitable selectionof the
device IV characteristics.
Figure 2-2: ESD design window for an ESD protection element indicating the
important electrical parameters in the high current regime. Concerning the
specific parameters see Table 2.1.
In order to choose a proper protection element, all potential candidates haveto be investigated whether they fit to the process technology specific ESD
design window. To prevent damage to the element during high current "ESD"electrical characterization, most of the electrical parameters summarized in
Table 2-1 have to be determined through pulse measurements. For many years,the use of Transmission Lines (TL) to generate square current pulses of a
specific duration and required strength have been widespread to characterizeelements [Maloney85] (see also Appendix A2).
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ESD Protection Elements and Calibration of the Device Simulator
Parameter Description
heal Vsig
(static)
The leakage current Iteak flows when the maximum operating
voltage Vsif, is applied to the protection element. Due to the
typically large device widths (several 100 urn), this parameter
can significantly contribute to the total leakage current of apad, which is defined in the pad specification.
Vbd
(static)
Breakdown voltage, for which the protection element goesinto avalanche breakdown.
Va, hi
@ rise time,
@ Vgate
(dynamic)
Trigger current and turn-on voltage of an inherent element,
e. g. the parasitic bipolar transistor within a NMOS transistor
(Chapter 2.2). The absolute value for an externally applied Vtl
and It] strongly depends on the rise time of the pulse since
displacement currents can reduce the static trigger condition
up to a point where the intrinsic response of the device
(characterized by a so-called base transit time [Krieger89])has been reached. Additionally, a pre-biased gate significantly
reduces the trigger voltage [Amerasekera95].
Vr
sp
@ pulseduration
(dynamic)
The activation of a parasitic device often leads to a negativedifferential resistance branch in the IV characteristic until a
minimum sustaining point Vsp is reached.
Rdi/r
@ pulseduration
(dynamic)
The low ohmic state of the device after snap back is described
by a differential resistance Rdiff. As the pulsed technique givesa dynamic picture of the structure, the extrac-ted value for Rdiffis a function of the duration of the pulse.
Imf
@ pulseduration
(dynamic)
Area optimization often forces a multi-finger (mf) layout of
the protection element. To ensure all fingers are triggered
during an ESD event, the voltage at the pad has to exceed the
trigger voltage VtI at least once again. This is fulfilled at the
current level Imf. This parameter is essential for the definitionof a pre-Si ESD concept (Chapter 3.2).
vt2, hi
@ pulseduration
(dynamic)
Trigger voltage and current level that cause destruction of the
protection element. An example is thermal breakdown due to
the high power dissipation in a very confined area of the
structure (see Chapter 4).
Table 2-1: Summary offundamentalparametersfor an ESD protection element.
A complete characterization demands a specification, whether the parameters
have been measured statically or dynamically. In case they are measured
dynamically, further pulse information like rise time and duration are needed.
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2.2 The ggNMOS Transistor
2.2 The ggNMOS Transistor
A proven protection element often used in a pre-silicon ESD protection
concept in a standard CMOS technology is the NMOS transistor. The device
belongsto the set of active elements and has a suitable breakdown
voltage.Even
today, the ggNMOS transistor [Amerasekera95] with minimum design channel
length and gate- source- and bulk- contacts tied together to ground (Fig. 2-3)
represents the workhorse of many ESD protection concepts. Besides its
electrical properties, the ggNMOS provides additional advantages:
1. Early availability in the development of the process.2. All active elements of the technology are well characterized in an early
stage of the process development.3. The device serves a dual purpose (driver and protection element) and
hence is area effective compared to other devices (PMOS, diode).4. Transferability.
The first two properties guarantee safe operation of the device at any time of the
process development. In order to ensure uniform turn-on of multi-finger
structures, further improvements have been made by using gate-coupling or
substrate pumping techniques [Polgreen89].
n+ drain gate n+ source p+ bulk
Figure 2-3:A
cross-sectional view of the ggNMOS transistor provides insightinto the different potential (Vy), current (e/h) and recombination-generation
(R/G) distributions in breakdown (a) and snap back mode (b).
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ESD Protection Elements and Calibration of the Device Simulator
For the sake of simplicity, the studies in this thesis were carried out on the
ggNMOS transistor. Of course, the results could easily be applied to the more
advanced variations of the ggNMOS.
As discussed in detail
by [Amerasekera95]and references therein, the
operation of the device changes drastically from the ordinary MOS mode to a
bipolar mode under ESD conditions. The key points of the device functionality
during this transition are repeated here. Applying a positive voltage to the drain
reverse biases the drain to substrate junction and gives rise to a reverse current
flow. Further increasing the electric field across the depletion region can result
in the breakdown of the junction due to the generation G (Fig. 2-3 a) of electron-
hole pairs by avalanche multiplication. While the generated electrons are
collected at the drain contact, the generated holes drift towards the bulk contact
giving rise to a substrate current Isub resulting in a voltage drop across the
effective substrate resistance Rsub. If the voltage drop across Rsub is high enoughto forward bias the substrate to source junction, electrons are emitted from the
source into the substrate, which indicates the activation of a parasitic bipolar
transistor, represented by the circuit symbol in Fig. 2-3b. In this state, the drain
of the ggNMOS is the collector of the bipolar, the source of the ggNMOS is the
emitter, and the substrate the base. After turn on of the lateral bipolar transistor,the device characteristic snaps back to a sustaining point Vsp, as more carriers are
available for carrier multiplication. Up to the current value It2, which can be
maximally handled by the device for a certain time as a result of internal power
dissipation, the low ohmic state of the ggNMOS transistor is described by adifferential resistance Rdiff('\g. 2-2).
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2.3 Technology Under Investigation
2.3 Technology Under Investigation
The ESD device simulations for the ggNMOS presented in this thesis arecarried out on two different platform technologies. These CMOS technologieshave a nominal minimum feature size
(gate length) of 0.35iim
and 0.18 urn,respectively and follow completely different process concepts. Table 2-2
provides information concerning some ESD-relevant technology features:
0.35 urn technology 0.18 urn technology
Starting material lightly /7-doped wafer
Device isolation LOCOSShallow Trench
Isolation (STI)
Wells Retrograded -well and p-well are implanted
GOX3 thickness
(nm)8.7 3.5
Suicide
Silicided technology with the option to block the
suicide in the active area to increase the resistance
of the poly/diffusion.
Contact compositionTi/TiN/W plugs yielding good electromigration
properties and avoiding contact spiking.VV
Slg
(V)3.3 10 % 1.8 10%
Vbd poly-bounded n+pjunction @ l|xA/um
(V)
9 5.5
DC VM for GOX
(V)= 10 = 4
Vbd for GOX for 100 ns
(V)= 19 = 10
Sheet resistance Rsq salicide
blocked n+ diffusion
(Q/sq.)
= 60 = 80
Table 2-2: Summary of ESD related process parameters of the two differentCMOS technologies under investigation. Considering DC conditions only, the
breakdown voltage of the gate oxide is too low such that the breakdown of the
n+pjunction could be used to prevent the dielectric breakdown. Under transient
(ESD) conditions, the gate oxide can withstand much higher voltages.
3Gate Oxide
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ESD Protection Elements and Calibration of the Device Simulator
net doping cone. (a.u.)
1
p substrate
Figure 2-4: Process simulated 2-D cross-section doping profile in the drain
region ofthe ggNMOS.
A typical cross-section of a NMOS transistor in the 0.35 |im technology is
sketched in Fig. 2-4. The net doping profile taken along the vertical cutline in
the drain reveals the junction from the n+ drain diffusion to the /-well and the
subsequent transition into the homogenously doped /^-substrate. Beside the
influence of technological parameters onto the electrical properties of the
ggNMOS, the IV characteristic of the device depends further on its design and
layout (Fig. 2-5). The values for the drain contact to gate spacing (DCG), source
contact to
gate spacing (SCG),and source to well
spacing (SWS)have to be
chosen very carefully, because they determine the ESD robustness and the
clamping capabilities of the protecting device (Chapter 3 and 4).
drain
LK>
gate source bulk
BWS fi"SBi>stiteg
LOCOS or STI
Silicide
Figure 2-5: Cross-section of a standard NMOS transistor with silicide blocked
diffusions showing the ESD relevant layout parameters.
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2.4 Calibration of the Device Simulator
2.4 Calibration of the Device Simulator
The doping profiles needed as input for the device simulation are obtained
from a 2-D process simulator (Fig. 2-4), which is TsupremlV [TMA98]. The
verification of the simulated
doping profilesis
performedin two different
wayscomplementing each other.
1) Comparison of doping profiles obtained by process simulation and SIMS.
2) Comparison of device simulated and measured electrical characteristics in
the operating regime for a fixed set of test structures. This includes
capacitance experiments as well as NMOS and PMOS transistor transfer
characteristics.
Since SIMS experiments only resolve the chemical amount of a doping speciesand not the electrical active contribution to the conductivity of the silicon
material, the comparison of simulated and measured electrical data is
indispensable. Additionally, SIMS experiments are limited by their spatial andconcentration dependent resolution and can not be applied to detect the veryimportant lateral diffusion of the doping under the edge of the implant mask.
The three governing equations to model carrier transport in semiconductordevices are the Poisson equation and the continuity equations for electrons and
holes [Selberherr84]. The chosen physical models in the device simulatorDESSISise [ISE98] for the drift diffusion approach are taken from the proposalgiven by [Slotboom93]. The default values in the physical models are reliable
and need only slight adjustment. If large modifications are required, this most
likely indicates an inaccuracy of the doping profiles used. An exceptionrepresents the carrier lifetime, which is a technology specific parameter.
Reasonable ESD device simulation needs different further preparations. One
requirement is a process technology specific adjustment of the carrier lifetimes
based on measured bipolar characteristics (Chapter 2.4.1). On the other hand, itis indispensable to verify or correct simulator specific settings concerning
temperature dependence in the physical model. This is due to the highimportance of thermal effects in the description of protection elements during anESD. This will be carried out in Chapter 2.4.2. The last difficulty of ESD device
simulation regards the choice of suitable electrical and thermal boundaryconditions; these will be discussed in Chapter 2.4.3.
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ESD Protection Elements and Calibration of the Device Simulator
2.4.1 Process Technology Specific Calibration
Within the drift-diffusion approach the lifetime of electrons and holes is the
parameter which is strongly process dependent and therefore has to be calibrated
separatelyfor each
technologyunder
investigation.The lifetime for electrons
and holes governs the spatial and injection dependent recombination rates for
excess carriers. One way to determine these parameters is to measure the current
gain of a bipolar transistor. The nBETA device (Fig. 2-6 , [Russ99]) is suitable
to perform the characterization. As demonstrated below, the implementation of
the parameter "lifetime" in a commercial device simulator usually makes it a
process technology as well as a device dependent parameter. From the close
relationship of the nBETA device to the ggNMOS transistor, there is a decisive
advantage to use it as the element for a lifetime calibration.
All four terminals drain, gate, source, and bulk of the nBETA device need to
be accessible in the measurement (Fig. 2-6). To suppress a MOS-current, the
gate is held at a negative potential, in this case -IV. The collector- and base-
current are then measured as a function of the emitter-base voltage Vbe and the
current gain =ic/ib is calculated (Fig. 2-7). The resultant values for the
measured current gain are very low for two reasons:
1) The relatively large doping concentration of the well leads to a large
gummel number of the transistor [Sze81]. The current gain is inversely
proportional to the Gummel number.
2) According to the calibration results, the source diffusion becomes an
effective recombination area (depicted with R in Fig. 2-3 b). This leads to
a decrease of the emitter diffusion length, causing a degradation of the
emitter efficiency [Sze81].
Drain Source Bulk
(collector) (emitter) (base)
p-well, p-substrate
Figure2-6: Cross-section and bias scheme
ofthe device used to characterize
the parasitic bipolar transistor of the NMOS transistor.
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2.4 Calibration of the Device Simulator
2.5
2.0
-u 1.5ii
CO.
1.0
0.5
nbeta:
measurement
Asimulation, def.:
Tn= 1e-5s, y=1
simulation, calibrated:
t = 6.5e-8 s, y= 0.55
r
i mi I I I I I I
^V
.''I*
***""
k
k
1E-3 0.01 0.1 10
I (mA/pm)
Figure 2-7: Measured and simulated current dependence of the bipolar gain forthe nBETA device in a 0.35 jum process technology. The default parametervalues in the simulation model for SRH-recombination have to be adjusted to
achieve good agreement with the experimental data.
The measured bipolar current gain is used next to adjust the excess carrier
lifetime in the device simulator. In the simulator, the overall lifetime of a carrier
is limited by the different recombination mechanisms each one represented by a
specific lifetime parameter [Selberherr84]. In particular, these are:
Recombination MechanismLifetime
Parameter
Indirect recombination via deep impurities TSRH
Auger Taug
Trap-Assisted-Auger (TAA) Ttaa
Table 2-3: Different recombination mechanisms in silicon considered in the
device simulation.
Auger recombination belongs to the class of intrinsic recombination processes
and is therefore an unavoidable material property [Hcker94]. The coefficientsthat enter the description of the model are well accepted, so no further
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ESD Protection Elements and Calibration of the Device Simulator
adjustment is necessary for this mechanism. Opposite to Auger recombination,
the Trap Assisted Auger recombination and the recombination via deep level
traps (so-called SRH recombination) belong to the class of extrinsic
recombination mechanisms. Deep traps with an effective cross-section may
originate by impuritiesor
damagecaused
duringion
implantation.As a result
the traps strongly depend on the type of process and trap characterizing
parameters have to be calibrated individually for the investigated technology.The classical Scharfetter relation for SRH recombination links lifetime and the
local background doping concentrations N [Selberherr84]
TSRH(N)= ^ . n n
i+
KN* >
The quantities t, Nre/and /represent the independent fit parameters that are
adjusted based upon the measured current gain (Fig. 2-7). In comparison to the
default settings in the simulator, the value for t chosen here is relatively smallQ
(t = 6.5-10" s), which is a consequence of the reduced thermal budget of
modern MOS-technologies. The new technique of Rapid Thermal Annealing
(RTA) allows the reduction of the thermal budget since implanted species can be
partly electrically activated, preventing simultaneously the diffusion of the
dopants. Due to the required pre-amorphization of source and drain regions priorto implantation in modern process technologies, the reduced thermal budgetdoes not allow a complete anneal of the implantation damage which leads to the
reduced SRH lifetimes. The agreement between simulated and measured current
gain (Fig. 2-7) is excellent. The range of high collector currents Ic are importantfor ESD device simulation. Nevertheless, the obtained calibration on base of
relation 2-1 requires some further comments. Fig. 2-8 summarizes the different
contributions to the total lifetime as a function of the carrier concentration for
this specific calibration result:
1. Due to the reduced lifetime as a consequence of SRH recombination, thecontribution of the Auger recombination is only remarkable above carrier
densities of 2-10 cm".
Therefore it is irrelevant, if one takes into account an
enhanced Auger process due to many body effects [Hcker94] or not (kink in
characteristic for raug at 3-10 cm" ). Furthermore, there is no significant
difference, if TAA-recombination is considered in the simulation. As
demonstrated by Schenk for a Smart-Power Technology, the calibration
result can be completely different for another process [Schenk99]. In the
particular case, Auger- and Trap-Assisted-Auger recombination played a
much more important part.
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2.4 Calibration of the Device Simulator
2. Since spatial information is missing in Eq. 2-1, the calibration based uponthis relation is rather an averaging over the entire device than a reasonable
local adjustment of the lifetime. This leads on the one hand to the observed
deviation between simulated and measured current gain in Fig. 2-7, and onthe other hand to the
consequence,that
the calibration is somehow devicedependent. It has to be checked, whether the same universal and "averaging"function with the same values for the parameters as used for the ggNMOS is
applicable for far more complex structures like thyristors that show
additional regions of remarkable carrier recombination (e. g. well, substrate).There is a new and quite promising approach to overcome the difficulties in
modeling SRH-recombination that takes into account a position-dependentlifetime [Vobecky96]. The method has recently been used for powersemiconductor devices that have been irradiated by high energy particles.This is to locally control the lifetime in the depth of the structure in order to
optimize its electrical behavior in view of a specific application.
3*
1E14 1E16 1E18 1E20excess carrier density (cm" )
Figure 2-8: Final result (grey shaded area) for the calibration of the overall
lifetime applicable for the simulation of the nBETA device in a 0.35 jumtechnology. The total lifetime is the result of different recombination
mechanisms, consisting of Auger (Aug), Trap-Assisted-Auger (TAA) andrecombination via deep traps (SRH). For the particular device, the influence ofTAA recombination is almost negligible, even at highest carrier densities
(arrow).
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ESD Protection Elements and Calibration of the Device Simulator
2.4.2 Simulator Specific Adjustments
The protection element inevitably heats up during an electrostatic discharge.As shown in Chapter 4, the device temperature is one of the crucial parameters
limiting the robustness ofa
protectionelement
againstESD. To
guaranteea
reasonable description of the element in a device simulator under high current
conditions, the parameters of the different models have to incorporate
temperature dependence. The scope of this section is to check the standard
device simulation models of mobility and impact ionization especially with
regard to their implementation of temperature dependence.
Mobility:
The different contributions to the mobility were checked separately based uponmeasured 0.35 urn process NMOS characteristics. The temperature dependencefor bulk and surface mobility have been verified using a drain voltage
Vds = 0.1 V which is much smaller than the signal voltage. For this bias scheme,
the effect of carrier velocity saturation can be neglected. The measured and
simulated characteristics are in good agreement for the investigated temperature
range from 300 K to 400 K; they require only a slight adjustment. In
[Stricker98], the verification has been carried out for even higher temperaturevalues. Next Vds has been increased to Vsig = 3.3 V to investigate the temperature
dependence of the high field saturation. Parameters taken from [Canali75]
perfectly reflect the experimental data (Fig. 2-9).
50
40
30
E
;-; 20
10
o0 12 3
V (V)gs
x '
Figure 2-9: Verification of the simulation modelfor the temperature dependentcarrier velocity saturation using measured NMOS transfer characteristics.
I
1NMOS: V, = 3.3
Measurer
v,vte=ovnent
n
ok Jr mf
30
Vw? 400 K
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2.4 Calibration of the Device Simulator
Impact Ionization:
The breakdown voltage Vbd of the ggNMOS transistor in a 0.35 urn technologyis caused by impact ionization. Impact ionization or avalanche generation is afundamental charge generation mechanisms and has to be explicitly specified inthe device simulator.
According to the so-called "Lucky-Electron-Model" [Shockley61] the
ionization rate a is governed by an initiating carrier that has to be accelerated
over a mean free path / in an electric field E to gain a certain threshold energy Etthat enables it to generate an electron-hole pair,
a exp(ZEL
qlE
\
(2-2)
As long as the variation of the electric field E over the avalanche region issmooth enough, the use of such a local avalanche generation model is justified.Classically, a minimum threshold energy of 1.5 times the bandgap Eg can bederived for the threshold energy Et [Sze81] however, experimentally determinedvalues are very different [Maes90]. The most commonly used relation for
modeling avalanche generation is related to the expression derived for the
Lucky-electron-model (2-2). It is the empirical relation of [Chynoweth58]
an,P=an,PexP'-b.An,p
(2-3)
The ionization parameters a~
and bnp have been experimentally determined
in [Overstraeten70]. Fig. 2-10 shows the reverse characteristic of the ggNMOSin a 0.35 urn technology showing relation (2-3) in comparison with
measurements. At about 9V, the reverse characteristic reveals a sudden increase
in the current indicating the electrical breakdown of the structure. The measuredbreakdown voltage Vbd of 9 V is read from the IV curve at the
arbitrarilychosen
current level of 1 nA/um and is reproduced quite well by the device simulation.
However, there is a transition regime between 6 V and 8.5 V that can only be
modeled, if additional tunneling effects are taken into account. Since the dopingconcentrations as well as the abruptness of the /-junctions of modern
technologies steadily increases, these effects are becoming a critical issue for thesimulation of the breakdown voltage (see Fig. 2-11). Within [PARASITICS00]it has been shown that tunneling has no influence on modeling the sustainingpoint or even the high current characteristic, so it can be omitted for these kindsof calculations.
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ESD Protection Elements and Calibration of the Device Simulator
1x10-7
1x10s
f1x10
11
slg
! i i
i
i'
! '1
measurement
simulation, wo. tunneling- simulation, w. tunneling /
r
1! // J
i. > .
i, i
> 4
c
ll v.. on
8 E10
Figure 2-10: Measured and simulated reverse IV characteristic for the
ggNMOS in the 0.35 jum technology showing avalanche breakdown. The
breakdown voltage Vbd is extracted at a current value ofl nA/jum.
- measurement
sim. w/o tunneling- - sim. tunneling
1x10
f1x1011
vi 00ds
Figure 2-11: Breakdown characteristics of a ggNMOS in two different CMOS
technologies. Tunneling plays an important role in the breakdown regime ofa
0.18 jum technology, while the IV characteristic is only slightly affected by
tunneling processes in a 0.35 jum technology.
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2.4 Calibration of the Device Simulator
The rate of impact ionization depends on the local temperature. In the Lucky-Electron Model (2-2), two effects are considered:
1. The threshold energy E{ to generate an electron-hole pair depends uponthe
bandgap Egof the semiconductor. This
bandgapshrinks with
risingtemperature resulting in an increased probability of ionization.
2. The mean free path / of an initiating carrier depends upon the scatteringrate of optical phonons. The higher the temperature, the more optical
phonons exist and the average energy gain of the accelerated carrier is
smaller, which leads to a reduced ionization probability.
In summary, both mechanisms show opposite dependence with respect to the
temperature. Many device simulators make use of both effects in the descriptionof the impact ionization model. On the one hand, the mean free path is modeled
as being proportional to the statistical occupation level of optical phonons[Crowell66]
/(r)oe tanh(tim \
op
V2V,(2-4)
In (2-4) the parameter ti(Oop represents the energy of the optical phonon. Since
the dispersion relation of optical phonons is nearly flat, this justifies thesimplification of considering only one energy level hcoop. On the other hand, thethreshold energy is linked to the temperature dependent bandgap Eg
E,{T)ocEg(Ty (2-5)
The reverse biased characteristics of the ggNMOS transistor in a 0.35 urn
process technology was examined in the temperature range from 293 Kto 594 K
(Fig. 2-12). Since the leakage current rises drastically with temperature, the
current level for extracting Vbd has to be increased to 1 uA/um. The breakdownvoltage is increasing with temperature, leading to an overall positive
temperature coefficient dVbd/dT of 4.4 mV/K for the breakdown voltage Vbd
(Fig. 2-13). A model considering only the temperature dependent mean free path/ leads to a strong overestimation (10 mV/K) in dVbd/dT. This is improvedslightly by further taking into account the temperature dependent bandgap whichreduces the deviation to 7 mV/K. As demonstrated in [Esmark99], the use of a
false temperature dependency in the avalanche rate is the main reason why thesimulated high current characteristic is strongly deviating from measured data.The
origin forthe
deviation observed here is the too much simplified model, asin reality, the temperature dependence for the scattering rates of carriers againstoptical and acoustic phonons is much more complicated.
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ESD Protection Elements and Calibration of the Device Simulator
T II
K*(V)ds
293K
594K
12
Figure 2-12: Measured reverse biased characteristic of the ggNMOS in a
0.35 jum technology for different ambient temperatures. Each curve is a 20 K
device temperature increase starting from room temperature. The breakdown
voltage extracted at 1 {lA/jum increases steadily at a rate of 4.4 mV/K.
2
simulation
incl. /(T)
incl. /(T), Eft)
adjusted function
300 350 400 450 500 550 600
7(K)
Figure 2-13: Compilation of the simulated breakdown voltage for the ggNMOSin a 0.35
fim technologyat
different temperatures.Several corrections have to
be made in the simulation model for impact ionization to reproduce the
measured data.
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2.4 Calibration of the Device Simulator
In [Valdinoci99] this problem is successfully overcome by calculating the
coefficient for impact ionization temperature dependence via a Boltzmann
solver. These results are then approximated by means of an analytical model,which in turn is used in the device simulator. Another effective workaround,
comparableto the
techniqueabove is to use a new
temperature dependentfunction in the rate of impact ionization and adjust it to measured values. By
fitting the dependency, it is possible to reproduce the experimentally determined
value of 4.4 mV/K for dVbd/dT (Fig. 2-13). This workaround is of course only
applicable, if the same function can be used regardless of the investigated
technology. Indeed, this has been verified within [PARASITICSOO] for several
+/?-junctions in a CMOS and a Smart Power Technology (SPT) as shown in
Fig. 2-14. Although the absolute value and the temperature dependence of the
breakdown voltage are completely different, the same fit can be applied.
1.25
1 1.15ii
.3^ 1.10
1.05
1.00
1 1 1 1 1
measurement n*p:0.35 urn techn.
smart power techn.
'
simulation: _
'
adjusted function adjusted function
"""
. '
jm'
'
.
1>^%
300 350 400 450 500 550 600
7(K)
Figure 2-14: Modeling of the temperature dependent breakdown voltage in aSPT and in a CMOS technology. Due to the different Vbd (approximately 10 V
for CMOS and 40 Vfor SPT), the breakdown voltage has been normalized to itsvalue at room temperature. For a reproduction ofdVbd/dT in both technologies,the same temperature dependentfunction was used.
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ESD Protection Elements and Calibration of the Device Simulator
2.4.3 Device Simulation Mesh and Boundary Conditions
Beside the specification of the physical models, another focus for the ESD
device simulation is the choice of an appropriate mesh and the definition of
suitableboundary
conditions. It isnecessary
to
set-upelectrical and thermal
boundary conditions and to choose a proper size for the finite simulation
domain. No simulation specific artificial distribution (e. g. for carrier density or
temperature) can be allowed to appear at any time and at any boundary of the
structure that could falsify the calculated results. Of course, this is in direct
conflict with the attempt to keep the simulation area and grid as small and coarse
as possible to save computation time. Therefore one is always forced to trade off
between numerical effort and accuracy. Table 2-4 summarizes the computational
effort for some typical problems, that are discussed in this thesis.
Problem# of Grid
Points
Typical
Computationtime
2-D, electrical simulation of
breakdown, DC2000-4000 5- 10 min.
2-D, electro-thermal simulation of
a TL pulse, transient2000 - 5000 0.5 - 3 hours
3-D,electro-thermal simulation of
a TL pulse, transient20000
- 35000 1-5 days
Table 2-4: Computation times of some typical simulation problems for a
workstation with a 500 MHz processor.
Both, electrical and thermal boundary conditions are examined more closely in
the following paragraphs.
Electrical boundary conditions:
In addition to the choice of a proper size for the simulation domain, another
problem concerns the integration of the ESD protection element DUT4 into an
ESD test environment (HBM/TLP/etc, see Fig. 2-15). The discharge waveforms
for the HBM and TLP stress can be reproduced by means of an electrical
network. In addition to this electrical network, the DUT connection to this
network has to be defined. In the case of the ggNMOS transistor, the gate,
source, and well contacts are connected together and tied to ground
(Fig. 2-15 a). Depending on the ESD stress, the drain contact is connected to one
of the following electrical networks:
4device under test
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2.4 Calibration of the Device Simulator
i b)TLP to DUT
! r"*
t1
! c)HBM c
! ESD-
L, HhmmL^_
Rhb=
tv C2 =| VESD 2
toDUl
Figure 2-15: a) Schematic for the integration of the ggNMOS transistor as a
DUT into different test environments. The parasitic bipolar transistor has been
indicated. The cutline is used to estimate the necessary depth of the simulationdomain. The electrical network according to different ESD stresses: b) TLP, c)HBM.
TLP: The electrical network for rectangular stress pulses is a simple time-
dependent current source. The pulse width (100 ns - 1 lis) and rise time
(default: 1 ns) correspond to the experimental condition (Fig. 2-15 b).
HBM: For HBM discharges, the resulting waveform can be modeled bymeans of an electrical network (CESd, Rhb in Fig. 2-15 c). The shape of the
pulse is determined in the ESD association standard [ESD98], but due to
tester parasitics the discharge waveform can slightly vary from tester to
tester. To take into account the influence of these parasitics, the lumpedelement model for the HBM tester has been extended by C], C2 and Lj. In
[Verhaege93] these parameters have been extracted for severalcommercial HBM testers.
The simulation domain has to be chosen sufficiently large to avoid any kind
of unphysical influence due to the boundaries. In the particular case of the
ggNMOS transistor, the depth of the simulation area is of special interest. For all
investigated technologies described here, the ggNMOS has been realized in abulk /^-substrate. Due to this configuration, carriers that have been injectedduring an ESD event into the /^-substrate, can deeply diffuse into the substratebefore
theyrecombine. There is no further barrier in the form of
a/w-junctionor
buried layer that can stop the penetration of these carriers.
a) ggNMOS (= DUT)
to electrical network
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ESD Protection Elements and Calibration of the Device Simulator
proposed depth for simulation of ggNMOS
-tf-r
1 10 20 30
Distance from Si-Si02 interface (urn)
Figure 2-16: Doping concentration and plasma density for the ggNMOS alongthe cutline defined in Fig. 2-15a during a 150 ns rectangular current pulse. The
p-substrate is completely charge carrier modulated.
For a TL pulse of 150 ns the charge carrier density injected into the substrate
(Fig. 2-16) has been plotted along the cutline depicted in Fig. 2-15a. Regions,where the density of the plasma strongly exceeds the background dopingconcentration of the bulk result in a charge carrier modulation. Since the electric
field in the substrate is almost negligible, the motion of the carriers is
determined by diffusion. This causes an accumulation of the carriers at the
bottom of the simulation structure with elapsed time. The characteristic depth of
the penetration can be estimated by usingthe diffusion
length Lnp [Sze81]of the
carriers
kDTKp = 4DnJn,P With Dnp =^-K (2-6)
Values for carrier lifetime and mobility can be taken from a simulation test run.
In this case the diffusion length is in the range of 15-20 fim (see Fig. 2-16). As
long as the depth of the simulation area is comparable or larger than this value,
then an artificial crowding of carriers at the bottom of the simulation structurewill be avoided.
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2.4 Calibration of the Device Simulator
Thermal boundary conditions:
The power dissipated by the protection element during an ESD event leads to anincrease of the lattice temperature. This demands a self-consistent solution of the
equations including the drift-diffusion approach and the heat transfer
c V-tS?T = H. (2-7)dt
The parameters c, k, and H represent the specific heat, the thermal conductivity,and the locally generated heat respectively. In commercial tools, the generatedheat is assumed to consist of three contributions: Recombination, Joule, and
Thomson/Peltier heating. Higher terms including changes in the plasma densityare neglected. According to [Tornblad96], Joule heating plays the dominant role
as long as effects due to switching transients (changes in the plasma density) canbe neglected. Tornblad has only investigated transient turn-on and turn-off
processes with time constants in the ixs time regime. It needs further verificationthat the simplified relation for H in the device simulator is still valid, if
discharge waveforms with rise times of some nanoseconds are considered.
However, the duration of a rectangular current pulse (100 ns) is much longercompared to its rise time (1 ns), so the generated error due to plasma effects is a
priori only of second order.
To guarantee natural heat propagation inside the structure, the thermal
boundaries are derived in a similar manner to the electrical boundaries. The
counterpart to the diffusion length LiP is the thermal diffusion length. For silicon
it is about 3 um for At= 100 ns [FKE00]. Characteristic device dimensions
range from 0.1 urn to some 100 urn and the typical width of an ESD pulse is onthe order of some 100 ns. This leads to the fundamental conclusion that duringan ESD event no thermal equilibrium is established inside the structure. This
assumption is verified by BLI5 experiments (see also Appendix Al). A typicalresult from BLI is presented in Fig. 2-17. Here it is demonstrated that, simplyspeaking, the temperature distribution continuously increases during a 150 ns
rectangular pulse. The internal heat sources continuously radiate their energyinto the surrounding material giving rise to a steadily increasing temperature.This non-equilibrium condition can only be described by a transient simulation;a quasi-static simulation is not able to handle such a situation.
5Backside Laser Interferometry
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ESD Protection Elements and Calibration of the Device Simulator
length (urn)
Figure 2-17: Measuredphase shift ofa laser beam used as a local thermoprobe
for an ESD protection element at different times during a TL pulse of 150 ns
[EsmarkOOa] along the length of the device. Two distinct hot spots HRl and
HR2 are detected. With elapsed time, the temperature increases.
It is worthwhile to have a look at a cross-section of a real ggNMOS formodeling the thermal boundaries (Fig. 2-18). Beside the drain, source, and bulk
contacts and the position of the gate, the complete system of isolation- (IMOX)and interconnecting (metal 1,2) layers as well as contact holes and vias are
shown. In principle, all these different layers must be considered for the
definition of reasonable boundary conditions. Either directly by adding a finite
volume to the device simulation area and solving the heat equation with
adequate thermal material parameters or in a more abstract approach using the
thermal network shown in Fig. 2-19a. The thermal resistances Rtf, replacing e. g.
a metal connection to the
pador the surrounding material in lateral directions or
at the bottom of the structure are calculated on the basis of the results presentedin [Schtz82]. Currently commercial device simulators do not support the
definition of thermal capacitances Cth. The reason might be that thermal
capacitances were not needed for conventional thermal simulation problems, as
they were always close to the equilibrium case. Therefore, the decision, in which
cases regions/materials can be reduced to a thermal resistance and when
explicitly an additional finite simulation volume is necessary is done on a
comparison between parameters pulse length, thermal capacitance, and thermal
resistance.
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2.4 Calibration of the Device Simulator
metal 2
contact hole
Figure 2-18: SEM picture of a ggNMOS designed in a 0.35 jum technology.
a) b) 300 K
contact hole
thermode (e g 300 K)ISV
VRth metal T
poly gate
/ bulkCfh lateral spacing 3 um
IMOX
surface of simulation area
* E
a.
cu
T3
c
g
ra
3
E
300 K7 ///[, drift diffusion + heat equation
heat equation
Figure 2-19: (a) Thermal network to terminate the simulation area with suitable
boundary conditions. In principle thermal capacitance Ctt, and resistance Rthcan reflect the thermal influence of the surrounding material in an abstract waybut unfortunately a definition of a Cth is not supported by the software, (b) Final
definition of the thermal boundary conditions by means of thermodes (300 K)and thermal resistances Rthfar the ggNMOS. The depth of the simulation area of15 jum is prescribed here by the electrical boundary conditions, while a lateral
spacing of3 jum is necessary due to thermal boundary conditions
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ESD Protection Elements and Calibration of the Device Simulator
In the case of the metal connection to the pad, it is sufficient to work with athermal resistance, in case of the silicon or the vicinity of a heat source, one
definitely has to use an extended volume, to solve the heat propagation more
exactly. The final definition of thermal boundary conditions of the ggNMOS isshown in
Fig.2-19b.
Figure 2-20: Temperature distribution in a ggNMOS 150 ns after the beginningof a TL pulse of 8 mA/jum. The isothermal lines are plotted with a spacing of15 K.
A typical temperature distribution for the ggNMOS for a TL pulse of8 mA/um is shown in Fig. 2-20. The hot spot, which is located at the gate edgeof the drain diffusion has a temperature of about 600 K after 150 ns and radiates
energy isotropically in all directions. Due to the reduced thermal conductivity ofthe IMOX, the isothermal lines are much closer compared to the underlyingsilicon. The excellent heat conduction across the contact hole becomes visible.
In general, it is sufficient to model the vicinity of the hot spots (in this case the
poly gate) carefully and to consider all areas and layers in a schematic way.
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Chapter 3
ESD Device Simulation:
I)Verification and First
ApplicationsThe following two Chapters focus on the realization of ESD device simulation
and the interpretation of their results. Chapter 3 deals with the verification of
simulated electrical and thermal parameters of an ESD protection element under
high current conditions. Good agreement between simulated and measured IV
characteristics is the prerequisite to estimate ESD failure thresholds of the
protection elements based on device simulation, which is the subject of
Chapter 4.
3.1 Electrical Parameters in the Snap Back and High Current
Regime
The reliability of device simulation must be tested with respect to the
reproduction of measured electrical parameters in the high current regime. A
complete list of the relevant parameters is given in Table 2-1. Obviously, the
electrical characteristic depends on the type of protection element. Beyond that,the design of the protection element and the process technology determine the
electrical parameters as well. The ggNMOS transistor is chosen here as the test
vehicle. Basic device dimensions of this particular element are the gate length lg,the drain and source contact to gate spacing DCG, SCG, respectively and the
width W(see also Fig. 2-5). The ggNMOS has been processed in a 0.35 urn and
a 0.18 urn technology. It required verification, such that influences arising from
the technology as well as the design of the structure are correctly reflected in the
calculated results with a satisfactory accuracy. This is the fundamental basis to
make use of ESD device simulation as a predictive tool. First of all a "reference"
ggNMOS transistor is defined in both technologies to study layout variations.The device has the following dimensions in each process technology:
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ESD Device Simulation: I) Verification and First Applications
Tech. DCG SCG /, W
0.35 urn 4.8 urn 0.66 urn 0.35 urn 100 urn
0.18 urn 5 urn 1 urn 0.18 urn 100 urn
Table 3-1: Layout dimensions of the reference ggNMOS in a 0.35 jum and a0.18 jum process technologies. The assignment of the different design
parameters to the layout of the device can be taken from Fig. 2.5.
The measured IV characteristic for the reference device in the 0.35 urn
technology is shown in Fig. 3-1. The electrical breakdown of the structure,
starting around 9 V, has been extensively discussed in Chapter 2.4.2. For
currents in the range between 0.01 mA/um and 0.1 mA/um the slope of the
IV characteristic changes significantly. At this point the voltage drop across the
substrate resistance is no longer negligible compared to the voltage drop across
the reverse biased drain to substrate junction. The voltage drop across the
substrate finally triggers the parasitic bipolar transistor by sufficiently forward-
biasing the base-emitter junction of the NMOS transistor.
10
n
:
0.1 r~- - - - - ......7
dl t -;
E 1E-3a.
:
%1E-5
,
. nr*rri measurement :
1E-7
\__
:
ii ;
tl
6 >* 8
ds
10 s? 12
Figure 3-1: Experimentally obtained IV characteristics for the ggNMOStransistor in a 0.35 jum process technology. The parasitic bipolar transistor is
triggered at a current Iti indicated by the snap back in the characteristics to a
sustaining point Vsp. For even higher current values, the device shows a
differential resistance Rdjff.
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3.1 Electrical Parameters in the Snap Back and High Current Regime
The 0.35 urn technology parasitic bipolar transistor is activated by a trigger
voltage Vti ~ 11 V and trigger current Itl =0.13 mA/um. The device snaps back
to a sustaining point Vsp of approximately 7 V straight after the trigger condition
is met. For nearly two decades in the current, the characteristic shows an almost
vertical branch. For currents above 5 mA/um the voltage drop across the deviceincreases again, giving rise to a differential resistance Rdlg. The characteristic
shown in Fig. 3-1 is the result of a combined experiment, consisting of a DC and
a pulsed measurement. For currents below the trigger point of the parasitic
bipolar transistor, thermal effects can be neglected, which enables a DC
characterization. For higher currents, the power dissipation inside the device
increases remarkably leading to a strong increase of the local temperature. This
is confirmed by the results of a simple 2-D device simulation. The evaluation in
Fig. 3-2 shows the simulated breakdown and snap back characteristic added bythe maximum temperature inside the device calculated for each point of the
characteristic.
Figure 3-2: 3-D representation of a device simulated IV characteristic for