dft_2006.06_sg_00_intro

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DFT Compiler 12006.06Synopsys Customer Education Services2006 Synopsys, Inc. All Rights Reserved Synopsys 30-I-011-SSG-009

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Facilities

Building Hours

Restrooms

Meals

Messages

Smoking

Recycling

Phones

Emergency EXIT

Please turn off cell phones and pagers

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Workshop Prerequisites

You should have experience in the following areas:

Digital IC design

Verilog or VHDL

UNIX and X-Windows A Unix based text editor

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The Power of Tcl3 workshops

at 3 skill levels


at 3 skill levels

Curriculum Flow

Design Compiler 1

PrimeTime:Debugging Constraints

Physical Compiler 1

DFT Compiler 1

PrimeTime 1

PrimeTime:

Signal Integrity

ATPG with TetraMAX

Astro 1 Astro XTalk


at 3 skill levels

IC Compiler 1

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Target Audience

SoC Design and Test engineers who need

to identify and fix DFT violations in their

RTL or gate-level designs, insert scan into

multi-million gate SoCs, and export designfiles to ATPG and P&R tools.

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Introductions

Name

Company

Job Responsibilities

EDA Experience

Main Goal(s) and Expectations for this Course

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Galaxy Design Platform

Design Services

Physical CompilerIC Compiler, Astro

JupiterXT

Star-RCXT

Hercules

Proteus

PrimeTimeSI

Power

Compiler

DFT

Compiler

Module

Compiler

Design Compiler

Design-

Ware

Milkyway

Test SynthesisDFT Compiler, DBIST, DFT MAX

Unif ied DFT syn thesis , veri f icat ion and

test signof fSigni f icant test cost reduc t ion

ATPGTetraMAXATPG, DSMTest, TenX

Leading-edge ATPG with com prehensivesupp ort for delay related d efects

Synopsys Manufactur ing Test Solut ion

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1-Pass Test Suite: Environment Overv iew

TetraMAX Environment

RTL Source

Boundary

Scan NetlistBSDL Test Vectors

Design Compiler/Physical Compiler Environment

DFT Compiler1-Pass Test Synthesis

Setup Info

STIL File

Scan Design

(Gates)

TetraMAX ATPGSequential Fault Simulator

Bridging Faults

IDDQ

Transition Delay

Path Delay

BSD CompilerIEEE-1149.1

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DFT Compiler TM 1-Pass Scan Synth esis

RTL Rule Checking: In-depth testability analysis

at RT Level:

Helps designers write test-friendly RTL

AutoFix: Automatic correction of scan DRC violations:

Removes unpredictability from back-end design process

DFT synthesis

Scan Synthesis: Transparent scan implementation:

Seamlessly optimize all design constraints timing, area, power

and test (logicalandphysicaldomain)

Hierarchical Scan Synthesis:Leverage existing flows

and test models to gain multi-million gate capacity and

improved performance (logicaland physica ldomain)

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Test-Ready Flow

Scan-inserted

Design

TestabilityReports

RTL

Source

DFT CompilerDFT synthesis, test drc, test

coverage preview

DFT Compiler Test-Ready or Unmapped Flow

Start point is RTL(unmapped) design

IDEALstarting point

1-Pass Scan synthesisachieved by taking RTL

directly to a scan

synthesized design

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Exist ing Scan Flow

Scan-insertedDesign

Testability

Reports

Gate-Level

Source

DFT CompilerDFT synthesis, test drc, testcoverage preview

DFT Compiler Existing Scan Flow

Start point is gate-leveldesign that already

includes scan cells and

chains

DFT Compiler performsscan chain extraction&

test DRCs in

preparation for

TetraMAX ATPG

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Bottom-Up Scan Insertion Flow

DFT Check

Specify Scan Paths

Preview

Coverage

Insert Scan Paths

Read Block and

Test Protocol Violations?

Violations?

Handoff Block

Block

DFT FlowRTL DFT Flow

DFT Check

Specify Scan Paths

Preview

Coverage

Insert Scan Paths

Read Block and

Test ProtocolViolations?

Violations?

Handoff Block

Block

DFT Flow

RTL DFT Flow

Top-Level DFT

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Methods for High Capacity Scan Synthesis

Unified Design Rule Checking

(UDRC):

Uses TetraMAX DRC forconsistency and faster runtime

Rapid Scan Synthesis (RSS):

Avoids test uniquification andjust stitches the scan chains

Test Models, Interface Logic

Models (ILMs) with Test Models:

Highly reduced scan models of

gate-level designs

XG Mode

New infrastructure increasescapacity and reduces runtime

DFT Compiler

UDRCRSS

Test Models

ILMs

DC

DC-XG

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Workshop Goal

Use DFT Compiler to check RTL and mapped

designs for DFT violations, insert scan chainsinto very large multi-million gate designs in

either logical or physical flows, and export all

the required files for downstream tools.

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Agenda

Understanding Scan Testing1

DFTC User Interfaces2

DFT for Clocks and Resets4

Creating Test Protocols3

DAY

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Agenda

DFT for Buses/Tristates5

Top-Down Scan Insertion6

Exporting Design Files7

DAY

2

High Capacity DFT Flows8

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Workshop Objectives: Day 2

How to fix Internal/External Buses for DFT

Insert scan to achieve well-balancedtop-level scanchainsand other scan design requirements

Write a scriptto perform all the stepsin the DFT flow,

including exporting all the required files for ATPG and

Place & Route

Customizethe test initializationsequence, if needed

Modify a bottom-up scan insertionscript for full

gate-level designs to use Test Models/ILMs with RSS

and run it

Preview top-level chain balance using test

models/ILMs after block level scan insertion and

revise block level scan architecture as needed to

improve top-level scan chain balance

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Agenda

DFT MAX10

Conclusion12

Customer SupportCS

DAY

3 New Features9

Clock Gating11

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Workshop Objectives: Day 3

Overview of new features in 2005.09 and 2006.06XG mode

Introduction to DFT MAX

DFT Power Compiler interoperability

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Lab Exercise Caution

RecommendationDefinition of

Acronyms

For Further Reference

Under the Hood

InformationGroup Exercise

Question

Icons Used in this Workshop

!

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Test Automation Docs are on SolvNet!

https://solvnet.synopsys.com/dow_retrieve/Y-2006.06/ni/test.html

Documentation on the Web:https://solvnet.synopsys.com/dow_search

dft_2006.06_sg_00_intro

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