dft_2006.06_sg_01_scanbasics

8/11/2019 DFT_2006.06_SG_01_scanbasics

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Agenda

2006 Synopsys, Inc. All Rights ReservedSynopsys 30-I-011-SSG-009

Understanding Scan Testing1

DFTC User Interfaces2

DFT for Clocks and Resets4

Creating Test Protocols3

DAY

DAY


2/40

21-

Unit O!ecti"es

After co#$leting t%is &nit' (o& s%o&ld e ale to)

*+$lain %o, to &se t%e D algorit%# to generate

a $attern t%at detects a gi"en st&ck-at fa&lt in aco#inational design

Do t%e sa#e in a f&ll scan se&ential design

.all of t%e fli$-flo$s are scan co#$liant' no

#e#or(' no latc%es/ *+$lain ,%( scan-c%ainsare necessar( to

s&$$ort ATP0


3/40

31-

Unit 1 Road#a$

What is Design for

Manufactuing

Test?

D Algorithm as

applied to purely

combinational

logic

Lab 1

D Algorithm as

applied to

sequential logic

(Full can!


4/40

41-

"ac#aged

$% %hips

Test"rogram

STIL 1.0;

AT&

Fail

Pass

%at is an&fact&ring Test

"ass'Fail Testing


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1-

Physical Defect:

A on-chip fla,introdced dring !"#ric"tion or p"c$"ging

o! "n individ"l ASI% th"t &"$es the device #alf&nction.

Co##on

P%(sical

Defects

hort

%ircuit

Transistor

Alays )*

)pen

%ircuit

%at Is a P%(sical Defect

)+ide

"inholes


6/40

51-

) u t p u t h o r t e d

t o L o g i c 1

" u l l , D o ( nT r a n s i s t o rA l ( a y s ) *

I N O U T

G R O U N D

P O W E R

$ n p u t) p e n

P%(sical Defects in COS

T%is $%(sical "ie, of a COS in"erter %as se"eral defects6


7/4071-

St&ck-At Fa&lt odel

Fault Model:A logical#odel re$resenting t%e effectsof a $%(sical defect8

SA1 Fault:

D&e to a defect' in$&t $inAof U0acts as if st&ck %ig%'inde$endent of in$&t signal8

SA0 Fault:

D&e to defect' o&t$&t $in Yof U1acts as if st&ck lo,'inde$endent of t%e in$&ts8


8/4091-

Rules of the Game:

'ester "ccess to the device-nder-test ()*'+

is onl( "lloedthrogh its $ri#ar(I ports.

R&les for Detecting a SAF

Internal Proingof IC Too Costl(6

Internal Proingof IC Too Costl(6


9/40:1-

Unit 1 Road#a$

What is Design for

Manufactuing

Test?

D Algorithm as

applied to purely

combinational

logic

Lab 1

D Algorithm as

applied to

sequential logic

(Full can!


10/401;1-

Else SA0 fault ispresent,and U1/Yremains at -.Else SA0 fault ispresent,and U1/Yremains at -.

T%is if


11/40111-

D A l g o r i t h m .

1 / T a r g e t a s p e c i c s t u c ! a t f a u l t .

0 / " r i v e f a u l t s i t e t o o p p o s i t e v a l u e .

( c o n t i n u e d )

Acti"ate t%e SA; Fa&lt .1et,ork 1

In$&t

Sti#&l&s

1' -

Fault,Free

Faulty alue

Legend


12/40121-




2 / " r o p a g a t e e r r o r t o p r i m a r # o u t p u t .

( c o n t i n u e d )

Pro$agate Fa&lt *ffect .2


13/40131-

Anato#( of a Test Pattern .3


14/40141-




2 / " r o p a g a t e e r r o r t o p r i m a r # o u t p u t .

5 / 4 e c o r d p a t t e r n $ d r o p d e t e c t e d f a u l t .

Record t%e Test Pattern .4


15/4011-

Assess#ent of D Algorit%#

Ad"antages)

Deter#inisticste$-(-ste$ #et%od of detecting SAFs

*+%a&sti"e@s&cceeds &nless a fa&lt is &ndetectale

=i#itations)

0enerates a test for onest&ck-at fa&lt at a ti#e

In"ol"es decision #akingat al#ost e"er( ste$ a( acktracke+cessi"el( for %ard-to-test fa&lts


16/40151-

What To Do.%se the Dalgorithm to generate a test pattern b# hand to detect the

)ecord #our test pattern *both

stimulusand response+ at right.

*+ercise) Detect SA1 Fa&lt

V e c t o r { A L L = _ _ _ _ _ _ _ ; }


17/40171-

111

1

-

Sol&tion) Detect SA1 Fa&lt

Legend.

InputNis a dont!care *0or 1+.

-utput 'is dont!strobe *mas+.

N - (con6ict!

-

-'1

V e c t o r { A L L = ; }111N0'0


18/40191-

Nf

= 2 ( Np i n s

+ Np o r t s

)

= 2 ( 1 1 + 5 )

= 3 2

Total

Fa&lt

Co&nt

>et,ork 1

o, an( St&ck-At Fa&lts


19/401:1-

Eui!alent Faults:A set o! !"lts hose e!!ects c"nnot #e distingished"t the A' "re e&i"alent to one "nother. >otestp"ttern eists th"t c"n tell the& "p"rt.

*&i"alent Fa&lts .1et,ork 1

Fanout!free net.Fanout!free net.

U1/ASA& U1/Y

SA0.

U1/ASA& U1/YSA0.

ATP /ors left to right,thinning euivalent faults.

ATP /ors left to right,thinning euivalent faults.


20/402;1-

Nf

= 2 ( Ni n p u t s

+ 1 )

= 6

Nf

= ( Ni n p u t s

+ 2 )

= 4

After

Colla$sing

BeforeColla$sing

*&i"alent Fa&lts .2A>D in$&t SA; is identical tot%eo&t$&t SA1

T%e fa&lt set ASA;' $SA;' YSA1 is t%&s ane&i"alent set

Onl( oneof t%e e&i"alent fa&lts needs to e incl&ded

*+a#$le) YSA1


21/40211-

*&i"alent Fa&lts .3et,ork 1

Fault "olla#sin$:

y testing !or only one!"lt per e/iv"lence set, yo redce

(or colla$se+ the !"lt popl"tion. 'his &e"ns !eer p"tterns.

After collapsing,

onl#

7of 20faults left.

After collapsing,

onl#7of 20faults left.


22/40221-

*&i"alent Fa&lts .4


23/40231-

U 1

U

U /

U 0

$

Y

A1 ' -

Undetectale Fa&lts

To a"oid an o&t$&t glitc%' designer %as added gate U1.It does notalter t%e f&nction Y' and is t%&s red&ndant8

SinceU1

%as no effect' t%e SA; fa&lt is &ndetectale8

>et,ork 2

8ndetectableStuc!At Fault

8ndetectableStuc!At Fault

)edundantate U1

)edundantate U1

Fan!-utPresentFan!-utPresent


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Test and Fa&lt Co"erage For#&las

Test Co"erage EDT .PT G $tHcredit/

all fa&lts - .UD .AU G a&Hcredit//

Fa&lt Co"erage EDT .PT G $tHcredit/

all fa&lts

$tHcredit E ; ( defa&lt

a&Hcredit E ; ( defa&lt


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21-

U!co2&e) St%c3 4%t S%55r6 Re2ort

(((((((((((((((((((((((((((((((((((((((((((((((

7%t c&& co)e 87%t&

(((((((((((((((((((((((((((((( (((( (((((((((

Detecte) DT 19:9

Po&&*


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251-

Test Esca#es:

"rts th"t $assevery test,

#t still h"ve &ndetected

de!ects th"t re"ch sers4

Is ig% Co"erage >eeded

Defect %e!el:

'he fractiono! test esc"pes, in

de!ective p"rts per &illion (DP+.


27/40

271-

ig% Co"erage Is =o, DP

Jo& need %ig% fa&lt co"erageto kee$ defect le"els lo,6

Process

Jield

;

1;;;;

2;;;;

3;;;;

4;;;;

;;;;

5;;;;

7;;;;

9;;;;

1;;I :9I :5I :4I :2I :;I

Fault %o3erage

Defecti"e

Parts $er

illion

;I

5;I

7;I9;I

:;I

Escapes0.&2

Escapes0.&2

Defect =e"el"ers&s

Fa&lt Co"erage


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D8T )ne or *oneFaults Present

)ne or *oneFaults Present

T%e Single

St&ck-At Fa&lt

Ass$tion

Single SAF Ass$tion .SSAF/

T%ere is a $ossiilit( t%at #&lti$le fa&lts in t%e ASICcan #ask o&tfa&lts tested &sing t%e SSAF ass$tion

T%e likeli%ood of si#&ltaneo&sSAFs is ignored

Testing for #&lti$le SAFsis too ti#e consing

T%e SSAF ass$tion is one $ossile reason for test

esca$es


29/40

2:1-

Unit 1 Road#a$

What is Design for

Manufactuing

Test?

D Algorithm as

applied to purely

combinational

logic

Lab 1

D Algorithm as

applied to

sequential logic

(Full can!

S


30/40

3;1-

Testing Se&ential Designs

Jo& still need to acti"atet%e fa&lt and $ro$agateits effect8Re$laceeac% flo$ ,it% a testale fli$-flo$8T%is re$lace#ent allo,s serialloadinget,ork 1

TargetFa&lt

Pre-Scan

Design

S l * i l t Fli Fl


31/40

311-

Scannale*&i"alent!or rdin"ry) 5lip-5lop

&lti$le+edFli$-Flo$

Sc"n Style

Scannale *&i"alent Fli$-Flo$

T%e scan e&i"alent %as a serial $at%fro# $in SIto SO

T%is $at% is enaled onl(d&ring testing' ( asserting SE

SE

0

1/SOD

LF

SI

D

LF

T% F ll S St t


32/40

321-

9ou stitch together a serial path through all the scan 6ops:

enabling AT& to preload registers and capture responses;

9ou stitch together a serialpaththrough all the scan 6ops:

enabling AT& to preloadregisters and captureresponses;

T%e F&ll Scan Strateg(

Seriall( &nload fa&lt effect at PO

T%en ca$t&ret%efa&lt effect .1/0/

into t%isregister8

Seriall( $reloadregister,it% t%e sti#&l&s' &000.

S T ti P t l * l 1


33/40

331-

Scan Testing Protocol) *+a#$le 1

Scan S%ift Scan S%ift

Ca$t&re

S*

C=K

SI

SO

1; ; ; >e+t Test Pattern

Res&lts Fro# Pre"io&s Test Pattern 1

'est here !or

" SA !"lt

1' --

-

-

1

1' -

S*C=K

SI

SO

PI1

PI2

PI3

PI4

PO1

PO2

S T ti P t l * l 2


34/40

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Scan Testing Protocol) *+a#$le 2

Scan S%ift Scan S%ift

Ca$t&re

S*

C=K

PO1

SI ; >e+t Test Pattern

PI1

;

1

1' -

1' -

S*C=K

SI

SO

PI1

PI2

PI3

PI4

PO1

PO2

-

1

-' 1

Test a node in

t%is logic clo&d

for a SA1 fa&lt

T t P tt O l


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31-

/ / /

% a p t u r e

c a n h i f t

% a p t u r e

/ / /

Pattern n

Pattern (n 1)

O"erla$$ing C(cles

Test Patterns O"erla$

Scanning o&t of $re"io&s $attern o"erla$sscanning in of ne+t

@for all &t first and last $atterns in t%e test $rogra#8

S St t i S i d


36/40

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Scan Strategies S#ariLed

'est Str"tegy

>o ScanGG5ll Se/enti"l A'G

F&ll Scan%oin"tion"l A'G

Al#ost-F&ll Scan5"st-Se/enti"l A'G

ig%est Co"erage

ost Scan I#$act

=ess Scan I#$act

ig% Co"erage

=onger R&n Ti#e

=ongest R&n Ti#e

oderate Co"erage

S$ecial A$$lications

(e.g. r"d-h"rd logic+

U it 1 R d


37/40

371-

Unit 1 Road#a$

What is Design for

Manufactuing

Test?

D Algorithm as

applied to purely

combinational

logic

Lab 1

D Algorithm as

applied to

sequential logic

(Full can!

U it S


38/40

391-

Unit S#ar(

F&ll Scan Ad"antages)

>eeds onl( co#inationalATP0 .D Algorit%#/for testing all SAFs

Co#inational ATP0 gi"es s%orter ATP0 r&n ti#es

Predictale and a$$lies across #ost arc%itect&res

0i"es %ig%est fa&lt co"erage of all t%e algorit%#s

*asiest to i#$le#ent

F&ll Scan =i#itations)

Adds nonf&nctional $insto t%e $ackage

Ti#ing and densit( i#$actof scan-e&i"alent flo$s

>ot a$$licale to e#edded #e#or(' latc%es'

fli$-flo$s not incl&ded on t%e scan-c%ain

= 1 C l t Fl


39/40

3:1-

=a 1) Co#$lete Flo,

DFT C%eck

Test-Read( Co#$ile

Ti#ing' Area

Read RT= Design

Miolations3 Create Test Protocol

Constraints

2et3

DFT C%eck

S$ecif( Scan Pat%s

Pre"ie,

Co"erage

Insert Scan Pat%s

Read Design and

Test Protocol Miolations3

Miolations3

andoff Design

Un#a$$ed

DFT Flo,

2a$$ed

DFT Flo,Start

*nd

=a 1) Fro# Reading to andoff


40/40

=a 1) Fro# Reading to andoff

After co#$leting t%is la' (o& s%o&ld e ale to) Identif( t%e $ri#ar( ste$s in r&nning t%e tool

Identif( t%e $ri#ar( co##and for e"al&ating

tool transfor#ations

Find o&t t%e $&r$ose and s(nta+ of

co##ands and "ariales

3; #in&tes

dft_2006.06_sg_01_scanbasics

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