library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;

entity ALU isPort ( Clk : in STD_LOGIC; A : in std_logic_vector (3 downto 0); B : in std_logic_vector(3 downto 0); R : out std_logic_vector(3 downto 0); op: in std_logic_vector(3 downto 0); Nul : out boolean; Cout : out STD_LOGIC); Cin, x, y : IN STD_LOGIC; s, Cout : OUT STD_LOGIC;end ALU;

architecture behavioral of alu is type op_type is ( op_a_suma_b, op_a_resta_b , op_a_inc_uno , op_a_dec_uno , op_a_mul_b , op_a_div_b , op_a_comp_b , op_a_and_b, op_a_nand_b, op_a_or_b, op_a_nor_b,op_a_xor_b, op_a_nexor_b,op_not_a ,op_not_b , op_nsu);

BEGINs