digital circuit logic unit 12: registers and counters lecture slides/week... · shift register. 3....
TRANSCRIPT
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved. 1
DIGITAL CIRCUIT LOGIC UNIT 12: REGISTERS AND COUNTERS
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Learning Objectives
1. Explain the operation of registers. Show howto transfer data between registers using a tri-state bus.
2. Explain the operation of shift registers, showhow to build them using flip-flops, and analyzetheir operation. Construct a timing diagram for ashift register.
3. Explain the operation of binary counters,show how to build them using flip-flops andgates, and analyze their operation.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Learning Objectives
4. Given the present state and desired next stateof a flip-flop, determine the required flip-flopinputs.
5. Given the desired counting sequence for acounter, derive the flip-flop input equations.
6. Explain the procedures used for deriving flip-flop input equations.
7. Construct a timing diagram for a counter bytracing signals through the circuit.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
Introduction:
A register consists of a group of flip-flops witha common clock input. Registers are commonlyused to store and shift binary data.
A counter is usually constructed from two ormore flip-flops which change states in aprescribed sequence when input pulses arereceived.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
4-Bit D Flip-Flop Registers with Data, Load,Clear and Clock Inputs:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
4-Bit D Flip-Flop Registers with Data, Load,Clear and Clock Inputs (continued):
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
Data Transfer Between Registers:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
8-Bit Register with Tri-State Output:
Figure 12-3(a) shows an integrated circuit registerthat contains eight D flip-flops with tri-state buffers atthe flip-flop outputs.
These buffers are enabled when En = 0. A symbolfor this 8-bit register is shown in Figure 12-3(b).
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
Data Transfer Using a Tri-State Bus:
Operation is as follows:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
Parallel Adder with Accumulator:
It is frequently desirable to store one number in aregister of flip-flops (called an accumulator) and add asecond number to it, leaving the result stored in theaccumulator (e.g., in ALU). See figure 12-5 below:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Registers and Register Transfers
Adder Cell with Multiplexer:
Figure 12-6 shows a typical cell of the adder wherethe accumulator flip-flop can either be loaded directlyfrom yi or from the sum output (si).
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
Shift Registers:
A shift register is a register in which binary data canbe stored, and this data can be shifted to the left orright when a shift signal is applied.
Shifts can be linear or cyclic.
The figure on the next slide shows a 4-bit right-shift register with serial input and outputconstructed from D flip-flops.
When Shift=1, the clock is enabled and shiftingoccurs on the rising clock edge. When Shift=0, noshifting occurs and the data in the register isunchanged.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
Serial In/ Serial Out Registers:
Serial in means that data is shifted into thefirst flip-flop one bit at a time, and the flip-flopscannot be loaded in parallel.
Serial out means that data can only be readout of the last flip-flop and the outputs from theother flip-flops are not connected to terminals ofthe integrated circuit.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
Johnson Counter:
A circuit that cycles through a fixed sequence ofstates is called a counter.
A shift register with inverted feedback is called aJohnson counter or a twisted ring counter.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Shift Registers
General Form of a Shift Register Counter:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Synchronous and Ripple Counters:
For synchronous counters, the operation of the flip-flops is synchronized by a common clock pulse so thatwhen several flip-flops must change state, the statechanges occur simultaneously.
Ripple counters are those in which the statechange of one flip-flop triggers another flip-flop.These will not be focused on in this chapter.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Binary Counters Using 3 T Flip-Flops to Count ClockPulses:
We assume that all the flip-flops change state a shorttime following the rising edge of the input pulse.
The state of the counter is determined by the states ofthe individual flip-flops; for example, if flip-flop C is in state0, B in state 1, and A in state 1, the state of the counter is011.
Initially, assume that all flip-flops are set to the 0 state.When a clock pulse is received, the counter will change tostate 001; when a second pulse is received, the state willchange to 010, etc.
When 111 is reached, the counter resets to the 000 state.
See next slide for figure.21
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Design of Binary Counter Using Transition Tables:
This table shows the present state of flip-flops C, B, and A(before a clock pulse is received) and the corresponding nextstate (after the clock pulse is received).
A third column in the table is used to derive the inputs for TC,TB, and TA. Whenever the entries in the A and A+ columns differ,flip-flop A must change state and TA must be 1.
TC, TB, and TA are now derived from the table as functions ofC, B, and A.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Karnaugh Maps for Binary Counters:
Figure 12-15 shows the Karnaugh maps for TC and TB, from which TC = BA and TB = A. These equations yield the same circuit derived previously for Figure 12-14.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Binary Counter with D Flip-Flops:
We must convert each D flip-flop to a T flip-flop by addingan XOR (exclusive-OR) gate, as shown in Figure 11-28(b).Figure 12-16 shows the resulting counter circuit.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Up-Down Counter Transition Graph, Table and Logic Equations::
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Binary Up-Down Counter:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
Loadable Counter with Count Enable:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Design of Binary Counters
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
Counter for Other Sequences (Example):
We will design a counter for the transition tableshown in Table 12-3 using T Flip-Flops.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
Input for T Flip-Flop:
T=1 whenever a state of change is required.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
Procedure for Designing a Counter Using T Flip-Flops:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
Counter Design using D Flip-Flops:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
Binary Counter with Clear:
Counters and shift registers with clear, preset, orparallel load capability can also be used to generatenonbinary count cycles.
Consider a binary counter with a clear input asshown Figure 12-28.
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Synchronous Clear:
Asynchronous Clear:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counters for Other Sequences
Binary Counter with Parallel Load:
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The counter must cycle throughstates 3 to 12. The logic mustgenerate Ld when the counter isin state 12 and the parallel inputs must be 0011.
States 0,1,2,13,14,15 are don’t-cares.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Procedure for Counter Design Using S-R Flip-Flops:
Instead of deriving an input equation for each D or Tflip-flop, the S and R input equations must bederived.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Counter Using S-R Flip Flops:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Counter Using S-R Flip Flops (continued):
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Counter Using S-R Flip-Flops (continued):
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Procedure for Counter Design Using J-K Flip- Flops:
The procedure used to design a counter with J-K flip-flopsis very similar to that used for S-R flip-flops, except that Jand K can be 1 simultaneously, in which case the flip-flopchanges state.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
J-K Flip-Flop Table:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Counter Design Using J-K Flip-Flop:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Counter Design Using S-R and J-K Flip-Flops
Counter Design Using J-K Flip-Flop (continued):
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Derivation of Flip-Flop Input Equations- Summary
Summary:
The input equation for the flip-flops in a sequential circuitmay be derived from the next-state equations by using truthtables or by using Karnaugh maps.
For the D flip-flop, the input is the same as the next state.
For the T flip-flop, the input is 1 whenever a state change isrequired.
For the S-R flip-flop, S is 1 whenever the flip-flop mustbe set to 1 and R is 1 when it must be reset to 0.
For a J-K flip-flop, the J and K inputs are the same as S andR, respectively, except that when one input is 1 the otherinput is X.
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Derivation of Flip-Flop Input Equations- Summary
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Derivation of Flip-Flop Input Equations- Summary
Example 1:
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ECE 102 – Digital Circuit Logic
© Mahdi Nikdast - CSU, SP18. All Rights Reserved.
Derivation of Flip-Flop Input Equations- Summary
Example 1 (continued):
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