digital cmos circuits (ch. 15)bandi.chungbuk.ac.kr/~ysk/ckt15.pdf · rc vv τ μ == n −...

Digital CMOS Circuits (Ch. 15)g

김 영 석김 영 석

충북대학교 전자정보대학

2012.9.1.9.

Email: [email protected]

전자정보대학 김영석 15-1

Contents15.1 General Considerations

15.2 CMOS Inverter

15.3 CMOS NOR and NAND Gates


15.1 General Considerations 15.1.1 Inverter Characteristic

_X A=X A

An inverter outputs a logical “1” when the input is a logical “0” and vice versa.


Ex15.2 NMOS Inverter

11

onR W=1( )

on

n ox DD THWC V VL

μ −

The CS stage resembles a voltage divider between RD and Ron1 when M1 is in deep triode region. It produces VDD when M1 is off.


Transition Region Gain

Infinite Transition Region Gain Finite Transition Region Gain

Ideally, the VTC(Voltage Transfer Characteristics) of an inverter has infinite transition region gain. However, practically the gain is finitepractically the gain is finite.

Ex15.3:

Transition Region: 50 mV

Supply voltage: 1.8V

1.8 360.05vA = =


Ex15.4 Logical Level Degradation

5 25 125V A m mVΔ = × Ω =5 25 125V A m mVΔ = × Ω =

Since real power buses have losses, the power supply levels at two different locations will be different. This will result in logical level degradation.


Ex15.5/6 Small-Signal Gain of NMOS Inverter

Ex15.5 Small-Signal Gain Variation of NMOS Inverter: As it can be g s seen, the small-signal gain is the largest in the transition region.

Ex15.6 Above Unity Small-Signal Gain: The magnitude of the small-signal gain in the transition region can be above 1.


Noise Margin

Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1-1.


Ex15.7: NMOS Inverter Noise Margin

1L IL TH

n ox D

NM V VWC RL

μ= = +1:

( ) 21 22out DD n ox D in TH out out

WV V C R V V V VL

μ ⎡ ⎤= − − −⎣ ⎦

L

2 L

V VVin=VIH122

in THout

n ox D

V VV WC RL

μ

−= +

NM V V2 H DD IHNM V V= −2:


Ex15.8: Minimum Vout

19DR W=

( )n ox DD THWC V VL

μ −

To guarantee an output low level that is below 0.05VDD, RD is chosen above.


15.1.2 Dynamic Behavior of NMOS Inverter Gates

Since digital circuits operate with large signals andSince digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must resort to time-domain analysis to evaluate the speed of a gateanalysis to evaluate the speed of a gate.

It usually takes 3 time constants for the output to transition.


Rise/Fall Time and Delay


Ex15.10: Time Constant

( )219

D XDD TH

LR CV V

τμ

= =−( )n DD THV Vμ

Assuming a 5% degradation in output low level the timeAssuming a 5% degradation in output low level, the time constant at node X is shown above.


Ex15.1: Interconnect Capacitance

Wire Capacitance per Mircon: 50x10-18 F/µm

Total Interconnect Capacitance: 15000X50x10-18 =750 fF

Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, Cox =13.5fF/µm2


15.1.3 Power-Delay Product

2DD XPDP V C≈ DD X

The power delay product of an NMOS Inverter can be loosely p y p s y thought of as the amount of energy the gate uses in each switching event.


Ex15.12: Power-Delay Product

3PLH D XT R C≈

( )( )3

3PLH D X

DD DD D X

T R CPDP I V R C=

23 DD oxPDP V WLC=


15.2 CMOS InverterDrawbacks of the NMOS Inverter

Because of constant RD, NMOS inverter consumes static power even when there is no switchingeven when there is no switching.RD presents a tradeoff between speed and power dissipation.


Improved Inverter Topology

A better alternative would probably have been an “intelligent” pullup device that turns on when M1 is off and vice versa.


Improved Falltime

This i d i t t l d s s f llti si ll fThis improved inverter topology decreases falltime since all of the current from M1 is available to discharge the capacitor.


CMOS Inverter

A circuit realization of this improved inverter topology is the CMOS inverter shown above.

The NMOS/PMOS pair complement each other to produce the desired effects.


15.2.2 Voltage Transfer CharacteristicCMOS Inverter Small-Signal Model

( )( )||outv ( )( )1 2 1 2||outm m O O

in

v g g r rv

= − +

When both M1 and M2 are in saturation, the small-signal gain is shown above.


Switching Threshold

The switching threshold (Vi T) or the “trip point” of theThe switching threshold (VinT) or the trip point of the inverter is when Vout equals Vin.

If VinT =Vdd/2, then W2/W1=µn/µp


CMOS Inverter VTC


Ex15.15: VTC

W22

As the PMOS device is made stronger the VTC is shifted toAs the PMOS device is made stronger, the VTC is shifted to the right.


Noise Margins

( )1 2 1 22 dd TH TH dd TH THa V V V V aV VV

− − − −= −

NML =VIL

( ) 11 3ILVaa a

=−− +

VIL is the low-level input voltage t hi h (δV / δV ) 1

( )1 2 1 22 dd TH TH dd TH THa V V V V aV VV

− − − −=

at which (δVout/ δVin)=-1

NMH =Vdd-VIH ( ) 11 1 3IHVaa a

= −−− +

VIH is the high-level input voltage

nWL

μ ⎛ ⎞⎜ ⎟⎝ ⎠

at which (δVout/ δVin)=-1

1

2

n

p

LaWL

μ

μ

⎜ ⎟⎝ ⎠=⎛ ⎞⎜ ⎟⎝ ⎠2⎝ ⎠


VIL of a Symmetric VTC

( ) ( )( )1 12 2 3 1

1 3DD TH DD TH

ILa V V a V a V

Va a

− − + − +⎡ ⎤⎣ ⎦=− +( )

Symmetric VTC: a=1

13 18 4IL DD THV V V= +


Ex15.17 Noise Margins of an Ideal Symmetric VTC

2DD

H ideal L idealVNM NM= =, , 2H ideal L ideal


Ex15.18 Floating Output

1 / 2/ 2

TH DDV VV V

>

>2 / 2TH DDV V>

When Vin=VDD/2, M2 and M1 will both be off and the output floats.


15.2.3 Dynamic CharacteristicsCharging Dynamics of CMOS Inverter

As V is i iti ll h d hi h th h i is li si MAs Vout is initially charged high, the charging is linear since M2

is in saturation. However, as M2 enters triode region the charge rate becomes sublinear.


Charging Current Variation with Time

The current of M2 is initially constant as M2 is in saturation. However as M2 enters triode, its current decreases.However as M2 enters triode, its current decreases.


Size Variation Effect to Output Transition

As the PMOS size is increased, the output exhibits a faster transition.


Discharging Dynamics of CMOS Inverter

Similar to the charging dynamics, the discharge is linear when M1 is in saturation and becomes sublinear as M1 enters triode region.


Rise/Fall Time Delay

Rise Time Delay2 2

22

2

2ln 3 4THL TH

PLHDD TH DD

p ox DD TH

VC VTW V V VC V VL

μ

⎡ ⎤⎛ ⎞= + −⎢ ⎥⎜ ⎟−⎛ ⎞ ⎝ ⎠⎣ ⎦⎡ − ⎤⎜ ⎟ ⎣ ⎦⎝ ⎠

2 VC V⎡ ⎤⎛ ⎞

Fall Time Delay

1 1

11

1

2ln 3 4THL TH

PHLDD TH DD

n ox DD TH

VC VTW V V VC V VL

μ

⎡ ⎤⎛ ⎞= + −⎢ ⎥⎜ ⎟−⎛ ⎞ ⎝ ⎠⎣ ⎦⎡ − ⎤⎜ ⎟ ⎣ ⎦⎝ ⎠


Ex15.21: Averaged Rise Time Delay

1 W⎛ ⎞ ( )222

14AVG p ox DD TH

WI C V VL

μ ⎛ ⎞= −⎜ ⎟⎝ ⎠

( )2/ 2DD DD THL V V VCT− −

=( )

22

22

.PLHDD TH

p ox DD TH

TW V VC V VL

μ=

−⎛ ⎞ −⎜ ⎟⎝ ⎠

2 24

PLH on LT R C≈2 23PLH on L


Ex15.22 Low Threshold Improves Speed

⎡ ⎤⎛ ⎞

1st Term

2 /1 2 /1/

2 /1/ 2 /1

2 /1

2ln 3 4TH THL

PLH HLDD TH DD

p n ox DD TH

V VCTW V V VC V VL

μ

⎡ ⎤⎛ ⎞= + −⎢ ⎥⎜ ⎟−⎛ ⎞ ⎝ ⎠⎣ ⎦⎡ ⎤−⎜ ⎟ ⎣ ⎦⎝ ⎠

22nd Term

The sum of the 1st and 2nd terms of the bracket is the smallest when VTH is the smallest, hence low VTH improves speed.p


Ex15.23: Increased Fall Time Due to Manufacturing Error

1

( )

'1 1 1'

11 1

1|| 2on on ON

n ox DD TH

R R RW WC V VL L

μ

= =⎛ ⎞⎡ ⎤⎛ ⎞ ⎛ ⎞⎜ ⎟+ −⎢ ⎥⎜ ⎟ ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠⎢ ⎥⎣ ⎦⎝ ⎠1 1⎝ ⎠ ⎝ ⎠⎢ ⎥⎣ ⎦⎝ ⎠

Since pull-down resistance is doubled, the fall time is also doubled.


15.2.4 Power Dissipation of the CMOS Inverter

2_

12Dissipation PMOS L DD inP C V f=

21P C V f

2supply L DD inP C V f=

_ 2Dissipation NMOS L DD inP C V f=


Ex15.24: Energy Calculation

21 2

2

12

1

stored L DDE C V

E C V

=

2

22dissipated L DD

drawn L DD

E C V

E C V

=

=


Power Delay Product

2 21 1

1

2ln 3 4THin L DD TH

DD TH DD

Vf C V VPDPW V V VC V Vμ

⎡ ⎤⎛ ⎞= + −⎢ ⎥⎜ ⎟−⎛ ⎞ ⎝ ⎠⎣ ⎦⎡ − ⎤⎜ ⎟ ⎣ ⎦1

1n ox DD THC V V

Lμ ⎝ ⎠⎣ ⎦⎡ − ⎤⎜ ⎟ ⎣ ⎦⎝ ⎠

Ron1=Ron2


Ex15.25: PDP

4 1R ≈3on

n ox DD

RWC VL

μ≈

⎛ ⎞⎜ ⎟⎝ ⎠2 27.25 ox in DD

n

WL C f VPDPμ

=


Crowbar Current

When Vin is between VTH1 and VDD-|VTH2|, both M1 and M2 are on and there will be a current flowing from supply to ground. g s pp y g


15.3 CMOS NOR and NAND GatesNMOS Section of NOR

When either A or B is high or if both A and B are high, the output will be low. Transistors operate as pull-down devices.


Ex15.26: Poor NOR

Th b i it f il t t NOR b h A iThe above circuit fails to act as a NOR because when A is high and B is low, both M4 and M1 are on and produces an ill-defined low.


PMOS Section of NOR

When both A and B are low, the output is high. Transistors operate as pull-up devices.


CMOS NOR

Combing the NMOS and PMOS NOR sections, we have the CMOS NOR.


Ex15.28: Three-Input NOR

( )'outV A B C= + +( )out

Equal Rise & Fall (µn≈2µp)

W1=W2=W3=WW4=W5=W6=6W


Drawback of CMOS NOR

Due to low PMOS mobility, series combination of M3 and M4

suffers from a high resistance, producing a long delay.

The widths of the PMOS transistors can be increased toThe widths of the PMOS transistors can be increased to counter the high resistance, however this would load the preceding stage and the overall delay of the system may not improveimprove.


15.3.2 NMOS NAND Section

When both A and B are high, the output is low.


PMOS NOR Section

When either A or B is low or if both A and B are low, the output is high.


CMOS NAND

Just like the CMOS NOR, the CMOS NAND can be implemented b bi i it ti NMOS d PMOS tiby combining its respective NMOS and PMOS sections, however it has better performance because its PMOS transistors are not in series.


Ex15.29: Three-Input NAND

( )'outV ABC= ( )out

Equal Rise & Fall (µn≈2µp)

W1=W2=W3=3WW4=W5=W6=2W


NMOS and PMOS Duality

C is in “series” with the “parallel” combination of A and B

C is in “parallel” with the “series” combination of A and B“series” combination of A and B

In the CMOS philosophy, the PMOS section can be obtained from the NMOS section by converting series combinations to the parallel combinations and vice versa.


digital cmos circuits (ch. 15)bandi.chungbuk.ac.kr/~ysk/ckt15.pdf · rc vv τ μ == n −...

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