digital design: an embedded systems approach using verilog chapter 2 combinational basics portions...

Digital Design:An Embedded Systems Approach Using Verilog

Chapter 2Combinational Basics

Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

Digital Design — Chapter 2 — Combinational Basics 2

Verilog

Combinational Circuits

Circuits whose outputs depend only on current input values no storage of past input values no state

Can be analyzed using laws of logic Boolean algebra, similar to

propositional calculus


Verilog

Boolean Functions

Functions operating on two-valued inputs giving two-valued outputs 0, implemented as a low voltage level 1, implemented as a high voltage

level Function defines output value for

all possible combinations of input value


Verilog

Truth Tables

Tabular definition of a Boolean function

x y x + y0 0 0

0 1 1

1 0 1

1 1 1

x y0 0 0

0 1 0

1 0 0

1 1 1

x0 1

1 0

yx x

Logical OR Logical AND Logical NOT

OR gate AND gate

inverter


Verilog

Boolean Expressions

Combination of variables, 0 and 1 literals, operators:

cba

Parentheses for order of evaluation Precedence: · before +

cba


Verilog

Boolean Equations

Equality relation between Boolean expressions Often, LHS is a single variable name The Boolean equation then defines a function

of that name Implemented as a combinational circuit

zyxf x

fy

z


Verilog

Boolean Equations

Boolean equations and truth tables are both valid ways to define a function

zyxf x y z f

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Q: How many rows in a truth table for an n-input Boolean function?

Evaluate f for each combination of input values, and fill in table


Verilog

Minterms

Given a truth table For each rows where

function value is 1, form a minterm: AND of

variables where input is 1 NOT of variables where

input is 0 Form OR of minterms

x y z f

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

zyxzyxzyxf


Verilog

P-terms

This is in sum-of-products form logical OR of p-terms (product terms)

Not all p-terms are minterms eg, the following also defines f

zyxzyxzyx

zxzyx


Verilog

Equivalence

These expressions all represent the same Boolean function

zxzyx

zyxzyxzyx

zyxf

The expressions are equivalent Consistent substitution of variable values

gives the same values for the expressions


Verilog

Optimization

Equivalence allows us to optimize choose a different circuit that implements

the same function more cheaply

Caution: smaller gate count is not always better choice depends on constraints that apply

xy

z

xy

z


Verilog

Complex Gates

All Boolean functions can be implemented using AND, OR and NOT But other complex gates may meet

constraints better in some fabrics

NAND NOR

XOR XNOR

AND-OR-INVERT

x y

NOR NAND

XOR XNOR

0 0 1 1 0 1

0 1 0 1 1 0

1 0 0 1 1 0

1 1 0 0 0 1

yx yx yx yx


Verilog

Complex Gate Example

These two expressions are equivalent:

cbaf 1 cbaf 2

The NAND-NOR circuit is much smaller and faster in most fabrics!

abc

f1

ab

c

f2


Verilog

Buffers

Identity function: output = input Needed for high fanout signals


Verilog

Don’t Care Inputs

Used where some inputs don’t affect the value of a function

Example: multiplexers a b z

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

s a b z

0 0 – 0

0 1 – 1

1 – 0 0

1 – 1 1


Verilog

Don’t Care Outputs

For input combinations that can’t arise don’t care if output is 0 or 1 let the synthesis tool choose

a b c f f1 f2

0 0 0 – 0 1

0 0 1 0 0 0

0 1 0 1 1 1

0 1 1 0 0 0

1 0 0 – 0 1

1 0 1 1 1 1

1 1 0 0 0 0

1 1 1 0 0 0

a

b

c

a

a

b

c

f1

f2

f2

c

b0


Verilog

Commutative Laws

Associative Laws

Distributive Laws

Identity Laws

Complement Laws

Boolean Algebra – Axioms

xyyx xyyx

zyxzyx zyxzyx

)()()( zxyxzyx )()()( zxyxzyx

xx 0 xx 1

1 xx 0xx

Dual of a Boolean equation substitute 0 for 1, 1 for 0, + for ·, · for + if original is valid, dual is also valid


Verilog

Hardware Interpretation

Laws imply equivalent circuits Example: Associative Laws

xyz

xyz

xyz

xyz

xyz

x


Verilog

More Useful Laws

Idempotence Laws

Identity Laws

Absorption Laws

DeMorgan Laws

xxx xxx

11x 00x

xyxx )( xyxx )(

yxyx yxyx


Verilog

Circuit Transformation

zyzxyx

zyzxyx

zzyzxyx

zzyzzxyx

zzyyzyzxyx

zyzyzyx

zyzyx

zyzyxf

0

0

0

x

f

yz

x

f

y

z


Verilog

Optimization Methods How do we decide which Law to apply? What are we trying to optimize? Methods

Karnaugh maps, Quine-McClusky minimize gate count

Espresso, Espresso-II, … multi-output minimization

Manual methods are only tractable for small circuits

Useful methods are embedded in EDA tools We just specify constraints


Verilog Boolean Equations in Verilog

Use logical operators in assignment statements

module circuit ( output f, input x, y, z );

assign f = (x | (y & ~z)) & ~(y & z);

endmodule


Verilog

Verilog Logical Operators

Precedence not has highest then &, then ^ and

~^, then | use parentheses to

make order of evaluation clear

Verilog bit values 1'b0 and 1'b1

ba

ba

ba

ba

ba

ba

a

a & b

a | b

~(a & b)

~(a | b)

a ^ b

a ~^ b

~a


Verilog

Boolean Equation Example

Air conditioner control logic heater_on = temp_low · auto_temp +

manual_heat cooler_on = temp_high · auto_temp +

manual_cool fan_on = heater_on + cooler_on + manual_fanmodule aircon ( output heater_on, cooler_on, fan_on,

input temp_low, temp_high, auto_temp, input manual_heat, manual_cool, manual_fan );

assign heater_on = (temp_low & auto_temp) | manual_heat; assign cooler_on = (temp_high & auto_temp) | manual_cool; assign fan_on = heater_on | cooler_on | manual_fan;

endmodule


Verilog

Binary Coding

How do we represent information with more than two possible values? eg, numbers N voltage levels? — No.

Multiple binary signals (multiple bits) (a1, a0): (0, 0), (0, 1), (1, 0), (1, 1)

This is a binary code Each pair of values is a code word Uses two signal wires for a1, a0


Verilog

Code Word Size

An n-bit code has 2n code words To represent N possible values

Need at least log2N code word bits More bits can be useful in some cases

Example: code for inkjet printer black, cyan, magenta, yellow, red, blue six values, log26 = 3 black: (0, 0, 1), cyan: (0, 1, 0), magenta: (0,

1, 1),yellow: (1, 0, 0), red: (1, 0, 1), blue: (1, 1, 0)


Verilog

One-Hot Codes

Each code word has exactly one 1 bit

Traffic light: red: (1,0,0), yellow: (0,1,0), green:

(0,0,1) Three signal wires: red, yellow, green

Each bit of a one-hot code corresponds to an encoded value No hardware needed to decode values


Verilog

Binary Codes in Verilog

Multiple bits represented by a vector

wire [4:0] w; This is a five-element wire w[4], w[3], w[2], w[1], w[0]

wire [1:3] a; This is a three-element wire A[1], a[2], a[3]


Verilog

Binary Coding Example Traffic-light controller with 1-hot code

enable == 1: lights_out = lights_in enable == 0: lights_out = (0, 0, 0)

module light_controller_and_enable ( output [1:3] lights_out, input [1:3] lights_in, input enable );

assign lights_out[1] = lights_in[1] & enable; assign lights_out[2] = lights_in[2] & enable; assign lights_out[3] = lights_in[3] & enable;

endmodule


Verilog

Binary Coding Example

module light_controller_conditional_enable ( output [1:3] lights_out, input [1:3] lights_in, input enable );

assign lights_out = enable ? lights_in : 3'b000;

endmodule


Verilog

Bit Errors

Electrical noise can change logic levels Bit flip: 0 → 1, 1 → 0

If flipped signal is in a code word result may be a different code word or an invalid code word inkjet printer, blue: (1, 1, 0) → ?: (1, 1, 1)

Could ignore the possibility of a bit flip don’t specify behavior of circuit ok if probability is low, effect isn’t

disastrous, and application is cost sensitive


Verilog

Fail-Safe Design

Detect illegal code words produce a safe result

Traffic-light controller with 1-hot code illegal code red light

s_greens_yellows_redgreen

s_greens_yellows_redyellow

yellowgreens_greens_yellows_redred


Verilog

Redundant Codes

Include extra error code words each differs from a valid code word by

a bit-flip ensure no two valid code words are a

bit-flip apart Detect error code words

take exceptional action eg, stop, error light, etc


Verilog

Parity Extend a code word with a parity bit Even parity: even number of 1 bits

001010110, 100100011 Odd parity: odd number of 1 bits

001010111, 100100010 To check for bit flip, count the 1s

even parity: 001010110 → 000010110 What if there are two bit flips?

even parity: 001010110 → 000110110


Verilog

Parity Using XOR Gates

XOR gives even parity for two bits extends to multiple bits, associatively

a0

a1

a2

a3

a4

a5

a6

a7

a0

a1

a2

a3

a4

a5

a6

a7

p

error


Verilog Combinational Components

We can build complex combination components from gates Decoders, encoders Multiplexers …

Use them as subcomponents of larger systems Abstraction and reuse


Verilog

Decoders

A decoder derives control signals from a binary coded signal One per code word Control signal is 1 when input has the

corresponding code word; 0 otherwise

For an n-bit code input Decoder has 2n outputs

Example: (a3, a2, a1, a1) Output for (1, 0, 1, 1): 012311 aaaay

a0a1a2

y0y1y2y3y4

… …

y15

a3


Verilog

Decoder ExampleColor Codeword (c2, c1, c0)

black 0, 0, 1

cyan 0, 1, 0

magenta 0, 1, 1

yellow 1, 0, 0

red 1, 0, 1

blue 1, 1, 0


Verilog

Decoder Example

module ink_jet_decoder ( output black, cyan, magenta, yellow, light_cyan, light_magenta, input color2, color1, color0 );

assign black = ~color2 & ~color1 & color0; assign cyan = ~color2 & color1 & ~color0; assign magenta = ~color2 & color1 & color0; assign yellow = color2 & ~color1 & ~color0; assign light_cyan = color2 & ~color1 & color0; assign light_magenta = color2 & color1 & ~color0;

endmodule


Verilog

Encoders

An encoder encodes which of several inputs is 1 Assuming (for now) at

most one input is 1 at a time

What if no input is 1? Separate output to

indicate this condition

a0a1a2

y0y1y2y3

… … valid

a3a4

a15


Verilog

Encoder Example

Burglar alarm: encode which zone is active

Zone Codeword

Zone 1 0, 0, 0

Zone 2 0, 0, 1

Zone 3 0, 1, 0

Zone 4 0, 1, 1

Zone 5 1, 0, 0

Zone 6 1, 0, 1

Zone 7 1, 1, 0

Zone 8 1, 1, 1


Verilog

Priority Encoders

If more than one input can be 1 Encode input that is 1 with highest priority

zone intruder_zone valid

(1) (2) (3) (4) (5) (6) (7) (8) (2) (1) (0)

1 – – – – – – – 0 0 0 1

0 1 – – – – – – 0 0 1 1

0 0 1 – – – – – 0 1 0 1

0 0 0 1 – – – – 0 1 1 1

0 0 0 0 1 – – – 1 0 0 1

0 0 0 0 0 1 – – 1 0 1 1

0 0 0 0 0 0 1 – 1 1 0 1

0 0 0 0 0 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 – – – 0


Verilog

Priority Encoder Example

module alarm_priority_1 ( output [2:0] intruder_zone, output valid, input [1:8] zone );

assign intruder_zone = zone[1] ? 3'b000 : zone[2] ? 3'b001 : zone[3] ? 3'b010 : zone[4] ? 3'b011 : zone[5] ? 3'b100 : zone[6] ? 3'b101 : zone[7] ? 3'b110 : zone[8] ? 3'b111 : 3'b000;

assign valid = zone[1] | zone[2] | zone[3] | zone[4] | zone[5] | zone[6] | zone[7] | zone[8];

endmodule


Verilog

BCD Code

Binary coded decimal 4-bit code for decimal digits

0: 0000 1: 0001 2: 0010 3: 0011 4: 0100

5: 0101 6: 0110 7: 0111 8: 1000 9: 1001


Verilog

Seven-Segment Decoder

Decodes BCD to drive a 7-segment LED or LCD display digit Segments: (g, f, e, d, c, b, a)

a

b

cde

f g 0111111 0000110 1011011 1001111 1100110

1101101 1111101 0000111 1111111 1101111


Verilog

Seven-Segment Decoder

module seven_seg_decoder ( output [7:1] seg, input [3:0] bcd, input blank );

reg [7:1] seg_tmp;

always @* case (bcd) 4'b0000: seg_tmp = 7'b0111111; // 0 4'b0001: seg_tmp = 7'b0000110; // 1 4'b0010: seg_tmp = 7'b1011011; // 2 4'b0011: seg_tmp = 7'b1001111; // 3 4'b0100: seg_tmp = 7'b1100110; // 4 4'b0101: seg_tmp = 7'b1101101; // 5 4'b0110: seg_tmp = 7'b1111101; // 6 4'b0111: seg_tmp = 7'b0000111; // 7 4'b1000: seg_tmp = 7'b1111111; // 8 4'b1001: seg_tmp = 7'b1101111; // 9 default: seg_tmp = 7'b1000000; // "-" for invalid code endcase

assign seg = blank ? 7'b0000000 : seg_tmp;

endmodule


Verilog

Multiplexers

Chooses between data inputs based on the select input

2-to-1 mux

sel z

0 a0

1 a1

4-to-1 mux

sel z

00 a0

01 a1

10 a2

11 a3

two select bits

N-to-1 multiplexer needs log2 N select bits

0

1

0123

2


Verilog

Multiplexer Example

module multiplexer_4_to_1 ( output reg z, input [3:0] a, input sel );

always @* case (sel) 2'b00: z = a[0]; 2'b01: z = a[1]; 2'b10: z = a[2]; 2'b11: z = a[3]; endcase

endmodule


Verilog

Multi-bit Multiplexers

To select between Nm-bit codeword inputs Connect m N-input

multiplexers in parallel

Abstraction Treat this as a

component

0

1

0

1

0

1

0

1

a0(0)a1(0)

z(0)

a0 3

33

a1z

a0(1)a1(1)

z(1)

a0(2)a1(2)sel

sel

z(2)


Verilog

Multi-bit Mux Example

module multiplexer_3bit_2_to_1 ( output [2:0] z, input [2:0] a0, a1, input sel );

assign z = sel ? a1 : a0;

endmodule


Verilog

Active-Low Logic

We’ve been using active-high logic 0 (low voltage): falsehood of a condition 1 (high voltage): truth of a condition

Active-low logic logic 0 (low voltage): truth of a condition 1 (high voltage): falsehood of a condition reverses the representation, not negative

voltage! In circuit schematics, label active-low signals

with overbar notation eg, lamp_lit: low when lit, high when not lit


Verilog

Active-Low Example

Night-light circuit, lamp connected to power supply

Match bubbles with active-low

signals to preserve logic

sense

Overbar indicates active-

low

lamp_enabled

dark

lamp_lit

sensor

+V +V


Verilog

Implied Negation

Negation implied by connecting An active-low signal to an active-high input/output An active-high signal to an active-low input/output

Negation implied

lamp_enabled

light

lamp_lit

sensor

+V


Verilog Active-Low Signals and Gates

DeMorgan’s laws suggest alternate views for gates They’re the same electrical circuit! Use the view that best represents the

logical function intended Match the bubbles, unless implied

negation is intended


Verilog

Active-Low Logic in Verilog

Can’t draw an overbar in Verilog Use _N suffix on signal or port name

1'b0 and 1'b1 in Verilog mean low and high

For active-low logic 1'b0 means the condition is true 1'b1 means the condition is false

Example assign lamp_lit_N = 1'b0; turns the lamp on


Verilog

Combinational Verification

Combination circuits: outputs are a function of inputs Functional verification: making sure

it's the right function!

Design UnderVerification

(DUV)Apply

Test Cases Checker

Verification Testbench


Verilog

Verification Example

Verify operation of traffic-light controller

Property to check enable lights_out == lights_in !enable all lights are inactive

Represent this as an assertion in the checker


Verilog

Testbench Module

`timescale 1ms/1ms

module light_testbench;

wire [1:3] lights_out; reg [1:3] lights_in; reg enable;

light_controller_and_enable duv ( .lights_out(lights_out), .lights_in(lights_in), .enable(enable) );


Verilog

Applying Test Cases

initial begin enable = 0; lights_in = 3'b000; #1000 enable = 0; lights_in = 3'b001; #1000 enable = 0; lights_in = 3'b010; #1000 enable = 0; lights_in = 3'b100; #1000 enable = 1; lights_in = 3'b001; #1000 enable = 1; lights_in = 3'b010; #1000 enable = 1; lights_in = 3'b100; #1000 enable = 1; lights_in = 3'b000; #1000 enable = 1; lights_in = 3'b111; #1000 $finish; end


Verilog

Checking Assertions

always @(enable or lights_in) begin #10 if (!( ( enable && lights_out == lights_in) || (!enable && lights_out == 3'b000) )) $display("Error in light controller output"); end

endmodule


Verilog

Functional Coverage

Did we test all possible input cases? For large designs, exhaustive

testing is not tractable N inputs: number of cases = 2N

Functional coverage Proportion of test cases covered by a

testbench It can be hard to decide how much

testing is enough


Verilog

Summary

Combinational logic: output values depend only on current input values

Boolean functions: defined by truth tables and Boolean equations

Equivalence of functions optimization

Binary codes used to represent information with more than two values


Verilog

Summary

Combinational components gates: AND, OR, inverter, 2-to-1 mux complex gates: NAND, NOR, XOR,

XNOR, AOI decoder, encoder, priority encoder

Active-low logic Verification testbench

apply test cases to DUV checker contains assertions

digital design: an embedded systems approach using verilog chapter 2 combinational basics portions...

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