eng2410 digital design: week #4 “combinational logic...
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ENG2410Digital Design: Week #4“Combinational Logic
Design”
S. AreibiSchool of EngineeringUniversity of Guelph
Week #4: Topics
Decoders Combinational circuit Implementation
Encoders Priority Encoders
Multiplexers Combinational Circuit Implementation
Demultiplexers
Resources
Chapter #4, Mano Sections 4.1 Combinational Circuits 4.3 Decoding 4.4 Encoding 4.5 Multiplexers 4.6 Comb Function Implementations
4
Central Processing Unit (CPU)
Any CPU consists of two main parts:• Datapath Unit: Arithmetic/Logic Operation
• Control Unit: Sends control signals to datapth to perform certain operations.
Controlunit DatapathCPU
Data/Instructions/codeAll in 01010010010
clock
Memory
Input/Output
Decoders and Multiplexors
Decoders and Multiplexors are important components and fundamental circuits that are found in any Central Processing Unit (CPU)
CPU Datapath
• Multiplexors are used to select certain registers to act as operands (inputs) to the Arithmetic/Logic Unit
• Decoders are used to enable registers to write the results back into the registers.
Decoders
Devices on a Bus
7
Device #0
Device #1
Device #2
Device #3
ControlUnit
Assume we have 4 devices that needs to put its data on a Bus Only one device has to be active at a time (i.e. writes info on the bus)! 4 control signals “wires” from the Control Unit are needed to enable each device If more devices are to be attached to the bus then we will need many more wires!!
BUS
Enable
Disable
Disable
Disable
Address Decoding
8
Device #0
Device #1
Device #2
Device #3
ControlUnit
4 devices need to write data to the Bus Only one device has to be active at a time! But! only 2 wires available from control unit
BUS
1
00
0
0
0
0
10
100
Truth Table
9
Decoders
Are circuits with n inputs and 2n outputs Drives high the output corresponding to binary
code of input Several Applications: Address Decoding, …
A
D0
D1
10
2-to-4 Line Decoder
Notice they are minterms
Inputs Outputs
Plane of AND Gates
11
Other DecodersExamples: 3-to-8 Decoder 4-to-16 Decoder
3-to-8Line
Decoder4-to-16
LineDecoder
3 8
Binary to Octal, Binary to Hex, e.t.c
4 16
12
Truth Table, 3-to-8 Decoder
Notice they are minterms
Example: Binary to Octal, Binary to Hex, e.t.c
3-to-8Line
Decoder
Binary to Octal,
A0
A1
A2
13
3-to-8 Line Decoder Schematic
14
2-to-4 with Enable
Why use an Enable?
15
Enable Used for ExpansionA1A2 A0
0
0
00
0
0
0
1
1
11
1
1
1
0
0
0
0
01
1
1
1
1 0 1
0
1
1
0
A 3-to-8 Decoder can be realized using two2-to-4 line decoders with an enable
16
Usage for Decoders
Binary to Octal/Hex converters. Selecting memory banks, for example 4
memory banks can be selected individually using 2 address lines.
Implementing logic circuits! Decoders are used in Micro Computer
Interfacing for Keyboard and Display applications.
Address Decoding
17
Memory Bank #1
Memory Bank #2
Memory Bank #3
Memory Bank #4
CPU
Decoders: Logic Implementation
19
Decoder generates appropriateminterm based on control signals
(it "decodes" control signals)
Decoders as General-purpose Logic
n:2n decoder implements any function of n variables With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function
20
Decoders as General-purpose Logic
Example: Implement the following Boolean functions 1. S(A2,A1,A0) = SUM(m(1,2,4,7))
2. C(A2,A1,A0) = SUM(m(3,5,6,7))
1. Since there are three inputs, we need a 3-to-8 line decoder.
2. The decoder generates the eight minterms for inputs A0,A1,A2
3. We choose only the minterms that we need for a function (S) or (C)
4. An OR GATE forms the logical sum mintermsrequired.
21
Decoders as General-purpose Logic
S(A2,A1,A0) = SUM(m(1,2,4,7))
S
22
Decoders as General-purpose Logic
C(A2,A1,A0) = SUM(m(3,5,6,7))
C
A Single Decoder can implement both “S” and “C” with two OR Gates
23
F1
Example F1 = A' B C' D + A' B' C D + A B C D
A B
0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD
4:16DECEnable
C D
o F1(A,B,C,D) = SUM(m(3,5,15))Therefore, we will need a 4-to-16 line decoder
23 2122 20
Need to show that variable A (MSB) needsto be connected to MSB of the Decoder
Encoders
25
Encoder
Encoder is the opposite of decoder 2n inputs (or less – maybe BCD in) n outputs
Examples: Octal to binary conversion Hexadecimal to binary conversion
26
Octal to Binary EncoderYou can think of the inputs as the 8 Octal digits
Only one input is active at a time
27
Design of Encoder
A0 = D1 + D3 + D5 + D7
Multiplexors
29
Multiplexer (or Mux)
Selects one of a set of inputs to pass on to output
For Every 2n inputs we need n select lines
Applications: Useful for choosing from sets of data Memory or register to ALU
MUX
In0In1
In2
In3
Out
S0 S1
Multiplexors
The Multiplexor in the register file allows one of the four registers R0, R1, R2, R3 to move its contents to the Function Unit
The Multiplexor in the Function Unit allows the user to choose between the ALUand Shifter to move data back to the Register File.
31
2-Input MultiplexerStructure:
A Plane of AND Gates
Followed by an OR Gate
32
4-to-1 Line Multiplexer
33
Quad 2-to-4 Line Mux Select one set
of 4 lines
Multiplexors: Logic Implementation
35
Implementing Logico 2n:1 multiplexer implements any function of n variables
1. With the variables used as control inputs and2. Data inputs tied to 0 or 13. In essence, a lookup table
o Example: F(A,B) = m0 + m2= A'B' + AB’
A B F0 0 10 1 01 0 11 1 0
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CA B
10100011
01234567S2
8:1 MUX
S1 S0
F
Muxes as General-purpose Logic
o 2n:1 multiplexer implements any function of n variables1. With the variables used as control inputs and2. Data inputs tied to 0 or 13. In essence, a lookup table
o Example: F(A,B,C) = m0 + m2 + m6 + m7= A'B'C' + A'BC' + ABC' + ABC
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
37
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
F
CA B
01234567
10100011
S2
8:1 MUX
S1 S0
2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement
Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
Muxes as General-purpose Logic
Not OptimizedHow to use a 4:1 MUX Instead?
Use inputs A, B as the selection lines for the 4:1 MUX since we will only have two selection lines
Find a relationship between C (the third input) and F
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A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
C'
C'
0
1 A B
S1 S0
F0123
4:1 MUXC'C'01
F
CA B
01234567
10100011
S2
8:1 MUX
S1 S0
2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement
Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
Muxes as General-purpose Logic
Not Optimized OptimizedHow to use a 4:1 MUX Instead?
Demultiplexors
40
Demultiplexer
Takes one input out to one of 2n possible outputs
VHDL Implementations
42
entity dec_2_to_4 isport (
A0, A1: in std_logic;D0, D1, D2, D3: out std_logic);
end entity dec_2_to_4;
Decoder: (VHDL Data Flow) Example: 2-to-4 decoder
D0
D1
D2
D3
A(1)
A(0)
Inte
rface
A0_n A1_n
architecture dataflow1 of dec_2_to_4 is
Signal A0_n, A1_n: std_logic;begin
A0_n <= not A0;A1_n <= not A1;D0 <= A0_n and A1_n;D1 <= A0 and A1_n;D2 <= A0_n and A1;D3 <= A0 and A1;
end architecture dataflow1;Fu
nctio
nalit
y
43
mux: Y <= D0 when S1 = ‘0’ and S0 = ‘0’ elseD1 when S1 = ‘0’ and S0 = ‘1’ elseD2 when S1 = ‘1’ and S0 = ‘0’ elseD3;
When Else Statement
44
VHDL of 4-to-1 Multiplexer using When/Else
-- 4-to-1 Line Mux; Conditional Dataflow VHDL Descriplibrary ieee;use ieee.std_logic_1164.all
entity multiplexer_4_to_1 isport (S: in std_logic_vector(1 downto 0);
D: in std_logic_vector(3 downto 0);Y: out std_logic;
end multiplexer_4_to_1;
45
Cont .. Dataflow VHDL Description
architecture function_table of multiplexer_4_to_1 is-- Using When Else
BeginY <= D(0) when S = “00” else
D(1) when S = “01” elseD(2) when S = “10” elseD(3) when S = “11” else`X’;
end function_table;
46
entity dec_2_to_4 isport (
A : in std_logic_vector(1 downto 0);D : out std_logic_vector(3 downto 0)
);end entity dec_2_to_4;
architecture dataflow2 of dec_2_to_4 isbegin
D <= "0001" when A = "00" else"0010" when A = "01" else"0100" when A = "10" else"1000" when A = "11" else"XXXX";
end architecture dataflow2;
Decoder: Data Flow #2Example: 2-to-4 decoder
D(0)
D(1)
D(2)
D(3)A(1)
A(0)
Inte
rface
Func
tiona
lity
A(1..0) D(3..0)
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
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VHDL Design Styles
Components andinterconnects
structural
VHDL Design Styles
dataflow
Concurrent statements
behavioral(algorithmic)
• Registers• State machines• Test benches
Sequential statements
Subset most suitable for synthesis
48
Structural VHDL Description of 2-to-4 Line Decoder
49
Structural VHDL Description“Entity Declaration”
-- 2-to-4 Line Decoder; structural VHDL Descriptionlibrary ieee;use ieee.std_logic_1164.all
entity decoder_2_4_w_enable isport (EN, A0, A1 : in std_logic;
D0, D1, D2, D3 : out std_logic);end decoder_2_to_4_w_enable;
50
Structural VHDL Description (Signals)
A0_nA1_n
N0
N3
N1
N2
51
Structural VHDL Description (Components)
architecture structural1_1 of decoder_2_to_4_w_enable is
component NOT1port(in1: in std_logic;
out1: out std_logic);end component;
component AND2port(in1, in2: in std_logic;
out1: out std_logic);end component;
52
Structural VHDL Description(Connecting components)
architecture structural1_1 of decoder_2_to_4_w_enable is-- component NOT1 declaration-- component NAND2 declarationsignal A0_n, A1_n, N0, N1, N2, N3: std_logic;
beging0: NOT1 port map (in1 => A0, out1 => A0_n);g1: NOT1 port map (in1 => A1, out1 => A1_n);………………
end structural_1;
A0_n
A1_n
component NOT1port(in1: in std_logic;
out1: out std_logic);end component;
53
Structural VHDL Description(Connecting components)
architecture structural1_1 of decoder_2_to_4_w_enable is-- component NOT1 declaration-- component NAND2 declarationsignal A0_n, A1_n, N0, N1, N2, N3: std_logic;
beging0: NOT1 port map (in1 => A0, out1 => A0_n);g1: NOT1 port map (in1 => A1, out1 => A1_n);g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0);g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1);g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2);g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3);g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0);g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1);g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2);g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);
end structural_1;
54
2-to-4 Line Decoder: Complete Design
architecture structural1_1 of decoder_2_to_4_w_enable is-- component NOT1 declaration-- component NAND2signal A0_n, A1_n, N0, N1, N2, N3: std_logic;begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);g1: NOT1 port map (in1 => A1, out1 => A1_n);
g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0);g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1);g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2);g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3);
g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0);g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1);g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2);g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);
end structural_1;
A0_n
A1_n
-- 2-to-4 Line Decoder; structural VHDL Descriptionlibrary ieee;use ieee.std_logic_1164.all
entity decoder_2_4_w_enable isport (EN, A0, A1 : in std_logic;
D0, D1, D2, D3 : out std_logic);end decoder_2_to_4_w_enable;
56
Revisiting Encoder!! Why?
Only ONE input is allowed to be active at a time!
57
What’s the Problem?
What if D3 and D6 both high? Simple OR circuit will set A to 111 This is an issue!!!! Solution?
58
Priority Encoder
Chooses one with highest priority Largest number, usually
“X” in input == 0 or 1 compact Truth Table
59
Unfolding the Compact Truth Table
D3 D2 D1 D0 A1 A0
0 0 1 0 0 10 0 0 1 0 0
0 0 1 1 0 1
What if all inputs are zero?
60
Need Another Output!
A Valid Output!
61
Expanded Truth Table (A0)
D3 D2 D1 D0 A0
0 0 0 0 X
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
x 0 1 10 0 0 01 1 1 11 1 1 1
00 01 11 10
000111
10
D3D2
D1D0
A0 = D3 + D2D1
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Valid is OR of all inputs
63
Structural VHDL Descriptionof 4-to-1 Line Multiplexer
N(0:3)D(0:3)S_n(0:1)
64
Cont .. Structural VHDL Descriptionof 4-to-1 Multiplexer
-- 4-to-1 Line Multiplexer; structural VHDL Descriptionlibrary ieee;use ieee.std_logic_1164.all
entity multiplexer_4_to_1_st isport (S: in std_logic_vector(0 to 1);
I: in std_logic_vector(0 to 3);Y: out std_logic;
end multiplexer_4_to_1_st;
65
Cont .. Structural VHDL Descriptionof 4-to-1 Multiplexer
architecture structural_2 of multiplexer_4_to_1_st iscomponent NOT1port(in1: in std_logic;
out1: out std_logic);end component;
component AND2port(in1, in2: in std_logic;
out1: out std_logic);end component;
component OR4port(in1, in2, in3, in4: in std_logic;
out1: out std_logic);end component;
66
Cont .. Structural VHDL Descriptionof 4-to-1 Multiplexer
architecture structural_2 of multiplexer_4_to_1_st is-- component NOT1 AND2 OR4 declarations
signal S_n : std_logic(0 to 1);signal D, N : std_logic_vector(0 to 3);begin
g0: NOT1 port map (S(0), S_n(0));g1: NOT1 port map (S(1), S_n(1));g2: AND2 port map (S_n(1), S_n(0), D(0));g3: AND2 port map (S_n(1),S(0), D(1));g4: AND2 port map (S(1),S(0), D(3));g5: AND2 port map (S(1), S(0), D(3));g6: AND2 port map (D(0), I(0), N(0));g7: AND2 port map (D(1),I(1), N(1));g8: AND2 port map (D(2),I(2),N(2));g9: AND2 port map (D(3),I(3), N(3));g10: OR4 port map (N(0), N(1), N(2), N(3), Y);
end structural_2;