digital microelectronic circuits · 2017-09-28 · sequential logic the vlsi systems center - bgu...
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Sequential logic The VLSI Systems Center - BGU 1
Digital Microelectronic
Circuits
(361-1-3021 )
Sequential LogicCircuits and Memories
Presented by: Adam Teman
Lecture 12:
Sequential logic The VLSI Systems Center - BGU
Last Lecture
Dynamic Logic
» Features and Problems
» Domino Logic
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Sequential logic The VLSI Systems Center - BGU
This Lecture
An introduction to sequential circuits and
semiconductor memory, focusing on the
circuit level implementation of basic gates
and cells.
A much more in-depth study of these circuits
will be given in Introduction to VLSI.
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Sequential logic The VLSI Systems Center - BGU
What will we learn today?
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11.1 The Latch
11.2 The Flip Flop
11.3 Read Only Memory
11.4 SRAM
11.5 DRAM
Sequential logic The VLSI Systems Center - BGU 5
Sequential Logic
COMBINATIONALLOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
Sequential logic The VLSI Systems Center - BGU
Memory Hierarchy
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Sequential logic The VLSI Systems Center - BGU
LATCH
The basic sequential timing element is the
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11.111.1 The Latch
11.2 The Flip Flop
11.3 Read Only Memory
11.4 SRAM
11.5 DRAM
Sequential logic The VLSI Systems Center - BGU
Latch
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Clk D Q
0 0 Hold
0 1 Hold
1 0 0
1 1 1
Sequential logic The VLSI Systems Center - BGU
Basic Static Latch
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Clk D Q
0 0 Hold
0 1 Hold
1 0 0
1 1 1
Sequential logic The VLSI Systems Center - BGU
Feedback Mux Latch
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Clk D Q
0 0 Hold
0 1 Hold
1 0 0
1 1 1
Sequential logic The VLSI Systems Center - BGU
Simple Dynamic Latch
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Sequential logic The VLSI Systems Center - BGU
C2MOS
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Sequential logic The VLSI Systems Center - BGU
TSPC
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Sequential logic The VLSI Systems Center - BGU
FLIP FLOP
The most important timing element in synchronous systems is the
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11.211.1 The Latch
11.2 The Flip Flop
11.3 Read Only Memory
11.4 SRAM
11.5 DRAM
Sequential logic The VLSI Systems Center - BGU
Flip Flop = Register
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Clk D Q
01 0 0
01 1 1
0 X Hold
1 X Hold
Sequential logic The VLSI Systems Center - BGU 16
Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge
Also called master-slave latch pair
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Master-Slave Register
Multiplexer-based latch pair
Clock load – 8 transistors
QM
Q
D
CLK
T 2I2
T 1I1
I3 T 4I5
T 3I4
I6
Sequential logic The VLSI Systems Center - BGU
C2MOS Register
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Sequential logic The VLSI Systems Center - BGU
Pulse Triggered Register
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Sequential logic The VLSI Systems Center - BGU
READ ONLY MEMORY
Now we are ready to look at the basic memory array:
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11.311.1 The Latch
11.2 The Flip Flop
11.3 Read Only Memory
11.4 SRAM
11.5 DRAM
Sequential logic The VLSI Systems Center - BGU
Memory Architecture
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Sequential logic The VLSI Systems Center - BGU 22
Read-Only Memory Cells
1
0
WL
BL
WL
BL
Diode ROM
WL
BL
WL
BL
VDD
MOS ROM 1
WL
BL
WL
BL
GND
MOS ROM 2
Sequential logic The VLSI Systems Center - BGU
MOS NOR ROM
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Sequential logic The VLSI Systems Center - BGU 24
Precharged MOS NOR ROM
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MOS NAND ROM
All word lines high by default with exception of selected row
Sequential logic The VLSI Systems Center - BGU
STATIC RANDOM ACCESS MEMORY
Most embedded memories are implemented with
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11.411.1 The Latch
11.2 The Flip Flop
11.3 Read Only Memory
11.4 SRAM
11.5 DRAM
Sequential logic The VLSI Systems Center - BGU
Random Access Memories
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Sequential logic The VLSI Systems Center - BGU
Basic Static Memory Element
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Sequential logic The VLSI Systems Center - BGU
Positive Feedback: Bi-Stability
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Sequential logic The VLSI Systems Center - BGU
Memory Cell
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Sequential logic The VLSI Systems Center - BGU 31
6-transistor CMOS SRAM Cell
WL
BL
VDD
M5M6
M4
M1
M2
M3
BL
Sequential logic The VLSI Systems Center - BGU
SRAM Operation - Read
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Sequential logic The VLSI Systems Center - BGU
SRAM Operation - Write
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Sequential logic The VLSI Systems Center - BGU
DYNAMIC RANDOM ACCESS MEMORY
How about reducing the number of transistors to achieve high
density…
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11.511.1 The Latch
11.2 The Flip Flop
11.3 Read Only Memory
11.4 SRAM
11.5 DRAM
Sequential logic The VLSI Systems Center - BGU
3-Transistor DRAM Cell
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Sequential logic The VLSI Systems Center - BGU
1-Transistor DRAM Cell
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Sequential logic The VLSI Systems Center - BGU
1-Transistor DRAM Cell
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