lec nnaik sequential circuits

8/12/2019 Lec Nnaik Sequential Circuits

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Sequential Circuit Design -1

Flip Flop / Latch

ESc201 : Introduction to Electronics

1


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Digital Circuits

Combinational Circuits Sequential Circuits

CC

X

Y

W

Output is determined bycurrent values of inputs only.

CC

Storageelements

X Z

Output is determined in general

by current values of inputs and

past values of inputs/outputs as

well. 2


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NOR SR Latch

Q

Q

R

S

1; 0 Set StateQ Q

0; 1 Re et StateQ Q s 1

0

0

0

1

1 0 1 0

S R Q Q State

SET

3


4/27

NOR SR Latch

Q

Q

R

S

1; 0 Set StateQ Q

0; 1 Re et StateQ Q s

1

0

0

0 1

1 0 1 0

S R Q Q State

SET

0 1 0 1 RESET

Reset

Set

4


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Q

QR

S

HOLD State

0

0

S R Q Q State

1 0 1 0 SET

0 1 0 1 RESET

0 0 HOLD

1

1

0

Q Q

1 1 0 0 INVALID

5


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Q

QR

S

1

1

0

0

Both the outputs are well defined and 0.

The first problem is that we do not get

complementary output.

A more serious problem occurs when we switch the latch to the hold state by

changing RS from 11 00 . Suppose the inputs do not change

simultaneously and we get the situation 1101*00

Q

QR

SQ

QR

SQ

QR

S

1

1

0

0

0

1

1

0

0

0

1

0

Q = 1 6


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Q

QR

SQ

QR

SQ

QR

S

1

1

0

0

0

1

1

0

0

0

1

0

Q = 1

Q

QR

SQ

QR

SQ

QR

S

1

1

0

0

1

0

0

1

0

0

0

1

Q = 0

Suppose the inputs change as RS = 11 10*00

So although output is well defined when we apply RS = 11, it becomes

unpredictable once we switch the latch to hold state by applying RS = 00. Thatis why RS = 11 is not used as an input combination.

7


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The error can occur also due to unequal gate delays.

Q

QR

S

1

2

1

1

0

0Q

QR

S

1

2

0

0

0

0

Suppose gate-1 is faster

Q

QR

S

1

2

0

0

1

0

0

Q = 1

On the other hand suppose that gate-2 is faster.

Q

Q

R

S

1

2

1

1

0

0Q

Q

R

S

1

2

0

0

0

0 Q

QR

S

1

2

0

01

0

0

Q = 0Again the output is unpredictable in general 8


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NAND Latch

Q

Q

R

S

S R Q Q State

0 1 1 0 SET

1 0 0 1 RESET

1 1 HOLDQ Q

0 0 1 1 INVALID

9


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RS NAND Latch with Enable

Q

Q

R

S

EN0

1

1

Hold State

Q

Q

R

S

EN

1

S

R

Enable StateS R Q Q

0

1

1

1

1

Hold

Set

Reset

Hold

Invalid

x x

1 0 1 0

0 1 0 1

Q Q

Q Q

1 1

0 0

0 0

10


11/27

D latch

Q

Q

S

R

QS

R Q

D

ENEN

Enable StateS R Q Q

0

1

1

1

1

Hold

Set

Reset

Hold

Invalid

x x

1 0 1 0

0 1 0 1

Q Q

Q Q

1 1

0 0

0 0

1 1

0

0

1

If EN = 1 then Q = D otherwise the latch is in Hold state

1

Q

Q

D

EN

11


12/27

Problem with Latch

QD

clk

zn

yn

1

1

Circuits are designed with the idea there would be single change in output

or memory state in single clock cycle.

clk

y

z

12


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Edge Triggered Latch or Flip-flop

QD

clk

Clock

D

Positive edge triggered flipflop 13


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Negative Edge Triggered Latch or Flip-flop

QD

clk

Clock

D

14


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Master-Slave D Flip-flop

EN

Q

Q

D

EN

DD

clk

slavemaster

Clock

D

Master

Slave

QD

clk

How do convert this into a positive edge triggered D flip-flop?15

P iti d t i d D Fli fl


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Q

1

2

3

4

5

6

Q

S

R

D

clk

Positive edge triggered D Flip-flop

0

1

0

0

1

1

0

1

1

0

0

1

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Q

1

2

3

4

5

6

Q

S

R

D

clk


0

1

1

0

1

1

1

0

1

01

0

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Q

1

2

3

4

5

6

Q

S

R

D

clk


1

0

1

1

0

1

1

00 1

A change in input has no effect if it occurs after the clock edge18

JK Fli fl


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19

JK Flip-flop

Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 11 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

)()()1( tQKtQJtQ

JK flip flop is refinement of RS flip

flop where indeterminate state of RS

flip flop is defined in JK Flip Flop.

T l T Fli fl


20/27

20

Toggle or T Flip-flop

)()1( tQTtQ

Q T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Ch t i ti t bl


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Characteristic table

QD

clk

Q(t+1)Inputs (D)

0 0

1 1

Q

clk

J

K

Q(t+1)InputsJK Flip-flop

J K

0 0 Q(t)

00 1

1 0 1

1 1 Q(t)

Given a input and the present state of the flip-flop, what is the next state of

the flip-flop

DtQ )1(Characteristic equation:

)()()1( tQKtQJtQ Characteristic equation:

D Flip-flop

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Q

clk

T

Q(t+1)Inputs (T)

0 Q(t)

1

Toggle or T Flip-flop

Q(t)

Excitation TableWhat inputs are required to effect a particular state change

)()1( tQTtQ Characteristic equation:

Inputs

0 0

0 1

1 0

1 1

Q(t+1)Q(t) T

0

0

1

1

Q T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Excitation Table

22

E it ti T bl


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Excitation Table

Q

clk

J

K

J K Q(t+1)

Q(t)0 0

0 1

1 0

1 1 Q(t)

0

1

Inputs

0 0

0 1

1 0

1 1

Q(t+1)Q(t)

X 0

J K

0 X

1 X

X 1

Characteristic Table

Excitation Table

Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0 23

E it ti T bl


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Excitation Table

QD

clk

Q(t+1)D

0 0

1 1

Inputs

0 0

0 1

1 0

1 1

Q(t+1)Q(t) D

0

1

0

1

Characteristic Table

Excitation Table

Q D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

24

C t D FF t JK FF


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Convert a D FF to JK FF

clk

QD

K

CC

J

J K Q Q(t+1) D

0 0

0 1

1 0

1 1

0 X

1 X

X 1

X 0

0

1

0

1

Inputs

0 0

0 1

1 0

1 1

Q(t+1)Q(t)

X 0

J K

0 X1 X

X 1

Excitation Table

Inputs

0 0

0 1

1 0

1 1

Q(t+1)Q(t) D

01

0

1

Excitation Table 25



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clk

QD

K

CC

J

. .D Q J Q K

J K Q Q(t+1) D

0 0

0 1

1 0

1 1

1 1

1

0 X

1

1 X

X 1

X 0

0

1

0

1

26



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. .D Q J Q K Q J K D Q(t+1)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Q(t+1)Inputs J K

0 0 Q(t)00 1

1 0 1

1 1 Q(t)

0 0

0 0

1 1

1 1

1 1

0 0

1 1

0 0

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lec nnaik sequential circuits

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